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target: convert 'unsigned' to 'unsigned int'

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Conversion done with
	checkpatch --fix-inplace -types UNSPECIFIED_INT

Ignore the cast as they could be better addressed.
Fix only minor additional checkpatch issue (spacing and line
length).

Use Checkpatch-ignore below for the function pointers in the file
'armv7a_cache_l2x.h' that do not assign the identifier names to
the function arguments.
Most of these struct are unused and should be fixed or dropped.

Checkpatch-ignore: FUNCTION_ARGUMENTS

Change-Id: I8f27e68eb3502e431c1ba801b362358105f9f2dc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8480
Tested-by: jenkins
Reviewed-by: zapb <dev@zapb.de>
This commit is contained in:
Antonio Borneo
2024-09-08 21:20:48 +02:00
parent 2ad48b78d4
commit e72733d590
45 changed files with 248 additions and 246 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/target/adi_v5_jtag.c
View File

@@ -736,7 +736,7 @@ static int jtag_send_sequence(struct adiv5_dap *dap, enum swd_special_seq seq)
return retval;
}
static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned int reg,
uint32_t *data)
{
int retval = jtag_limit_queue_size(dap);
@@ -749,7 +749,7 @@ static int jtag_dp_q_read(struct adiv5_dap *dap, unsigned reg,
return retval;
}
static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned int reg,
uint32_t data)
{
int retval = jtag_limit_queue_size(dap);
@@ -763,7 +763,7 @@ static int jtag_dp_q_write(struct adiv5_dap *dap, unsigned reg,
}
/** Select the AP register bank */
static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned int reg)
{
int retval;
struct adiv5_dap *dap = ap->dap;
@@ -818,7 +818,7 @@ static int jtag_ap_q_bankselect(struct adiv5_ap *ap, unsigned reg)
return ERROR_OK;
}
static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned int reg,
uint32_t *data)
{
int retval = jtag_limit_queue_size(ap->dap);
@@ -840,7 +840,7 @@ static int jtag_ap_q_read(struct adiv5_ap *ap, unsigned reg,
return retval;
}
static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned reg,
static int jtag_ap_q_write(struct adiv5_ap *ap, unsigned int reg,
uint32_t data)
{
int retval = jtag_limit_queue_size(ap->dap);

10
src/target/adi_v5_swd.c
View File

@@ -485,7 +485,7 @@ static int swd_queue_ap_abort(struct adiv5_dap *dap, uint8_t *ack)
return check_sync(dap);
}
static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned int reg,
uint32_t *data)
{
int retval = swd_check_reconnect(dap);
@@ -499,7 +499,7 @@ static int swd_queue_dp_read(struct adiv5_dap *dap, unsigned reg,
return swd_queue_dp_read_inner(dap, reg, data);
}
static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned int reg,
uint32_t data)
{
const struct swd_driver *swd = adiv5_dap_swd_driver(dap);
@@ -517,7 +517,7 @@ static int swd_queue_dp_write(struct adiv5_dap *dap, unsigned reg,
}
/** Select the AP register bank */
static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned int reg)
{
int retval;
struct adiv5_dap *dap = ap->dap;
@@ -567,7 +567,7 @@ static int swd_queue_ap_bankselect(struct adiv5_ap *ap, unsigned reg)
return ERROR_OK;
}
static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned int reg,
uint32_t *data)
{
struct adiv5_dap *dap = ap->dap;
@@ -592,7 +592,7 @@ static int swd_queue_ap_read(struct adiv5_ap *ap, unsigned reg,
return check_sync(dap);
}
static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned reg,
static int swd_queue_ap_write(struct adiv5_ap *ap, unsigned int reg,
uint32_t data)
{
struct adiv5_dap *dap = ap->dap;

4
src/target/arc.c
View File

@@ -516,7 +516,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
unsigned long i = 0;
struct reg_cache *reg_cache = target->reg_cache;
while (reg_cache) {
for (unsigned j = 0; j < reg_cache->num_regs; j++, i++)
for (unsigned int j = 0; j < reg_cache->num_regs; j++, i++)
(*reg_list)[i] = &reg_cache->reg_list[j];
reg_cache = reg_cache->next;
}
@@ -527,7 +527,7 @@ static int arc_get_gdb_reg_list(struct target *target, struct reg **reg_list[],
unsigned long gdb_reg_number = 0;
struct reg_cache *reg_cache = target->reg_cache;
while (reg_cache) {
for (unsigned j = 0;
for (unsigned int j = 0;
j < reg_cache->num_regs && gdb_reg_number <= arc->last_general_reg;
j++) {
if (reg_cache->reg_list[j].exist) {

8
src/target/arm.h
View File

@@ -143,8 +143,8 @@ enum {
ARM_VFP_V3_FPSCR,
};
const char *arm_mode_name(unsigned psr_mode);
bool is_arm_mode(unsigned psr_mode);
const char *arm_mode_name(unsigned int psr_mode);
bool is_arm_mode(unsigned int psr_mode);
/** The PSR "T" and "J" bits define the mode of "classic ARM" cores. */
enum arm_state {
@@ -325,7 +325,7 @@ int arm_blank_check_memory(struct target *target,
struct target_memory_check_block *blocks, int num_blocks, uint8_t erased_value);
void arm_set_cpsr(struct arm *arm, uint32_t cpsr);
struct reg *arm_reg_current(struct arm *arm, unsigned regnum);
struct reg *armv8_reg_current(struct arm *arm, unsigned regnum);
struct reg *arm_reg_current(struct arm *arm, unsigned int regnum);
struct reg *armv8_reg_current(struct arm *arm, unsigned int regnum);
#endif /* OPENOCD_TARGET_ARM_H */

2
src/target/arm11.c
View File

@@ -478,7 +478,7 @@ static int arm11_resume(struct target *target, int current,
/* activate all breakpoints */
if (true) {
struct breakpoint *bp;
unsigned brp_num = 0;
unsigned int brp_num = 0;
for (bp = target->breakpoints; bp; bp = bp->next) {
struct arm11_sc7_action brp[2];

2
src/target/arm11.h
View File

@@ -39,7 +39,7 @@ struct arm11_common {
/** Debug module state. */
struct arm_dpm dpm;
struct arm11_sc7_action *bpwp_actions;
unsigned bpwp_n;
unsigned int bpwp_n;
size_t brp; /**< Number of Breakpoint Register Pairs from DIDR */
size_t free_brps; /**< Number of breakpoints allocated */

10
src/target/arm11_dbgtap.c
View File

@@ -567,8 +567,8 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
chain5_fields[2].in_value = NULL;
uint8_t *readies;
unsigned readies_num = count;
unsigned bytes = sizeof(*readies)*readies_num;
unsigned int readies_num = count;
unsigned int bytes = sizeof(*readies) * readies_num;
readies = malloc(bytes);
if (!readies) {
@@ -592,7 +592,7 @@ static int arm11_run_instr_data_to_core_noack_inner(struct jtag_tap *tap,
int retval = jtag_execute_queue();
if (retval == ERROR_OK) {
unsigned error_count = 0;
unsigned int error_count = 0;
for (size_t i = 0; i < readies_num; i++) {
if (readies[i] != 1)
@@ -1042,7 +1042,7 @@ static int arm11_dpm_instr_read_data_r0(struct arm_dpm *dpm,
* and watchpoint operations instead of running them right away. Since we
* pre-allocated our vector, we don't need to worry about space.
*/
static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
uint32_t addr, uint32_t control)
{
struct arm11_common *arm11 = dpm_to_arm11(dpm);
@@ -1079,7 +1079,7 @@ static int arm11_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
return ERROR_OK;
}
static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
static int arm11_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
{
struct arm11_common *arm11 = dpm_to_arm11(dpm);
struct arm11_sc7_action *action;

6
src/target/arm9tdmi.c
View File

@@ -821,9 +821,9 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
else if (strcmp(CMD_ARGV[0], "none") == 0) {
/* do nothing */
} else {
for (unsigned i = 0; i < CMD_ARGC; i++) {
for (unsigned int i = 0; i < CMD_ARGC; i++) {
/* go through list of vectors */
unsigned j;
unsigned int j;
for (j = 0; arm9tdmi_vectors[j].name; j++) {
if (strcmp(CMD_ARGV[i], arm9tdmi_vectors[j].name) == 0) {
vector_catch_value |= arm9tdmi_vectors[j].value;
@@ -850,7 +850,7 @@ COMMAND_HANDLER(handle_arm9tdmi_catch_vectors_command)
}
/* output current settings */
for (unsigned i = 0; arm9tdmi_vectors[i].name; i++) {
for (unsigned int i = 0; arm9tdmi_vectors[i].name; i++) {
command_print(CMD, "%s: %s", arm9tdmi_vectors[i].name,
(vector_catch_value & arm9tdmi_vectors[i].value)
? "catch" : "don't catch");

20
src/target/arm_adi_v5.h
View File

@@ -454,17 +454,17 @@ struct dap_ops {
int (*send_sequence)(struct adiv5_dap *dap, enum swd_special_seq seq);
/** DP register read. */
int (*queue_dp_read)(struct adiv5_dap *dap, unsigned reg,
int (*queue_dp_read)(struct adiv5_dap *dap, unsigned int reg,
uint32_t *data);
/** DP register write. */
int (*queue_dp_write)(struct adiv5_dap *dap, unsigned reg,
int (*queue_dp_write)(struct adiv5_dap *dap, unsigned int reg,
uint32_t data);
/** AP register read. */
int (*queue_ap_read)(struct adiv5_ap *ap, unsigned reg,
int (*queue_ap_read)(struct adiv5_ap *ap, unsigned int reg,
uint32_t *data);
/** AP register write. */
int (*queue_ap_write)(struct adiv5_ap *ap, unsigned reg,
int (*queue_ap_write)(struct adiv5_ap *ap, unsigned int reg,
uint32_t data);
/** AP operation abort. */
@@ -553,7 +553,7 @@ static inline int dap_send_sequence(struct adiv5_dap *dap,
* @return ERROR_OK for success, else a fault code.
*/
static inline int dap_queue_dp_read(struct adiv5_dap *dap,
unsigned reg, uint32_t *data)
unsigned int reg, uint32_t *data)
{
assert(dap->ops);
return dap->ops->queue_dp_read(dap, reg, data);
@@ -571,7 +571,7 @@ static inline int dap_queue_dp_read(struct adiv5_dap *dap,
* @return ERROR_OK for success, else a fault code.
*/
static inline int dap_queue_dp_write(struct adiv5_dap *dap,
unsigned reg, uint32_t data)
unsigned int reg, uint32_t data)
{
assert(dap->ops);
return dap->ops->queue_dp_write(dap, reg, data);
@@ -588,7 +588,7 @@ static inline int dap_queue_dp_write(struct adiv5_dap *dap,
* @return ERROR_OK for success, else a fault code.
*/
static inline int dap_queue_ap_read(struct adiv5_ap *ap,
unsigned reg, uint32_t *data)
unsigned int reg, uint32_t *data)
{
assert(ap->dap->ops);
if (ap->refcount == 0) {
@@ -608,7 +608,7 @@ static inline int dap_queue_ap_read(struct adiv5_ap *ap,
* @return ERROR_OK for success, else a fault code.
*/
static inline int dap_queue_ap_write(struct adiv5_ap *ap,
unsigned reg, uint32_t data)
unsigned int reg, uint32_t data)
{
assert(ap->dap->ops);
if (ap->refcount == 0) {
@@ -659,7 +659,7 @@ static inline int dap_sync(struct adiv5_dap *dap)
return ERROR_OK;
}
static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned int reg,
uint32_t *value)
{
int retval;
@@ -671,7 +671,7 @@ static inline int dap_dp_read_atomic(struct adiv5_dap *dap, unsigned reg,
return dap_run(dap);
}
static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned reg,
static inline int dap_dp_poll_register(struct adiv5_dap *dap, unsigned int reg,
uint32_t mask, uint32_t value, int timeout)
{
assert(timeout > 0);

20
src/target/arm_disassembler.c
View File

@@ -114,7 +114,7 @@ static int evaluate_pld(uint32_t opcode,
if ((opcode & 0x0d30f000) == 0x0510f000) {
uint8_t rn;
uint8_t u;
unsigned offset;
unsigned int offset;
instruction->type = ARM_PLD;
rn = (opcode & 0xf0000) >> 16;
@@ -701,9 +701,9 @@ static int evaluate_load_store(uint32_t opcode,
static int evaluate_extend(uint32_t opcode, uint32_t address, char *cp)
{
unsigned rm = (opcode >> 0) & 0xf;
unsigned rd = (opcode >> 12) & 0xf;
unsigned rn = (opcode >> 16) & 0xf;
unsigned int rm = (opcode >> 0) & 0xf;
unsigned int rd = (opcode >> 12) & 0xf;
unsigned int rn = (opcode >> 16) & 0xf;
char *type, *rot;
switch ((opcode >> 24) & 0x3) {
@@ -892,7 +892,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address,
/* multiplies */
if ((opcode & 0x01f00080) == 0x01000000) {
unsigned rn = (opcode >> 12) & 0xf;
unsigned int rn = (opcode >> 12) & 0xf;
if (rn != 0xf)
sprintf(cp, "SML%cD%s%s\tr%d, r%d, r%d, r%d",
@@ -925,7 +925,7 @@ static int evaluate_media(uint32_t opcode, uint32_t address,
return ERROR_OK;
}
if ((opcode & 0x01f00000) == 0x01500000) {
unsigned rn = (opcode >> 12) & 0xf;
unsigned int rn = (opcode >> 12) & 0xf;
switch (opcode & 0xc0) {
case 3:
@@ -1001,8 +1001,8 @@ static int evaluate_media(uint32_t opcode, uint32_t address,
return ERROR_OK;
}
if (mnemonic) {
unsigned rm = (opcode >> 0) & 0xf;
unsigned rd = (opcode >> 12) & 0xf;
unsigned int rm = (opcode >> 0) & 0xf;
unsigned int rd = (opcode >> 12) & 0xf;
sprintf(cp, "%s%s\tr%d, r%d", mnemonic, COND(opcode), rm, rd);
return ERROR_OK;
@@ -2747,7 +2747,7 @@ static int evaluate_cond_branch_thumb(uint16_t opcode,
static int evaluate_cb_thumb(uint16_t opcode, uint32_t address,
struct arm_instruction *instruction)
{
unsigned offset;
unsigned int offset;
/* added in Thumb2 */
offset = (opcode >> 3) & 0x1f;
@@ -2858,7 +2858,7 @@ static int evaluate_hint_thumb(uint16_t opcode, uint32_t address,
static int evaluate_ifthen_thumb(uint16_t opcode, uint32_t address,
struct arm_instruction *instruction)
{
unsigned cond = (opcode >> 4) & 0x0f;
unsigned int cond = (opcode >> 4) & 0x0f;
char *x = "", *y = "", *z = "";
if (opcode & 0x01)

2
src/target/arm_disassembler.h
View File

@@ -171,7 +171,7 @@ struct arm_instruction {
uint32_t opcode;
/* return value ... Thumb-2 sizes vary */
unsigned instruction_size;
unsigned int instruction_size;
union {
struct arm_b_bl_bx_blx_instr b_bl_bx_blx;

38
src/target/arm_dpm.c
View File

@@ -167,7 +167,7 @@ int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
}
/* Read 64bit VFP registers */
static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
{
int retval = ERROR_FAIL;
uint32_t value_r0, value_r1;
@@ -205,7 +205,7 @@ static int dpm_read_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
}
/* just read the register -- rely on the core mode being right */
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
{
uint32_t value;
int retval;
@@ -272,7 +272,7 @@ int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
}
/* Write 64bit VFP registers */
static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
{
int retval = ERROR_FAIL;
uint32_t value_r0 = buf_get_u32(r->value, 0, 32);
@@ -308,7 +308,7 @@ static int dpm_write_reg_u64(struct arm_dpm *dpm, struct reg *r, unsigned regnum
}
/* just write the register -- rely on the core mode being right */
static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
static int dpm_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
{
int retval;
uint32_t value = buf_get_u32(r->value, 0, 32);
@@ -386,7 +386,7 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm)
return retval;
/* read R0 and R1 first (it's used for scratch), then CPSR */
for (unsigned i = 0; i < 2; i++) {
for (unsigned int i = 0; i < 2; i++) {
r = arm->core_cache->reg_list + i;
if (!r->valid) {
retval = arm_dpm_read_reg(dpm, r, i);
@@ -404,7 +404,7 @@ int arm_dpm_read_current_registers(struct arm_dpm *dpm)
arm_set_cpsr(arm, cpsr);
/* REVISIT we can probably avoid reading R1..R14, saving time... */
for (unsigned i = 2; i < 16; i++) {
for (unsigned int i = 2; i < 16; i++) {
r = arm_reg_current(arm, i);
if (r->valid)
continue;
@@ -501,7 +501,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
* cope with the hand-crafted breakpoint code.
*/
if (arm->target->type->add_breakpoint == dpm_add_breakpoint) {
for (unsigned i = 0; i < dpm->nbp; i++) {
for (unsigned int i = 0; i < dpm->nbp; i++) {
struct dpm_bp *dbp = dpm->dbp + i;
struct breakpoint *bp = dbp->bp;
@@ -513,7 +513,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
}
/* enable/disable watchpoints */
for (unsigned i = 0; i < dpm->nwp; i++) {
for (unsigned int i = 0; i < dpm->nwp; i++) {
struct dpm_wp *dwp = dpm->dwp + i;
struct watchpoint *wp = dwp->wp;
@@ -538,9 +538,9 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
did_write = false;
/* check everything except our scratch registers R0 and R1 */
for (unsigned i = 2; i < cache->num_regs; i++) {
for (unsigned int i = 2; i < cache->num_regs; i++) {
struct arm_reg *r;
unsigned regnum;
unsigned int regnum;
/* also skip PC, CPSR, and non-dirty */
if (i == 15)
@@ -625,7 +625,7 @@ int arm_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
arm->pc->dirty = false;
/* flush R0 and R1 (our scratch registers) */
for (unsigned i = 0; i < 2; i++) {
for (unsigned int i = 0; i < 2; i++) {
retval = dpm_write_reg(dpm, &cache->reg_list[i], i);
if (retval != ERROR_OK)
goto done;
@@ -643,7 +643,7 @@ done:
* or MODE_ANY.
*/
static enum arm_mode dpm_mapmode(struct arm *arm,
unsigned num, enum arm_mode mode)
unsigned int num, enum arm_mode mode)
{
enum arm_mode amode = arm->core_mode;
@@ -793,7 +793,7 @@ static int arm_dpm_full_context(struct target *target)
* Pick some mode with unread registers and read them all.
* Repeat until done.
*/
for (unsigned i = 0; i < cache->num_regs; i++) {
for (unsigned int i = 0; i < cache->num_regs; i++) {
struct arm_reg *r;
if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
@@ -921,7 +921,7 @@ static int dpm_add_breakpoint(struct target *target, struct breakpoint *bp)
if (bp->type == BKPT_SOFT)
LOG_DEBUG("using HW bkpt, not SW...");
for (unsigned i = 0; i < dpm->nbp; i++) {
for (unsigned int i = 0; i < dpm->nbp; i++) {
if (!dpm->dbp[i].bp) {
retval = dpm_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
bp->address, bp->length);
@@ -940,7 +940,7 @@ static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
struct arm_dpm *dpm = arm->dpm;
int retval = ERROR_COMMAND_SYNTAX_ERROR;
for (unsigned i = 0; i < dpm->nbp; i++) {
for (unsigned int i = 0; i < dpm->nbp; i++) {
if (dpm->dbp[i].bp == bp) {
dpm->dbp[i].bp = NULL;
dpm->dbp[i].bpwp.dirty = true;
@@ -954,7 +954,7 @@ static int dpm_remove_breakpoint(struct target *target, struct breakpoint *bp)
return retval;
}
static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
static int dpm_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t,
struct watchpoint *wp)
{
int retval;
@@ -997,7 +997,7 @@ static int dpm_add_watchpoint(struct target *target, struct watchpoint *wp)
int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
if (dpm->bpwp_enable) {
for (unsigned i = 0; i < dpm->nwp; i++) {
for (unsigned int i = 0; i < dpm->nwp; i++) {
if (!dpm->dwp[i].wp) {
retval = dpm_watchpoint_setup(dpm, i, wp);
break;
@@ -1014,7 +1014,7 @@ static int dpm_remove_watchpoint(struct target *target, struct watchpoint *wp)
struct arm_dpm *dpm = arm->dpm;
int retval = ERROR_COMMAND_SYNTAX_ERROR;
for (unsigned i = 0; i < dpm->nwp; i++) {
for (unsigned int i = 0; i < dpm->nwp; i++) {
if (dpm->dwp[i].wp == wp) {
dpm->dwp[i].wp = NULL;
dpm->dwp[i].bpwp.dirty = true;
@@ -1161,7 +1161,7 @@ int arm_dpm_initialize(struct arm_dpm *dpm)
{
/* Disable all breakpoints and watchpoints at startup. */
if (dpm->bpwp_disable) {
unsigned i;
unsigned int i;
for (i = 0; i < dpm->nbp; i++) {
dpm->dbp[i].bpwp.number = i;

14
src/target/arm_dpm.h
View File

@@ -19,7 +19,7 @@
*/
struct dpm_bpwp {
unsigned number;
unsigned int number;
uint32_t address;
uint32_t control;
/* true if hardware state needs flushing */
@@ -109,7 +109,7 @@ struct arm_dpm {
uint32_t opcode, uint64_t *data);
struct reg *(*arm_reg_current)(struct arm *arm,
unsigned regnum);
unsigned int regnum);
/* BREAKPOINT/WATCHPOINT SUPPORT */
@@ -119,7 +119,7 @@ struct arm_dpm {
* must currently be disabled. Indices 0..15 are used for
* breakpoints; indices 16..31 are for watchpoints.
*/
int (*bpwp_enable)(struct arm_dpm *dpm, unsigned index_value,
int (*bpwp_enable)(struct arm_dpm *dpm, unsigned int index_value,
uint32_t addr, uint32_t control);
/**
@@ -127,15 +127,15 @@ struct arm_dpm {
* hardware control registers. Indices are the same ones
* accepted by bpwp_enable().
*/
int (*bpwp_disable)(struct arm_dpm *dpm, unsigned index_value);
int (*bpwp_disable)(struct arm_dpm *dpm, unsigned int index_value);
/* The breakpoint and watchpoint arrays are private to the
* DPM infrastructure. There are nbp indices in the dbp
* array. There are nwp indices in the dwp array.
*/
unsigned nbp;
unsigned nwp;
unsigned int nbp;
unsigned int nwp;
struct dpm_bp *dbp;
struct dpm_wp *dwp;
@@ -158,7 +158,7 @@ struct arm_dpm {
int arm_dpm_setup(struct arm_dpm *dpm);
int arm_dpm_initialize(struct arm_dpm *dpm);
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum);
int arm_dpm_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum);
int arm_dpm_read_current_registers(struct arm_dpm *dpm);
int arm_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);

22
src/target/armv4_5.c
View File

@@ -168,9 +168,9 @@ static const struct {
};
/** Map PSR mode bits to the name of an ARM processor operating mode. */
const char *arm_mode_name(unsigned psr_mode)
const char *arm_mode_name(unsigned int psr_mode)
{
for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
for (unsigned int i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
if (arm_mode_data[i].psr == psr_mode)
return arm_mode_data[i].name;
}
@@ -179,9 +179,9 @@ const char *arm_mode_name(unsigned psr_mode)
}
/** Return true iff the parameter denotes a valid ARM processor mode. */
bool is_arm_mode(unsigned psr_mode)
bool is_arm_mode(unsigned int psr_mode)
{
for (unsigned i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
for (unsigned int i = 0; i < ARRAY_SIZE(arm_mode_data); i++) {
if (arm_mode_data[i].psr == psr_mode)
return true;
}
@@ -272,8 +272,8 @@ static const struct {
* CPSR -or- SPSR depending on whether 'mode' is MODE_ANY.
* (Exception modes have both CPSR and SPSR registers ...)
*/
unsigned cookie;
unsigned gdb_index;
unsigned int cookie;
unsigned int gdb_index;
enum arm_mode mode;
} arm_core_regs[] = {
/* IMPORTANT: we guarantee that the first eight cached registers
@@ -499,7 +499,7 @@ void arm_set_cpsr(struct arm *arm, uint32_t cpsr)
* However, R8..R14, and SPSR (arm->spsr) *must* be mapped.
* CPSR (arm->cpsr) is also not mapped.
*/
struct reg *arm_reg_current(struct arm *arm, unsigned regnum)
struct reg *arm_reg_current(struct arm *arm, unsigned int regnum)
{
struct reg *r;
@@ -840,7 +840,7 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
regs = arm->core_cache->reg_list;
for (unsigned mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
for (unsigned int mode = 0; mode < ARRAY_SIZE(arm_mode_data); mode++) {
const char *name;
char *sep = "\n";
char *shadow = "";
@@ -875,11 +875,11 @@ COMMAND_HANDLER(handle_armv4_5_reg_command)
sep, name, shadow);
/* display N rows of up to 4 registers each */
for (unsigned i = 0; i < arm_mode_data[mode].n_indices; ) {
for (unsigned int i = 0; i < arm_mode_data[mode].n_indices; ) {
char output[80];
int output_len = 0;
for (unsigned j = 0; j < 4; j++, i++) {
for (unsigned int j = 0; j < 4; j++, i++) {
uint32_t value;
struct reg *reg = regs;
@@ -1750,7 +1750,7 @@ cleanup:
static int arm_full_context(struct target *target)
{
struct arm *arm = target_to_arm(target);
unsigned num_regs = arm->core_cache->num_regs;
unsigned int num_regs = arm->core_cache->num_regs;
struct reg *reg = arm->core_cache->reg_list;
int retval = ERROR_OK;

8
src/target/armv7a_cache_l2x.h
View File

@@ -122,16 +122,16 @@ struct outer_cache_fns {
void (*resume)(void);
/* This is an ARM L2C thing */
void (*write_sec)(unsigned long, unsigned);
void (*write_sec)(unsigned long, unsigned int);
void (*configure)(const struct l2x0_regs *);
};
struct l2c_init_data {
const char *type;
unsigned way_size_0;
unsigned num_lock;
unsigned int way_size_0;
unsigned int num_lock;
void (*enable)(uint32_t, uint32_t, unsigned);
void (*enable)(uint32_t, uint32_t, unsigned int);
void (*fixup)(uint32_t, uint32_t, struct outer_cache_fns *);
void (*save)(uint32_t);
void (*configure)(uint32_t);

6
src/target/armv7m.c
View File

@@ -74,9 +74,9 @@ const int armv7m_msp_reg_map[ARMV7M_NUM_CORE_REGS] = {
* doesn't include basepri or faultmask registers.
*/
static const struct {
unsigned id;
unsigned int id;
const char *name;
unsigned bits;
unsigned int bits;
enum reg_type type;
const char *group;
const char *feature;
@@ -530,7 +530,7 @@ int armv7m_start_algorithm(struct target *target,
}
/* Store all non-debug execution registers to armv7m_algorithm_info context */
for (unsigned i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
for (unsigned int i = 0; i < armv7m->arm.core_cache->num_regs; i++) {
struct reg *reg = &armv7m->arm.core_cache->reg_list[i];
if (!reg->exist)
continue;

22
src/target/armv8.c
View File

@@ -36,7 +36,7 @@ static const char * const armv8_state_strings[] = {
static const struct {
const char *name;
unsigned psr;
unsigned int psr;
} armv8_mode_data[] = {
{
.name = "USR",
@@ -105,9 +105,9 @@ static const struct {
};
/** Map PSR mode bits to the name of an ARM processor operating mode. */
const char *armv8_mode_name(unsigned psr_mode)
const char *armv8_mode_name(unsigned int psr_mode)
{
for (unsigned i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
for (unsigned int i = 0; i < ARRAY_SIZE(armv8_mode_data); i++) {
if (armv8_mode_data[i].psr == psr_mode)
return armv8_mode_data[i].name;
}
@@ -683,7 +683,7 @@ static int armv8_read_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum,
struct arm_dpm *dpm = &armv8->dpm;
struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1;
uint32_t value_r0 = 0, value_r1 = 0;
unsigned num = (regnum - ARMV8_V0) << 1;
unsigned int num = (regnum - ARMV8_V0) << 1;
switch (regnum) {
case ARMV8_V0 ... ARMV8_V15:
@@ -817,7 +817,7 @@ static int armv8_write_reg_simdfp_aarch32(struct armv8_common *armv8, int regnum
struct arm_dpm *dpm = &armv8->dpm;
struct reg *reg_r1 = dpm->arm->core_cache->reg_list + ARMV8_R1;
uint32_t value_r0 = 0, value_r1 = 0;
unsigned num = (regnum - ARMV8_V0) << 1;
unsigned int num = (regnum - ARMV8_V0) << 1;
switch (regnum) {
case ARMV8_V0 ... ARMV8_V15:
@@ -1506,9 +1506,9 @@ static struct reg_data_type aarch64_flags_cpsr[] = {
};
static const struct {
unsigned id;
unsigned int id;
const char *name;
unsigned bits;
unsigned int bits;
enum arm_mode mode;
enum reg_type type;
const char *group;
@@ -1611,10 +1611,10 @@ static const struct {
};
static const struct {
unsigned id;
unsigned mapping;
unsigned int id;
unsigned int mapping;
const char *name;
unsigned bits;
unsigned int bits;
enum arm_mode mode;
enum reg_type type;
const char *group;
@@ -1881,7 +1881,7 @@ struct reg_cache *armv8_build_reg_cache(struct target *target)
return cache;
}
struct reg *armv8_reg_current(struct arm *arm, unsigned regnum)
struct reg *armv8_reg_current(struct arm *arm, unsigned int regnum)
{
struct reg *r;

2
src/target/armv8.h
View File

@@ -329,7 +329,7 @@ static inline unsigned int armv8_curel_from_core_mode(enum arm_mode core_mode)
}
}
const char *armv8_mode_name(unsigned psr_mode);
const char *armv8_mode_name(unsigned int psr_mode);
void armv8_select_reg_access(struct armv8_common *armv8, bool is_aarch64);
int armv8_set_dbgreg_bits(struct armv8_common *armv8, unsigned int reg, unsigned long mask, unsigned long value);

28
src/target/armv8_dpm.c
View File

@@ -417,7 +417,7 @@ static int dpmv8_instr_read_data_r0_64(struct arm_dpm *dpm,
}
#if 0
static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
target_addr_t addr, uint32_t control)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
@@ -450,7 +450,7 @@ static int dpmv8_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
}
#endif
static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
static int dpmv8_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
uint32_t cr;
@@ -641,7 +641,7 @@ int armv8_dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
/*
* Common register read, relies on armv8_select_reg_access() having been called.
*/
static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
int retval = ERROR_FAIL;
@@ -684,7 +684,7 @@ static int dpmv8_read_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
/*
* Common register write, relies on armv8_select_reg_access() having been called.
*/
static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned regnum)
static int dpmv8_write_reg(struct arm_dpm *dpm, struct reg *r, unsigned int regnum)
{
struct armv8_common *armv8 = dpm->arm->arch_info;
int retval = ERROR_FAIL;
@@ -887,7 +887,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
* cope with the hand-crafted breakpoint code.
*/
if (arm->target->type->add_breakpoint == dpmv8_add_breakpoint) {
for (unsigned i = 0; i < dpm->nbp; i++) {
for (unsigned int i = 0; i < dpm->nbp; i++) {
struct dpm_bp *dbp = dpm->dbp + i;
struct breakpoint *bp = dbp->bp;
@@ -899,7 +899,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
}
/* enable/disable watchpoints */
for (unsigned i = 0; i < dpm->nwp; i++) {
for (unsigned int i = 0; i < dpm->nwp; i++) {
struct dpm_wp *dwp = dpm->dwp + i;
struct watchpoint *wp = dwp->wp;
@@ -919,7 +919,7 @@ int armv8_dpm_write_dirty_registers(struct arm_dpm *dpm, bool bpwp)
goto done;
/* check everything except our scratch register R0 */
for (unsigned i = 1; i < cache->num_regs; i++) {
for (unsigned int i = 1; i < cache->num_regs; i++) {
struct arm_reg *r;
/* skip non-existent */
@@ -1047,7 +1047,7 @@ static int armv8_dpm_full_context(struct target *target)
* Pick some mode with unread registers and read them all.
* Repeat until done.
*/
for (unsigned i = 0; i < cache->num_regs; i++) {
for (unsigned int i = 0; i < cache->num_regs; i++) {
struct arm_reg *r;
if (!cache->reg_list[i].exist || cache->reg_list[i].valid)
@@ -1175,7 +1175,7 @@ static int dpmv8_add_breakpoint(struct target *target, struct breakpoint *bp)
if (bp->type == BKPT_SOFT)
LOG_DEBUG("using HW bkpt, not SW...");
for (unsigned i = 0; i < dpm->nbp; i++) {
for (unsigned int i = 0; i < dpm->nbp; i++) {
if (!dpm->dbp[i].bp) {
retval = dpmv8_bpwp_setup(dpm, &dpm->dbp[i].bpwp,
bp->address, bp->length);
@@ -1194,7 +1194,7 @@ static int dpmv8_remove_breakpoint(struct target *target, struct breakpoint *bp)
struct arm_dpm *dpm = arm->dpm;
int retval = ERROR_COMMAND_SYNTAX_ERROR;
for (unsigned i = 0; i < dpm->nbp; i++) {
for (unsigned int i = 0; i < dpm->nbp; i++) {
if (dpm->dbp[i].bp == bp) {
dpm->dbp[i].bp = NULL;
dpm->dbp[i].bpwp.dirty = true;
@@ -1208,7 +1208,7 @@ static int dpmv8_remove_breakpoint(struct target *target, struct breakpoint *bp)
return retval;
}
static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned index_t,
static int dpmv8_watchpoint_setup(struct arm_dpm *dpm, unsigned int index_t,
struct watchpoint *wp)
{
int retval;
@@ -1251,7 +1251,7 @@ static int dpmv8_add_watchpoint(struct target *target, struct watchpoint *wp)
int retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE;
if (dpm->bpwp_enable) {
for (unsigned i = 0; i < dpm->nwp; i++) {
for (unsigned int i = 0; i < dpm->nwp; i++) {
if (!dpm->dwp[i].wp) {
retval = dpmv8_watchpoint_setup(dpm, i, wp);
break;
@@ -1268,7 +1268,7 @@ static int dpmv8_remove_watchpoint(struct target *target, struct watchpoint *wp)
struct arm_dpm *dpm = arm->dpm;
int retval = ERROR_COMMAND_SYNTAX_ERROR;
for (unsigned i = 0; i < dpm->nwp; i++) {
for (unsigned int i = 0; i < dpm->nwp; i++) {
if (dpm->dwp[i].wp == wp) {
dpm->dwp[i].wp = NULL;
dpm->dwp[i].bpwp.dirty = true;
@@ -1484,7 +1484,7 @@ int armv8_dpm_initialize(struct arm_dpm *dpm)
{
/* Disable all breakpoints and watchpoints at startup. */
if (dpm->bpwp_disable) {
unsigned i;
unsigned int i;
for (i = 0; i < dpm->nbp; i++) {
dpm->dbp[i].bpwp.number = i;

4
src/target/cortex_a.c
View File

@@ -571,7 +571,7 @@ static int cortex_a_instr_read_data_r0_r1(struct arm_dpm *dpm,
return retval;
}
static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned int index_t,
uint32_t addr, uint32_t control)
{
struct cortex_a_common *a = dpm_to_a(dpm);
@@ -606,7 +606,7 @@ static int cortex_a_bpwp_enable(struct arm_dpm *dpm, unsigned index_t,
return retval;
}
static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned index_t)
static int cortex_a_bpwp_disable(struct arm_dpm *dpm, unsigned int index_t)
{
struct cortex_a_common *a = dpm_to_a(dpm);
uint32_t cr;

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