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STM32L: Added flash driver and target
Added the flash driver for the STM32L family, which highly differ from the STM32F family. Added the TCL target file for JTAG access.
This commit is contained in:
Clément Burin des Roziers
committed by
Øyvind Harboe
Øyvind Harboe
parent
a17adf0601
commit
da8ce5f2e1
63
contrib/loaders/flash/stm32lx.S
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63
contrib/loaders/flash/stm32lx.S
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@@ -0,0 +1,63 @@
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/***************************************************************************
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* Copyright (C) 2010 by Spencer Oliver *
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* spen@spen-soft.co.uk *
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* *
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* Copyright (C) 2011 Øyvind Harboe *
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* oyvind.harboe@zylin.com *
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* *
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* Copyright (C) 2011 Clement Burin des Roziers *
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* clement.burin-des-roziers@hikob.com *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program; if not, write to the *
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* Free Software Foundation, Inc., *
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* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
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***************************************************************************/
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// Build : arm-eabi-gcc -c stm32lx.S
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.text
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.syntax unified
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.cpu cortex-m3
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.thumb
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.thumb_func
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.global write
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/*
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r0 - destination address
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r1 - source address
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r2 - count
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*/
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// Set 0 to r3
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movs r3, #0
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// Go to compare
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b.n test_done
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write_word:
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// Load one word from address in r0, increment by 4
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ldr.w ip, [r1], #4
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// Store the word to address in r1, increment by 4
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str.w ip, [r0], #4
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// Increment r3
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adds r3, #1
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test_done:
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// Compare r3 and r2
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cmp r3, r2
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// Loop if not zero
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bcc.n write_word
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// Set breakpoint to exit
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bkpt #0x00
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@@ -26,6 +26,7 @@ NOR_DRIVERS = \
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stellaris.c \
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stm32f1x.c \
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stm32f2x.c \
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stm32lx.c \
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str7x.c \
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str9x.c \
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str9xpec.c \
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@@ -34,6 +34,7 @@ extern struct flash_driver stellaris_flash;
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extern struct flash_driver str9xpec_flash;
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extern struct flash_driver stm32f1x_flash;
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extern struct flash_driver stm32f2x_flash;
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extern struct flash_driver stm32lx_flash;
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extern struct flash_driver tms470_flash;
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extern struct flash_driver ecosflash_flash;
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extern struct flash_driver ocl_flash;
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@@ -65,6 +66,7 @@ static struct flash_driver *flash_drivers[] = {
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&str9xpec_flash,
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&stm32f1x_flash,
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&stm32f2x_flash,
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&stm32lx_flash,
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&tms470_flash,
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&ecosflash_flash,
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&ocl_flash,
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970
src/flash/nor/stm32lx.c
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970
src/flash/nor/stm32lx.c
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File diff suppressed because it is too large
Load Diff
81
tcl/target/stm32l.cfg
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81
tcl/target/stm32l.cfg
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@@ -0,0 +1,81 @@
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# script for stm32l
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME stm32l
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}
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if { [info exists ENDIAN] } {
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set _ENDIAN $ENDIAN
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} else {
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set _ENDIAN little
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}
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# Work-area is a space in RAM used for flash programming
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# By default use 14kB
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x3800
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}
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# JTAG speed should be <= F_CPU/6.
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# F_CPU after reset is 2MHz, so use F_JTAG max = 333kHz
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adapter_khz 100
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adapter_nsrst_delay 100
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jtag_ntrst_delay 100
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#jtag scan chain
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if { [info exists CPUTAPID ] } {
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set _CPUTAPID $CPUTAPID
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} else {
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# See STM Document RM0038
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# Section 24.6.3
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set _CPUTAPID 0x4ba00477
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}
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_CPUTAPID
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if { [info exists BSTAPID ] } {
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# FIXME this never gets used to override defaults...
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set _BSTAPID $BSTAPID
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} else {
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# See STM Document RM0038
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# Section 24.6.2
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set _BSTAPID 0x06416041
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}
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jtag newtap $_CHIPNAME bs -irlen 5 -expected-id $_BSTAPID
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set _TARGETNAME $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m3 -endian $_ENDIAN -chain-position $_TARGETNAME
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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# flash size will be probed
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME stm32lx 0x08000000 0 0 0 $_TARGETNAME
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# if srst is not fitted use SYSRESETREQ to
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# perform a soft reset
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cortex_m3 reset_config sysresetreq
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proc stm32l_enable_HSI {} {
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# Enable HSI as clock source
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echo "STM32L: Enabling HSI"
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# Set HSION in RCC_CR
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mww 0x40023800 0x00000101
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# Set HSI as SYSCLK
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mww 0x40023808 0x00000001
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# Increase JTAG speed
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adapter_khz 2000
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}
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$_TARGETNAME configure -event reset-init {
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stm32l_enable_HSI
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}
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