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nds32: drop it, together with aice adapter driver

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The target nds32 and its companion adapter aice have not received
any real improvement since 2013.
It has been hard to keep them aligned during the evolution of
OpenOCD code, with no way for maintainers to really check if they
are still working.
No real documentation is present for them in OpenOCD.
The nds32 code triggers ~50 errors/warnings with scan-build.

The arch nds32 has been dropped from Linux kernel v5.18-rc1.

For all the reasons above, this code has been deprecated with
commit 2e5df83de7 ("nds32: deprecate it, together with aice
adapter driver") and tagged to be dropped before v0.13.0.

Let it r.i.p. in OpenOCD git history.

While there, drop from checkpatch list the camelcase symbols that
where only used in this code.

Change-Id: Ide52a217f2228e9da2f1cc5036c48f3536f26952
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/7382
Tested-by: jenkins
This commit is contained in:
Antonio Borneo
2022-09-19 23:14:41 +02:00
parent 8bb926eb01
commit da34e36cdb
51 changed files with 4 additions and 18510 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
README
View File

@@ -101,7 +101,7 @@ Supported hardware
JTAG adapters
-------------
AICE, AM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835,
AM335x, ARM-JTAG-EW, ARM-USB-OCD, ARM-USB-TINY, AT91RM9200, axm0432, BCM2835,
Bus Blaster, Buspirate, Cadence DPI, Cadence vdebug, Chameleon, CMSIS-DAP,
Cortino, Cypress KitProg, DENX, Digilent JTAG-SMT2, DLC 5, DLP-USB1232H,
embedded projects, Espressif USB JTAG Programmer,
@@ -122,7 +122,7 @@ Debug targets
ARM: AArch64, ARM11, ARM7, ARM9, Cortex-A/R (v7-A/R), Cortex-M (ARMv{6/7/8}-M),
FA526, Feroceon/Dragonite, XScale.
ARCv2, AVR32, DSP563xx, DSP5680xx, EnSilica eSi-RISC, EJTAG (MIPS32, MIPS64),
ESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, NDS32, RISC-V, ST STM8,
ESP32, ESP32-S2, ESP32-S3, Intel Quark, LS102x-SAP, RISC-V, ST STM8,
Xtensa.
Flash drivers

7
configure.ac
View File

@@ -130,9 +130,6 @@ m4_define([USB1_ADAPTERS],
[[usbprog], [USBProg JTAG Programmer], [USBPROG]],
[[esp_usb_jtag], [Espressif JTAG Programmer], [ESP_USB_JTAG]]])
m4_define([DEPRECATED_USB1_ADAPTERS],
[[[aice], [Andes JTAG Programmer (deprecated)], [AICE]]])
m4_define([HIDAPI_ADAPTERS],
[[[cmsis_dap], [CMSIS-DAP Compliant Debugger], [CMSIS_DAP_HID]],
[[nulink], [Nu-Link Programmer], [HLADAPTER_NULINK]]])
@@ -264,8 +261,6 @@ AC_ARG_ADAPTERS([
LIBJAYLINK_ADAPTERS
],[auto])
AC_ARG_ADAPTERS([DEPRECATED_USB1_ADAPTERS],[no])
AC_ARG_ENABLE([parport],
AS_HELP_STRING([--enable-parport], [Enable building the pc parallel port driver]),
[build_parport=$enableval], [build_parport=no])
@@ -684,7 +679,6 @@ m4_define([PROCESS_ADAPTERS], [
])
PROCESS_ADAPTERS([USB1_ADAPTERS], ["x$use_libusb1" = "xyes"], [libusb-1.x])
PROCESS_ADAPTERS([DEPRECATED_USB1_ADAPTERS], ["x$use_libusb1" = "xyes"], [libusb-1.x])
PROCESS_ADAPTERS([HIDAPI_ADAPTERS], ["x$use_hidapi" = "xyes"], [hidapi])
PROCESS_ADAPTERS([HIDAPI_USB1_ADAPTERS], ["x$use_hidapi" = "xyes" -a "x$use_libusb1" = "xyes"], [hidapi and libusb-1.x])
PROCESS_ADAPTERS([LIBFTDI_ADAPTERS], ["x$use_libftdi" = "xyes"], [libftdi])
@@ -834,7 +828,6 @@ echo
echo OpenOCD configuration summary
echo --------------------------------------------------
m4_foreach([adapter], [USB1_ADAPTERS,
DEPRECATED_USB1_ADAPTERS,
HIDAPI_ADAPTERS, HIDAPI_USB1_ADAPTERS, LIBFTDI_ADAPTERS,
LIBFTDI_USB1_ADAPTERS,
LIBGPIOD_ADAPTERS,

1
contrib/buildroot/openocd_be_defconfig
View File

@@ -12,7 +12,6 @@ BR2_PACKAGE_OPENOCD_UBLASTER2=y
BR2_PACKAGE_OPENOCD_JLINK=y
BR2_PACKAGE_OPENOCD_OSDBM=y
BR2_PACKAGE_OPENOCD_OPENDOUS=y
BR2_PACKAGE_OPENOCD_AICE=y
BR2_PACKAGE_OPENOCD_VSLLINK=y
BR2_PACKAGE_OPENOCD_USBPROG=y
BR2_PACKAGE_OPENOCD_RLINK=y

5
doc/openocd.texi
View File

@@ -2480,7 +2480,7 @@ This command is only available if your libusb1 is at least version 1.0.16.
Specifies the @var{serial_string} of the adapter to use.
If this command is not specified, serial strings are not checked.
Only the following adapter drivers use the serial string from this command:
aice (aice_usb), arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
arm-jtag-ew, cmsis_dap, ft232r, ftdi, hla (stlink, ti-icdi), jlink, kitprog, opendus,
openjtag, osbdm, presto, rlink, st-link, usb_blaster (ublast2), usbprog, vsllink, xds110.
@end deffn
@@ -4825,9 +4825,6 @@ specified, @xref{gdbportoverride,,option -gdb-port}.), and a fake ARM core will
be emulated to comply to GDB remote protocol.
@item @code{mips_m4k} -- a MIPS core.
@item @code{mips_mips64} -- a MIPS64 core.
@item @code{nds32_v2} -- this is an Andes NDS32 v2 core (deprecated; would be removed in v0.13.0).
@item @code{nds32_v3} -- this is an Andes NDS32 v3 core (deprecated; would be removed in v0.13.0).
@item @code{nds32_v3m} -- this is an Andes NDS32 v3m core (deprecated; would be removed in v0.13.0).
@item @code{or1k} -- this is an OpenRISC 1000 core.
The current implementation supports three JTAG TAP cores:
@itemize @minus

5
src/jtag/Makefile.am
View File

@@ -9,11 +9,6 @@ include %D%/hla/Makefile.am
%C%_libjtag_la_LIBADD += $(top_builddir)/%D%/hla/libocdhla.la
endif
if AICE
include %D%/aice/Makefile.am
%C%_libjtag_la_LIBADD += $(top_builddir)/%D%/aice/libocdaice.la
endif
include %D%/drivers/Makefile.am
%C%_libjtag_la_LIBADD += $(top_builddir)/%D%/drivers/libocdjtagdrivers.la

16
src/jtag/aice/Makefile.am
View File

@@ -1,16 +0,0 @@
# SPDX-License-Identifier: GPL-2.0-or-later
noinst_LTLIBRARIES += %D%/libocdaice.la
%C%_libocdaice_la_CPPFLAGS = -I$(top_srcdir)/src/jtag/drivers $(AM_CPPFLAGS) $(LIBUSB1_CFLAGS)
%C%_libocdaice_la_SOURCES = \
%D%/aice_transport.c \
%D%/aice_interface.c \
%D%/aice_port.c \
%D%/aice_usb.c \
%D%/aice_pipe.c \
%D%/aice_transport.h \
%D%/aice_interface.h \
%D%/aice_port.h \
%D%/aice_usb.h \
%D%/aice_pipe.h

507
src/jtag/aice/aice_interface.c
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File diff suppressed because it is too large Load Diff

14
src/jtag/aice/aice_interface.h
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@@ -1,14 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* Copyright (C) 2013 by Andes Technology *
* Hsiangkai Wang <hkwang@andestech.com> *
***************************************************************************/
#ifndef OPENOCD_JTAG_AICE_AICE_INTERFACE_H
#define OPENOCD_JTAG_AICE_AICE_INTERFACE_H
int aice_init_targets(void);
int aice_scan_jtag_chain(void);
#endif /* OPENOCD_JTAG_AICE_AICE_INTERFACE_H */

884
src/jtag/aice/aice_pipe.c
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File diff suppressed because it is too large Load Diff

20
src/jtag/aice/aice_pipe.h
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@@ -1,20 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* Copyright (C) 2013 by Andes Technology *
* Hsiangkai Wang <hkwang@andestech.com> *
***************************************************************************/
#ifndef OPENOCD_JTAG_AICE_AICE_PIPE_H
#define OPENOCD_JTAG_AICE_AICE_PIPE_H
#include <helper/types.h>
#define set_u32(buffer, value) h_u32_to_le((uint8_t *)buffer, value)
#define set_u16(buffer, value) h_u16_to_le((uint8_t *)buffer, value)
#define get_u32(buffer) le_to_h_u32((const uint8_t *)buffer)
#define get_u16(buffer) le_to_h_u16((const uint8_t *)buffer)
extern struct aice_port_api_s aice_pipe;
#endif /* OPENOCD_JTAG_AICE_AICE_PIPE_H */

34
src/jtag/aice/aice_port.c
View File

@@ -1,34 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2013 by Andes Technology *
* Hsiangkai Wang <hkwang@andestech.com> *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <helper/log.h>
#include "aice_usb.h"
#include "aice_pipe.h"
#include "aice_port.h"
static const struct aice_port aice_ports[] = {
{
.name = "aice_usb",
.type = AICE_PORT_AICE_USB,
.api = &aice_usb_api,
},
{
.name = "aice_pipe",
.type = AICE_PORT_AICE_PIPE,
.api = &aice_pipe,
},
{.name = NULL, /* END OF TABLE */ },
};
/** */
const struct aice_port *aice_port_get_list(void)
{
return aice_ports;
}

224
src/jtag/aice/aice_port.h
View File

@@ -1,224 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* Copyright (C) 2013 by Andes Technology *
* Hsiangkai Wang <hkwang@andestech.com> *
***************************************************************************/
#ifndef OPENOCD_JTAG_AICE_AICE_PORT_H
#define OPENOCD_JTAG_AICE_AICE_PORT_H
#include <target/nds32_edm.h>
#define AICE_MAX_NUM_CORE (0x10)
#define ERROR_AICE_DISCONNECT (-200)
#define ERROR_AICE_TIMEOUT (-201)
enum aice_target_state_s {
AICE_DISCONNECT = 0,
AICE_TARGET_DETACH,
AICE_TARGET_UNKNOWN,
AICE_TARGET_RUNNING,
AICE_TARGET_HALTED,
AICE_TARGET_RESET,
AICE_TARGET_DEBUG_RUNNING,
};
enum aice_srst_type_s {
AICE_SRST = 0x1,
AICE_RESET_HOLD = 0x8,
};
enum aice_target_endian {
AICE_LITTLE_ENDIAN = 0,
AICE_BIG_ENDIAN,
};
enum aice_api_s {
AICE_OPEN = 0x0,
AICE_CLOSE,
AICE_RESET,
AICE_IDCODE,
AICE_SET_JTAG_CLOCK,
AICE_ASSERT_SRST,
AICE_RUN,
AICE_HALT,
AICE_STEP,
AICE_READ_REG,
AICE_WRITE_REG,
AICE_READ_REG_64,
AICE_WRITE_REG_64,
AICE_READ_MEM_UNIT,
AICE_WRITE_MEM_UNIT,
AICE_READ_MEM_BULK,
AICE_WRITE_MEM_BULK,
AICE_READ_DEBUG_REG,
AICE_WRITE_DEBUG_REG,
AICE_STATE,
AICE_MEMORY_ACCESS,
AICE_MEMORY_MODE,
AICE_READ_TLB,
AICE_CACHE_CTL,
AICE_SET_RETRY_TIMES,
AICE_PROGRAM_EDM,
AICE_SET_COMMAND_MODE,
AICE_EXECUTE,
AICE_SET_CUSTOM_SRST_SCRIPT,
AICE_SET_CUSTOM_TRST_SCRIPT,
AICE_SET_CUSTOM_RESTART_SCRIPT,
AICE_SET_COUNT_TO_CHECK_DBGER,
AICE_SET_DATA_ENDIAN,
};
enum aice_error_s {
AICE_OK,
AICE_ACK,
AICE_ERROR,
};
enum aice_cache_ctl_type {
AICE_CACHE_CTL_L1D_INVALALL = 0,
AICE_CACHE_CTL_L1D_VA_INVAL,
AICE_CACHE_CTL_L1D_WBALL,
AICE_CACHE_CTL_L1D_VA_WB,
AICE_CACHE_CTL_L1I_INVALALL,
AICE_CACHE_CTL_L1I_VA_INVAL,
};
enum aice_command_mode {
AICE_COMMAND_MODE_NORMAL,
AICE_COMMAND_MODE_PACK,
AICE_COMMAND_MODE_BATCH,
};
struct aice_port_param_s {
/** */
const char *device_desc;
/** */
uint16_t vid;
/** */
uint16_t pid;
/** */
char *adapter_name;
};
struct aice_port_s {
/** */
uint32_t coreid;
/** */
const struct aice_port *port;
};
/** */
extern struct aice_port_api_s aice_usb_layout_api;
/** */
struct aice_port_api_s {
/** */
int (*open)(struct aice_port_param_s *param);
/** */
int (*close)(void);
/** */
int (*reset)(void);
/** */
int (*idcode)(uint32_t *idcode, uint8_t *num_of_idcode);
/** */
int (*set_jtag_clock)(uint32_t a_clock);
/** */
int (*assert_srst)(uint32_t coreid, enum aice_srst_type_s srst);
/** */
int (*run)(uint32_t coreid);
/** */
int (*halt)(uint32_t coreid);
/** */
int (*step)(uint32_t coreid);
/** */
int (*read_reg)(uint32_t coreid, uint32_t num, uint32_t *val);
/** */
int (*write_reg)(uint32_t coreid, uint32_t num, uint32_t val);
/** */
int (*read_reg_64)(uint32_t coreid, uint32_t num, uint64_t *val);
/** */
int (*write_reg_64)(uint32_t coreid, uint32_t num, uint64_t val);
/** */
int (*read_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
uint32_t count, uint8_t *buffer);
/** */
int (*write_mem_unit)(uint32_t coreid, uint32_t addr, uint32_t size,
uint32_t count, const uint8_t *buffer);
/** */
int (*read_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
uint8_t *buffer);
/** */
int (*write_mem_bulk)(uint32_t coreid, uint32_t addr, uint32_t length,
const uint8_t *buffer);
/** */
int (*read_debug_reg)(uint32_t coreid, uint32_t addr, uint32_t *val);
/** */
int (*write_debug_reg)(uint32_t coreid, uint32_t addr, const uint32_t val);
/** */
int (*state)(uint32_t coreid, enum aice_target_state_s *state);
/** */
int (*memory_access)(uint32_t coreid, enum nds_memory_access a_access);
/** */
int (*memory_mode)(uint32_t coreid, enum nds_memory_select mem_select);
/** */
int (*read_tlb)(uint32_t coreid, target_addr_t virtual_address, target_addr_t *physical_address);
/** */
int (*cache_ctl)(uint32_t coreid, uint32_t subtype, uint32_t address);
/** */
int (*set_retry_times)(uint32_t a_retry_times);
/** */
int (*program_edm)(uint32_t coreid, char *command_sequence);
/** */
int (*set_command_mode)(enum aice_command_mode command_mode);
/** */
int (*execute)(uint32_t coreid, uint32_t *instructions, uint32_t instruction_num);
/** */
int (*set_custom_srst_script)(const char *script);
/** */
int (*set_custom_trst_script)(const char *script);
/** */
int (*set_custom_restart_script)(const char *script);
/** */
int (*set_count_to_check_dbger)(uint32_t count_to_check);
/** */
int (*set_data_endian)(uint32_t coreid, enum aice_target_endian target_data_endian);
/** */
int (*profiling)(uint32_t coreid, uint32_t interval, uint32_t iteration,
uint32_t reg_no, uint32_t *samples, uint32_t *num_samples);
};
#define AICE_PORT_UNKNOWN 0
#define AICE_PORT_AICE_USB 1
#define AICE_PORT_AICE_PIPE 2
/** */
struct aice_port {
/** */
const char *name;
/** */
int type;
/** */
struct aice_port_api_s *const api;
};
/** */
const struct aice_port *aice_port_get_list(void);
#endif /* OPENOCD_JTAG_AICE_AICE_PORT_H */

432
src/jtag/aice/aice_transport.c
View File

@@ -1,432 +0,0 @@
// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Copyright (C) 2013 by Andes Technology *
* Hsiangkai Wang <hkwang@andestech.com> *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
/* project specific includes */
#include <jtag/interface.h>
#include <jtag/tcl.h>
#include <transport/transport.h>
#include <target/target.h>
#include <jtag/aice/aice_interface.h>
#include <jtag/aice/aice_transport.h>
#include <string.h>
/* */
static int jim_newtap_expected_id(struct jim_nvp *n, struct jim_getopt_info *goi,
struct jtag_tap *tap)
{
jim_wide w;
int e = jim_getopt_wide(goi, &w);
if (e != JIM_OK) {
Jim_SetResultFormatted(goi->interp, "option: %s bad parameter",
n->name);
return e;
}
unsigned expected_len = sizeof(uint32_t) * tap->expected_ids_cnt;
uint32_t *new_expected_ids = malloc(expected_len + sizeof(uint32_t));
if (!new_expected_ids) {
Jim_SetResultFormatted(goi->interp, "no memory");
return JIM_ERR;
}
assert(tap->expected_ids);
memcpy(new_expected_ids, tap->expected_ids, expected_len);
new_expected_ids[tap->expected_ids_cnt] = w;
free(tap->expected_ids);
tap->expected_ids = new_expected_ids;
tap->expected_ids_cnt++;
return JIM_OK;
}
#define NTAP_OPT_EXPECTED_ID 0
/* */
static int jim_aice_newtap_cmd(struct jim_getopt_info *goi)
{
struct jtag_tap *tap;
int x;
int e;
struct jim_nvp *n;
char *cp;
const struct jim_nvp opts[] = {
{.name = "-expected-id", .value = NTAP_OPT_EXPECTED_ID},
{.name = NULL, .value = -1},
};
tap = calloc(1, sizeof(struct jtag_tap));
if (!tap) {
Jim_SetResultFormatted(goi->interp, "no memory");
return JIM_ERR;
}
/*
* we expect CHIP + TAP + OPTIONS
* */
if (goi->argc < 3) {
Jim_SetResultFormatted(goi->interp,
"Missing CHIP TAP OPTIONS ....");
free(tap);
return JIM_ERR;
}
const char *tmp;
jim_getopt_string(goi, &tmp, NULL);
tap->chip = strdup(tmp);
jim_getopt_string(goi, &tmp, NULL);
tap->tapname = strdup(tmp);
/* name + dot + name + null */
x = strlen(tap->chip) + 1 + strlen(tap->tapname) + 1;
cp = malloc(x);
sprintf(cp, "%s.%s", tap->chip, tap->tapname);
tap->dotted_name = cp;
LOG_DEBUG("Creating New Tap, Chip: %s, Tap: %s, Dotted: %s, %d params",
tap->chip, tap->tapname, tap->dotted_name, goi->argc);
while (goi->argc) {
e = jim_getopt_nvp(goi, opts, &n);
if (e != JIM_OK) {
jim_getopt_nvp_unknown(goi, opts, 0);
free(cp);
free(tap);
return e;
}
LOG_DEBUG("Processing option: %s", n->name);
switch (n->value) {
case NTAP_OPT_EXPECTED_ID:
e = jim_newtap_expected_id(n, goi, tap);
if (e != JIM_OK) {
free(cp);
free(tap);
return e;
}
break;
} /* switch (n->value) */
} /* while (goi->argc) */
/* default is enabled-after-reset */
tap->enabled = !tap->disabled_after_reset;
jtag_tap_init(tap);
return JIM_OK;
}
/* */
static int jim_aice_newtap(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
{
struct jim_getopt_info goi;
jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
return jim_aice_newtap_cmd(&goi);
}
/* */
COMMAND_HANDLER(handle_aice_init_command)
{
if (CMD_ARGC != 0)
return ERROR_COMMAND_SYNTAX_ERROR;
static bool jtag_initialized;
if (jtag_initialized) {
LOG_INFO("'jtag init' has already been called");
return ERROR_OK;
}
jtag_initialized = true;
LOG_DEBUG("Initializing jtag devices...");
return jtag_init(CMD_CTX);
}
COMMAND_HANDLER(handle_scan_chain_command)
{
struct jtag_tap *tap;
char expected_id[12];
aice_scan_jtag_chain();
tap = jtag_all_taps();
command_print(CMD,
" TapName Enabled IdCode Expected IrLen IrCap IrMask");
command_print(CMD,
"-- ------------------- -------- ---------- ---------- ----- ----- ------");
while (tap) {
uint32_t expected, expected_mask, ii;
snprintf(expected_id, sizeof(expected_id), "0x%08x",
(unsigned)((tap->expected_ids_cnt > 0)
? tap->expected_ids[0]
: 0));
if (tap->ignore_version)
expected_id[2] = '*';
expected = buf_get_u32(tap->expected, 0, tap->ir_length);
expected_mask = buf_get_u32(tap->expected_mask, 0, tap->ir_length);
command_print(CMD,
"%2d %-18s %c 0x%08x %s %5d 0x%02x 0x%02x",
tap->abs_chain_position,
tap->dotted_name,
tap->enabled ? 'Y' : 'n',
(unsigned int)(tap->idcode),
expected_id,
(unsigned int)(tap->ir_length),
(unsigned int)(expected),
(unsigned int)(expected_mask));
for (ii = 1; ii < tap->expected_ids_cnt; ii++) {
snprintf(expected_id, sizeof(expected_id), "0x%08x",
(unsigned) tap->expected_ids[ii]);
if (tap->ignore_version)
expected_id[2] = '*';
command_print(CMD,
" %s",
expected_id);
}
tap = tap->next_tap;
}
return ERROR_OK;
}
static int jim_aice_arp_init(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
{
LOG_DEBUG("No implement: jim_aice_arp_init");
return JIM_OK;
}
/* */
static int aice_init_reset(struct command_context *cmd_ctx)
{
LOG_DEBUG("Initializing with hard TRST+SRST reset");
int retval;
enum reset_types jtag_reset_config = jtag_get_reset_config();
jtag_add_reset(1, 0); /* TAP_RESET */
if (jtag_reset_config & RESET_HAS_SRST) {
jtag_add_reset(1, 1);
if ((jtag_reset_config & RESET_SRST_PULLS_TRST) == 0)
jtag_add_reset(0, 1);
}
jtag_add_reset(0, 0);
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
/* */
static int jim_aice_arp_init_reset(Jim_Interp *interp, int argc, Jim_Obj * const *argv)
{
int e = ERROR_OK;
struct jim_getopt_info goi;
jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
if (goi.argc != 0) {
Jim_WrongNumArgs(goi.interp, 1, goi.argv - 1, "(no params)");
return JIM_ERR;
}
struct command_context *context = current_command_context(interp);
e = aice_init_reset(context);
if (e != ERROR_OK) {
Jim_Obj *obj = Jim_NewIntObj(goi.interp, e);
Jim_SetResultFormatted(goi.interp, "error: %#s", obj);
return JIM_ERR;
}
return JIM_OK;
}
static int jim_aice_names(Jim_Interp *interp, int argc, Jim_Obj *const *argv)
{
struct jim_getopt_info goi;
jim_getopt_setup(&goi, interp, argc - 1, argv + 1);
if (goi.argc != 0) {
Jim_WrongNumArgs(goi.interp, 1, goi.argv, "Too many parameters");
return JIM_ERR;
}
Jim_SetResult(goi.interp, Jim_NewListObj(goi.interp, NULL, 0));
struct jtag_tap *tap;
for (tap = jtag_all_taps(); tap; tap = tap->next_tap)
Jim_ListAppendElement(goi.interp,
Jim_GetResult(goi.interp),
Jim_NewStringObj(goi.interp,
tap->dotted_name, -1));
return JIM_OK;
}
/* */
static const struct command_registration aice_transport_jtag_subcommand_handlers[] = {
{
.name = "init",
.mode = COMMAND_ANY,
.handler = handle_aice_init_command,
.help = "initialize jtag scan chain",
.usage = ""
},
{
.name = "arp_init",
.mode = COMMAND_ANY,
.jim_handler = jim_aice_arp_init,
.help = "Validates JTAG scan chain against the list of "
"declared TAPs.",
},
{
.name = "arp_init-reset",
.mode = COMMAND_ANY,
.jim_handler = jim_aice_arp_init_reset,
.help = "Uses TRST and SRST to try resetting everything on "
"the JTAG scan chain, then performs 'jtag arp_init'."
},
{
.name = "newtap",
.mode = COMMAND_CONFIG,
.jim_handler = jim_aice_newtap,
.help = "Create a new TAP instance named basename.tap_type, "
"and appends it to the scan chain.",
.usage = "basename tap_type ['-expected_id' number]"
},
{
.name = "tapisenabled",
.mode = COMMAND_EXEC,
.jim_handler = jim_jtag_tap_enabler,
.help = "Returns a Tcl boolean (0/1) indicating whether "
"the TAP is enabled (1) or not (0).",
.usage = "tap_name",
},
{
.name = "tapenable",
.mode = COMMAND_EXEC,
.jim_handler = jim_jtag_tap_enabler,
.help = "Try to enable the specified TAP using the "
"'tap-enable' TAP event.",
.usage = "tap_name",
},
{
.name = "tapdisable",
.mode = COMMAND_EXEC,
.jim_handler = jim_jtag_tap_enabler,
.help = "Try to disable the specified TAP using the "
"'tap-disable' TAP event.",
.usage = "tap_name",
},
{
.name = "configure",
.mode = COMMAND_ANY,
.jim_handler = jim_jtag_configure,
.help = "Provide a Tcl handler for the specified "
"TAP event.",
.usage = "tap_name '-event' event_name handler",
},
{
.name = "cget",
.mode = COMMAND_EXEC,
.jim_handler = jim_jtag_configure,
.help = "Return any Tcl handler for the specified "
"TAP event.",
.usage = "tap_name '-event' event_name",
},
{
.name = "names",
.mode = COMMAND_ANY,
.jim_handler = jim_aice_names,
.help = "Returns list of all JTAG tap names.",
},
{
.name = "scan_chain",
.handler = handle_scan_chain_command,
.mode = COMMAND_ANY,
.help = "print current scan chain configuration",
.usage = ""
},
COMMAND_REGISTRATION_DONE
};
/* */
static const struct command_registration aice_transport_command_handlers[] = {
{
.name = "jtag",
.mode = COMMAND_ANY,
.usage = "",
.chain = aice_transport_jtag_subcommand_handlers,
},
COMMAND_REGISTRATION_DONE
};
/* */
static int aice_transport_register_commands(struct command_context *cmd_ctx)
{
return register_commands(cmd_ctx, NULL, aice_transport_command_handlers);
}
/* */
static int aice_transport_init(struct command_context *cmd_ctx)
{
LOG_DEBUG("aice_transport_init");
struct target *t = get_current_target(cmd_ctx);
struct transport *transport;
if (!t) {
LOG_ERROR("no current target");
return ERROR_FAIL;
}
transport = get_current_transport();
if (!transport) {
LOG_ERROR("no transport selected");
return ERROR_FAIL;
}
LOG_DEBUG("current transport %s", transport->name);
return aice_init_targets();
}
/* */
static int aice_transport_select(struct command_context *ctx)
{
LOG_DEBUG("aice_transport_select");
int retval;
retval = aice_transport_register_commands(ctx);
if (retval != ERROR_OK)
return retval;
return ERROR_OK;
}
static struct transport aice_jtag_transport = {
.name = "aice_jtag",
.select = aice_transport_select,
.init = aice_transport_init,
};
const char *aice_transports[] = { "aice_jtag", NULL };
static void aice_constructor(void) __attribute__((constructor));
static void aice_constructor(void)
{
transport_register(&aice_jtag_transport);
}

13
src/jtag/aice/aice_transport.h
View File

@@ -1,13 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* Copyright (C) 2013 by Andes Technology *
* Hsiangkai Wang <hkwang@andestech.com> *
***************************************************************************/
#ifndef OPENOCD_JTAG_AICE_AICE_TRANSPORT_H
#define OPENOCD_JTAG_AICE_AICE_TRANSPORT_H
extern const char *aice_transports[];
#endif /* OPENOCD_JTAG_AICE_AICE_TRANSPORT_H */

4099
src/jtag/aice/aice_usb.c
View File

File diff suppressed because it is too large Load Diff

122
src/jtag/aice/aice_usb.h
View File

@@ -1,122 +0,0 @@
/* SPDX-License-Identifier: GPL-2.0-or-later */
/***************************************************************************
* Copyright (C) 2013 by Andes Technology *
* Hsiangkai Wang <hkwang@andestech.com> *
***************************************************************************/
#ifndef OPENOCD_JTAG_AICE_AICE_USB_H
#define OPENOCD_JTAG_AICE_AICE_USB_H
#include "aice_port.h"
/* AICE USB timeout value */
#define AICE_USB_TIMEOUT 5000
/* AICE USB buffer size */
#define AICE_IN_BUFFER_SIZE 2048
#define AICE_OUT_BUFFER_SIZE 2048
#define AICE_IN_PACKETS_BUFFER_SIZE 2048
#define AICE_OUT_PACKETS_BUFFER_SIZE 2048
#define AICE_IN_BATCH_COMMAND_SIZE 512
#define AICE_OUT_BATCH_COMMAND_SIZE 512
#define AICE_IN_PACK_COMMAND_SIZE 2048
#define AICE_OUT_PACK_COMMAND_SIZE 2048
/* Constants for AICE command READ_CTRL */
#define AICE_READ_CTRL_GET_ICE_STATE 0x00
#define AICE_READ_CTRL_GET_HARDWARE_VERSION 0x01
#define AICE_READ_CTRL_GET_FPGA_VERSION 0x02
#define AICE_READ_CTRL_GET_FIRMWARE_VERSION 0x03
#define AICE_READ_CTRL_GET_JTAG_PIN_STATUS 0x04
#define AICE_READ_CTRL_BATCH_BUF_INFO 0x22
#define AICE_READ_CTRL_BATCH_STATUS 0x23
#define AICE_READ_CTRL_BATCH_BUF0_STATE 0x31
#define AICE_READ_CTRL_BATCH_BUF4_STATE 0x39
#define AICE_READ_CTRL_BATCH_BUF5_STATE 0x3b
/* Constants for AICE command WRITE_CTRL */
#define AICE_WRITE_CTRL_TCK_CONTROL 0x00
#define AICE_WRITE_CTRL_JTAG_PIN_CONTROL 0x01
#define AICE_WRITE_CTRL_CLEAR_TIMEOUT_STATUS 0x02
#define AICE_WRITE_CTRL_RESERVED 0x03
#define AICE_WRITE_CTRL_JTAG_PIN_STATUS 0x04
#define AICE_WRITE_CTRL_CUSTOM_DELAY 0x0d
#define AICE_WRITE_CTRL_BATCH_CTRL 0x20
#define AICE_WRITE_CTRL_BATCH_ITERATION 0x21
#define AICE_WRITE_CTRL_BATCH_DIM_SIZE 0x22
#define AICE_WRITE_CTRL_BATCH_CMD_BUF0_CTRL 0x30
#define AICE_WRITE_CTRL_BATCH_DATA_BUF0_CTRL 0x38
#define AICE_WRITE_CTRL_BATCH_DATA_BUF1_CTRL 0x3a
#define AICE_BATCH_COMMAND_BUFFER_0 0x0
#define AICE_BATCH_COMMAND_BUFFER_1 0x1
#define AICE_BATCH_COMMAND_BUFFER_2 0x2
#define AICE_BATCH_COMMAND_BUFFER_3 0x3
#define AICE_BATCH_DATA_BUFFER_0 0x4
#define AICE_BATCH_DATA_BUFFER_1 0x5
#define AICE_BATCH_DATA_BUFFER_2 0x6
#define AICE_BATCH_DATA_BUFFER_3 0x7
/* Constants for AICE command WRITE_CTRL:TCK_CONTROL */
#define AICE_TCK_CONTROL_TCK3048 0x08
#define AICE_TCK_CONTROL_TCK_SCAN 0x10
/* Constants for AICE command WRITE_CTRL:JTAG_PIN_CONTROL */
#define AICE_JTAG_PIN_CONTROL_SRST 0x01
#define AICE_JTAG_PIN_CONTROL_TRST 0x02
#define AICE_JTAG_PIN_CONTROL_STOP 0x04
#define AICE_JTAG_PIN_CONTROL_RESTART 0x08
/* Constants for AICE command WRITE_CTRL:TCK_CONTROL */
#define AICE_TCK_CONTROL_TCK_SCAN 0x10
/* Custom SRST/DBGI/TRST */
#define AICE_CUSTOM_DELAY_SET_SRST 0x01
#define AICE_CUSTOM_DELAY_CLEAN_SRST 0x02
#define AICE_CUSTOM_DELAY_SET_DBGI 0x04
#define AICE_CUSTOM_DELAY_CLEAN_DBGI 0x08
#define AICE_CUSTOM_DELAY_SET_TRST 0x10
#define AICE_CUSTOM_DELAY_CLEAN_TRST 0x20
struct aice_usb_handler_s {
unsigned int usb_read_ep;
unsigned int usb_write_ep;
struct libusb_device_handle *usb_handle;
};
struct cache_info {
uint32_t set;
uint32_t way;
uint32_t line_size;
uint32_t log2_set;
uint32_t log2_line_size;
};
struct aice_nds32_info {
uint32_t edm_version;
uint32_t r0_backup;
uint32_t r1_backup;
uint32_t host_dtr_backup;
uint32_t target_dtr_backup;
uint32_t edmsw_backup;
uint32_t edm_ctl_backup;
bool debug_under_dex_on;
bool dex_use_psw_on;
bool host_dtr_valid;
bool target_dtr_valid;
enum nds_memory_access access_channel;
enum nds_memory_select memory_select;
enum aice_target_state_s core_state;
bool cache_init;
struct cache_info icache;
struct cache_info dcache;
};
extern struct aice_port_api_s aice_usb_api;
int aice_read_ctrl(uint32_t address, uint32_t *data);
int aice_write_ctrl(uint32_t address, uint32_t data);
#endif /* OPENOCD_JTAG_AICE_AICE_USB_H */

6
src/jtag/interfaces.c
View File

@@ -118,9 +118,6 @@ extern struct adapter_driver linuxgpiod_adapter_driver;
#if BUILD_XLNX_PCIE_XVC == 1
extern struct adapter_driver xlnx_pcie_xvc_adapter_driver;
#endif
#if BUILD_AICE == 1
extern struct adapter_driver aice_adapter_driver;
#endif
#if BUILD_BCM2835GPIO == 1
extern struct adapter_driver bcm2835gpio_adapter_driver;
#endif
@@ -238,9 +235,6 @@ struct adapter_driver *adapter_drivers[] = {
#if BUILD_XLNX_PCIE_XVC == 1
&xlnx_pcie_xvc_adapter_driver,
#endif
#if BUILD_AICE == 1
&aice_adapter_driver,
#endif
#if BUILD_BCM2835GPIO == 1
&bcm2835gpio_adapter_driver,
#endif

6
src/jtag/startup.tcl
View File

@@ -865,12 +865,6 @@ proc ft232r_restore_serial args {
eval ft232r restore_serial $args
}
lappend _telnet_autocomplete_skip "aice serial"
proc "aice serial" {args} {
echo "DEPRECATED! use 'adapter serial' not 'aice serial'"
eval adapter serial $args
}
lappend _telnet_autocomplete_skip cmsis_dap_serial
proc cmsis_dap_serial args {
echo "DEPRECATED! use 'adapter serial' not 'cmsis_dap_serial'"

14
src/rtos/FreeRTOS.c
View File

@@ -71,20 +71,6 @@ static const struct freertos_params freertos_params_list[] = {
&rtos_standard_cortex_m4f_stacking,
&rtos_standard_cortex_m4f_fpu_stacking,
},
{
"nds32_v3", /* target_name */
4, /* thread_count_width; */
4, /* pointer_width; */
16, /* list_next_offset; */
20, /* list_width; */
8, /* list_elem_next_offset; */
12, /* list_elem_content_offset */
0, /* thread_stack_offset; */
52, /* thread_name_offset; */
&rtos_standard_nds32_n1068_stacking, /* stacking_info */
&rtos_standard_cortex_m4f_stacking,
&rtos_standard_cortex_m4f_fpu_stacking,
},
};
static bool freertos_detect_rtos(struct target *target);

47
src/rtos/rtos_standard_stackings.c
View File

@@ -102,45 +102,6 @@ static const struct stack_register_offset rtos_standard_cortex_r4_stack_offsets[
{ 26, 0x04, 32 }, /* CSPR */
};
static const struct stack_register_offset rtos_standard_nds32_n1068_stack_offsets[] = {
{ 0, 0x88, 32 }, /* R0 */
{ 1, 0x8C, 32 }, /* R1 */
{ 2, 0x14, 32 }, /* R2 */
{ 3, 0x18, 32 }, /* R3 */
{ 4, 0x1C, 32 }, /* R4 */
{ 5, 0x20, 32 }, /* R5 */
{ 6, 0x24, 32 }, /* R6 */
{ 7, 0x28, 32 }, /* R7 */
{ 8, 0x2C, 32 }, /* R8 */
{ 9, 0x30, 32 }, /* R9 */
{ 10, 0x34, 32 }, /* R10 */
{ 11, 0x38, 32 }, /* R11 */
{ 12, 0x3C, 32 }, /* R12 */
{ 13, 0x40, 32 }, /* R13 */
{ 14, 0x44, 32 }, /* R14 */
{ 15, 0x48, 32 }, /* R15 */
{ 16, 0x4C, 32 }, /* R16 */
{ 17, 0x50, 32 }, /* R17 */
{ 18, 0x54, 32 }, /* R18 */
{ 19, 0x58, 32 }, /* R19 */
{ 20, 0x5C, 32 }, /* R20 */
{ 21, 0x60, 32 }, /* R21 */
{ 22, 0x64, 32 }, /* R22 */
{ 23, 0x68, 32 }, /* R23 */
{ 24, 0x6C, 32 }, /* R24 */
{ 25, 0x70, 32 }, /* R25 */
{ 26, 0x74, 32 }, /* R26 */
{ 27, 0x78, 32 }, /* R27 */
{ 28, 0x7C, 32 }, /* R28 */
{ 29, 0x80, 32 }, /* R29 */
{ 30, 0x84, 32 }, /* R30 (LP) */
{ 31, 0x00, 32 }, /* R31 (SP) */
{ 32, 0x04, 32 }, /* PSW */
{ 33, 0x08, 32 }, /* IPC */
{ 34, 0x0C, 32 }, /* IPSW */
{ 35, 0x10, 32 }, /* IFC_LP */
};
static target_addr_t rtos_generic_stack_align(struct target *target,
const uint8_t *stack_data, const struct rtos_register_stacking *stacking,
target_addr_t stack_ptr, int align)
@@ -268,11 +229,3 @@ const struct rtos_register_stacking rtos_standard_cortex_r4_stacking = {
.calculate_process_stack = rtos_generic_stack_align8,
.register_offsets = rtos_standard_cortex_r4_stack_offsets
};
const struct rtos_register_stacking rtos_standard_nds32_n1068_stacking = {
.stack_registers_size = 0x90,
.stack_growth_direction = -1,
.num_output_registers = 32,
.calculate_process_stack = rtos_generic_stack_align8,
.register_offsets = rtos_standard_nds32_n1068_stack_offsets
};

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