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https://github.com/linux-msm/openocd.git
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flash/nor: Add support for TI CC3220SF internal flash
Added cc3220sf flash driver to support the TI CC3220SF microcontrollers. Implemented flash driver to support the internal flash of the CC3220SF. The implementation does not support the serial flash of the CC32xx family that requires connection over UART, and not via JTAG/SWD debug. Added config files for both CC32xx devices (no flash) and CC3220SF (with flash). Updated to implement comments from code review. Additional updates to handle remaining comments from review. Additional updates per review. Added code to only request aligned writes and full 32-bit words down to flash helper algorithm. Updated for recent changes in OpenOCD flash code. Removed cc32xx.cfg file made obsolete by this patch. Change-Id: I58fc1478d07238d39c7ef02339f1097a91668c47 Signed-off-by: Edward Fewell <efewell@ti.com> Reviewed-on: http://openocd.zylin.com/4319 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Edward Fewell
committed by
Tomas Vanek
Tomas Vanek
parent
a077715b71
commit
d02de3a8a9
19
contrib/loaders/flash/cc3220sf/Makefile
Normal file
19
contrib/loaders/flash/cc3220sf/Makefile
Normal file
@@ -0,0 +1,19 @@
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BIN2C = ../../../../src/helper/bin2char.sh
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CROSS_COMPILE ?= arm-none-eabi-
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AS = $(CROSS_COMPILE)as
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OBJCOPY = $(CROSS_COMPILE)objcopy
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all: cc3220sf.inc
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%.elf: %.s
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$(AS) $< -o $@
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%.bin: %.elf
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$(OBJCOPY) -Obinary $< $@
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%.inc: %.bin
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$(BIN2C) < $< > $@
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clean:
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-rm -f *.elf *.bin *.inc
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10
contrib/loaders/flash/cc3220sf/cc3220sf.inc
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10
contrib/loaders/flash/cc3220sf/cc3220sf.inc
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@@ -0,0 +1,10 @@
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/* Autogenerated with ../../../../src/helper/bin2char.sh */
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0xdf,0xf8,0x7c,0xa0,0xdf,0xf8,0x7c,0xb0,0xdf,0xf8,0x7c,0xc0,0x01,0xf0,0x7f,0x03,
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0x00,0x2b,0x1e,0xd1,0x4f,0xf0,0x00,0x04,0xcc,0xf8,0x00,0x10,0x03,0x68,0xcb,0xf8,
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0x00,0x30,0x0b,0xf1,0x04,0x0b,0x00,0xf1,0x04,0x00,0xa2,0xf1,0x01,0x02,0x04,0xf1,
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0x01,0x04,0x01,0xf1,0x04,0x01,0x00,0x2a,0x01,0xd0,0x20,0x2c,0xee,0xd1,0xcc,0xf8,
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0x20,0xa0,0xdc,0xf8,0x20,0x30,0x13,0xf0,0x01,0x0f,0xfa,0xd1,0x00,0x2a,0xd7,0xd1,
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0x13,0xe0,0xcc,0xf8,0x00,0x10,0x03,0x68,0xcc,0xf8,0x04,0x30,0xcc,0xf8,0x08,0xa0,
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0xdc,0xf8,0x08,0x30,0x13,0xf0,0x01,0x0f,0xfa,0xd1,0xa2,0xf1,0x01,0x02,0x00,0xf1,
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0x04,0x00,0x01,0xf1,0x04,0x01,0x00,0x2a,0xc2,0xd1,0x00,0xbe,0x01,0xbe,0xfc,0xe7,
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0x01,0x00,0x42,0xa4,0x00,0xd1,0x0f,0x40,0x00,0xd0,0x0f,0x40,
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93
contrib/loaders/flash/cc3220sf/cc3220sf.s
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93
contrib/loaders/flash/cc3220sf/cc3220sf.s
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@@ -0,0 +1,93 @@
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/***************************************************************************
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* Copyright (C) 2017 by Texas Instruments, Inc. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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/* Params:
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* r0 = buffer start address (in)
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* r1 = flash destination address (in)
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* r2 = number of words to write (in/out)
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*/
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.text
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.cpu cortex-m4
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.code 16
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.thumb
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.syntax unified
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.align 2
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/* r3 = scratchpad
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* r4 = buffer word counter
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* r10 = flash programming key
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* r11 = base FWB address
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* r12 = base flash regs address
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*/
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start:
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ldr r10, =0xa4420001 /* flash programming key */
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ldr r11, =0x400fd100 /* base of FWB */
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ldr r12, =0x400fd000 /* base of flash regs */
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and r3, r1, #0x7f /* is the dest address 32 word aligned? */
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cmp r3, #0
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bne program_word /* if not aligned do one word at a time */
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/* program using the write buffers */
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program_buffer:
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mov r4, #0 /* start the buffer word counter at 0 */
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str r1, [r12] /* store the dest addr in FMA */
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fill_buffer:
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ldr r3, [r0] /* get the word to write to FWB */
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str r3, [r11] /* store the word in the FWB */
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add r11, r11, #4 /* increment the FWB pointer */
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add r0, r0, #4 /* increment the source pointer */
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sub r2, r2, #1 /* decrement the total word counter */
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add r4, r4, #1 /* increment the buffer word counter */
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add r1, r1, #4 /* increment the dest pointer */
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cmp r2, #0 /* is the total word counter now 0? */
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beq buffer_ready /* go to end if total word counter is 0 */
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cmp r4, #32 /* is the buffer word counter now 32? */
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bne fill_buffer /* go to continue to fill buffer */
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buffer_ready:
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str r10, [r12, #0x20] /* store the key and write bit to FMC2 */
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wait_buffer_done:
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ldr r3, [r12, #0x20] /* read FMC2 */
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tst r3, #1 /* see if the write bit is cleared */
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bne wait_buffer_done /* go to read FMC2 if bit not cleared */
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cmp r2, #0 /* is the total word counter now 0? */
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bne start /* go if there is more to program */
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b exit
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/* program just one word */
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program_word:
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str r1, [r12] /* store the dest addr in FMA */
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ldr r3, [r0] /* get the word to write to FMD */
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str r3, [r12, #0x4] /* store the word in FMD */
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str r10, [r12, #0x8] /* store the key and write bit to FMC */
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wait_word_done:
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ldr r3, [r12, #0x8] /* read FMC */
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tst r3, #1 /* see if the write bit is cleared */
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bne wait_word_done /* go to read FMC if bit not cleared */
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sub r2, r2, #1 /* decrement the total word counter */
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add r0, r0, #4 /* increment the source pointer */
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add r1, r1, #4 /* increment the dest pointer */
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cmp r2, #0 /* is the total word counter now 0 */
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bne start /* go if there is more to program */
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/* end */
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exit:
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bkpt #0
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bkpt #1
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b exit
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@@ -5578,6 +5578,20 @@ Triggering a mass erase is also useful when users want to disable readout protec
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@end deffn
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@deffn {Flash Driver} cc3220sf
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The CC3220SF version of the SimpleLink CC32xx microcontrollers from Texas
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Instruments includes 1MB of internal flash. The cc3220sf flash driver only
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supports the internal flash. The serial flash on SimpleLink boards is
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programmed via the bootloader over a UART connection. Security features of
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the CC3220SF may erase the internal flash during power on reset. Refer to
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documentation at @url{www.ti.com/cc3220sf} for details on security features
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and programming the serial flash.
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@example
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flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
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@end example
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@end deffn
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@deffn {Flash Driver} efm32
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All members of the EFM32 microcontroller family from Energy Micro include
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internal flash and use ARM Cortex-M3 cores. The driver automatically recognizes
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@@ -19,6 +19,7 @@ NOR_DRIVERS = \
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%D%/atsamv.c \
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%D%/avrf.c \
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%D%/bluenrg-x.c \
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%D%/cc3220sf.c \
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%D%/cfi.c \
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%D%/dsp5680xx_flash.c \
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%D%/efm32.c \
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@@ -63,6 +64,7 @@ NOR_DRIVERS = \
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NORHEADERS = \
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%D%/core.h \
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%D%/cc3220sf.h \
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%D%/cfi.h \
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%D%/driver.h \
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%D%/imp.h \
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529
src/flash/nor/cc3220sf.c
Normal file
529
src/flash/nor/cc3220sf.c
Normal file
File diff suppressed because it is too large
Load Diff
45
src/flash/nor/cc3220sf.h
Normal file
45
src/flash/nor/cc3220sf.h
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@@ -0,0 +1,45 @@
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/***************************************************************************
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* Copyright (C) 2017 by Texas Instruments, Inc. *
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* *
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* This program is free software; you can redistribute it and/or modify *
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* it under the terms of the GNU General Public License as published by *
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* the Free Software Foundation; either version 2 of the License, or *
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* (at your option) any later version. *
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* *
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* This program is distributed in the hope that it will be useful, *
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* but WITHOUT ANY WARRANTY; without even the implied warranty of *
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
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* GNU General Public License for more details. *
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* *
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* You should have received a copy of the GNU General Public License *
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* along with this program. If not, see <http://www.gnu.org/licenses/>. *
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***************************************************************************/
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#ifndef OPENOCD_FLASH_NOR_CC3220SF_H
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#define OPENOCD_FLASH_NOR_CC3220SF_H
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/* CC3220SF device types */
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#define CC3220_NO_TYPE 0 /* Device type not determined yet */
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#define CC3220_OTHER 1 /* CC3220 variant without flash */
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#define CC3220SF 2 /* CC3220SF variant with flash */
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/* Flash parameters */
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#define FLASH_BASE_ADDR 0x01000000
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#define FLASH_SECTOR_SIZE 2048
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#define FLASH_NUM_SECTORS 512
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/* CC2200SF flash registers */
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#define FMA_REGISTER_ADDR 0x400FD000
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#define FMC_REGISTER_ADDR 0x400FD008
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#define FMC_DEFAULT_VALUE 0xA4420000
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#define FMC_ERASE_BIT 0x00000002
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#define FMC_MERASE_BIT 0x00000004
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#define FMC_ERASE_VALUE (FMC_DEFAULT_VALUE | FMC_ERASE_BIT)
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#define FMC_MERASE_VALUE (FMC_DEFAULT_VALUE | FMC_MERASE_BIT)
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/* Flash helper algorithm for CC3220SF */
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const uint8_t cc3220sf_algo[] = {
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#include "../../../contrib/loaders/flash/cc3220sf/cc3220sf.inc"
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};
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#endif /* OPENOCD_FLASH_NOR_CC3220SF_H */
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@@ -32,6 +32,7 @@ extern struct flash_driver ath79_flash;
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extern struct flash_driver atsamv_flash;
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extern struct flash_driver avr_flash;
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extern struct flash_driver bluenrgx_flash;
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extern struct flash_driver cc3220sf_flash;
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extern struct flash_driver cfi_flash;
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extern struct flash_driver dsp5680xx_flash;
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extern struct flash_driver efm32_flash;
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@@ -90,6 +91,7 @@ static struct flash_driver *flash_drivers[] = {
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&atsamv_flash,
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&avr_flash,
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&bluenrgx_flash,
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&cc3220sf_flash,
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&cfi_flash,
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&dsp5680xx_flash,
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&efm32_flash,
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7
tcl/board/ti_cc3220sf_launchpad.cfg
Normal file
7
tcl/board/ti_cc3220sf_launchpad.cfg
Normal file
@@ -0,0 +1,7 @@
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#
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# TI CC3220SF-LaunchXL LaunchPad Evaluation Kit
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#
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source [find interface/xds110.cfg]
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adapter_khz 2500
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transport select swd
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source [find target/ti_cc3220sf.cfg]
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7
tcl/board/ti_cc32xx_launchpad.cfg
Normal file
7
tcl/board/ti_cc32xx_launchpad.cfg
Normal file
@@ -0,0 +1,7 @@
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#
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# TI CC32xx-LaunchXL LaunchPad Evaluation Kit
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#
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source [find interface/xds110.cfg]
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adapter_khz 2500
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transport select swd
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source [find target/ti_cc32xx.cfg]
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@@ -1,54 +0,0 @@
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# Config for Texas Instruments SoC CC32xx family
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source [find target/swj-dp.tcl]
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adapter_khz 100
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source [find target/icepick.cfg]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cc32xx
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}
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#
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# Main DAP
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#
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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if {[using_jtag]} {
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set _DAP_TAPID 0x4BA00477
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} else {
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set _DAP_TAPID 0x2BA01477
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}
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}
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
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jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
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} else {
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swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
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}
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#
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# ICEpick-C (JTAG route controller)
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#
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0B97C02F
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}
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.dap"
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}
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#
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# Cortex-M3 target
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#
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set _TARGETNAME $_CHIPNAME.cpu
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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12
tcl/target/ti_cc3220sf.cfg
Normal file
12
tcl/target/ti_cc3220sf.cfg
Normal file
@@ -0,0 +1,12 @@
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#
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# Texas Instruments CC3220SF - ARM Cortex-M4
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#
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# http://www.ti.com/CC3220SF
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#
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source [find target/swj-dp.tcl]
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source [find target/icepick.cfg]
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source [find target/ti_cc32xx.cfg]
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cc3220sf 0 0 0 0 $_TARGETNAME
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64
tcl/target/ti_cc32xx.cfg
Normal file
64
tcl/target/ti_cc32xx.cfg
Normal file
@@ -0,0 +1,64 @@
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#
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# Texas Instruments CC32xx - ARM Cortex-M4
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#
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# http://www.ti.com/product/CC3200
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# http://www.ti.com/product/CC3220
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#
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source [find target/swj-dp.tcl]
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source [find target/icepick.cfg]
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if { [info exists CHIPNAME] } {
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set _CHIPNAME $CHIPNAME
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} else {
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set _CHIPNAME cc32xx
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}
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#
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# Main DAP
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#
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if { [info exists DAP_TAPID] } {
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set _DAP_TAPID $DAP_TAPID
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} else {
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if {[using_jtag]} {
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set _DAP_TAPID 0x4BA00477
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} else {
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set _DAP_TAPID 0x2BA01477
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}
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}
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|
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME cpu -irlen 4 -ircapture 0x1 -irmask 0xf -expected-id $_DAP_TAPID -disable
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jtag configure $_CHIPNAME.cpu -event tap-enable "icepick_c_tapenable $_CHIPNAME.jrc 0"
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} else {
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swj_newdap $_CHIPNAME cpu -expected-id $_DAP_TAPID
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}
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#
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# ICEpick-C (JTAG route controller)
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#
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if { [info exists JRC_TAPID] } {
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set _JRC_TAPID $JRC_TAPID
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} else {
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set _JRC_TAPID 0x0B97C02F
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}
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|
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if {[using_jtag]} {
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jtag newtap $_CHIPNAME jrc -irlen 6 -ircapture 0x1 -irmask 0x3f -expected-id $_JRC_TAPID -ignore-version
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jtag configure $_CHIPNAME.jrc -event setup "jtag tapenable $_CHIPNAME.cpu"
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}
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set _TARGETNAME $_CHIPNAME.cpu
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dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
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target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
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if { [info exists WORKAREASIZE] } {
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set _WORKAREASIZE $WORKAREASIZE
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} else {
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set _WORKAREASIZE 0x2000
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}
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$_TARGETNAME configure -work-area-phys 0x20000000 -work-area-size $_WORKAREASIZE -work-area-backup 0
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|
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reset_config srst_only
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adapter_nsrst_delay 1100
|
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