src/flash/nor: flash driver for RSL10

Add new flash driver for internal flash of onsemi RSL10 device.

Valgrind-clean. Clang AddressSanitizer shows no errors.

Signed-off-by: Toms Stūrmanis <toms.sturmanis@gmail.com>
Change-Id: I8030542cb9805e94f56d7a69404cef5d88d6dd5a
Reviewed-on: https://review.openocd.org/c/openocd/+/7115
Tested-by: jenkins
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>

contrib/loaders/flash/rsl10/Makefile

@@ -0,0 +1,30 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+BIN2C = ../../../../src/helper/bin2char.sh
+
+CROSS_COMPILE ?= arm-none-eabi-
+
+CC=$(CROSS_COMPILE)gcc
+OBJCOPY=$(CROSS_COMPILE)objcopy
+OBJDUMP=$(CROSS_COMPILE)objdump
+
+CFLAGS = -static -nostartfiles -mlittle-endian -Wa,-EL
+
+all: rom_launcher.inc
+
+.PHONY: clean
+
+%.elf: %.S
+	$(CC) $(CFLAGS) $< -o $@
+
+%.lst: %.elf
+	$(OBJDUMP) -S $< > $@
+
+%.bin: %.elf
+	$(OBJCOPY) -Obinary $< $@
+
+%.inc: %.bin
+	$(BIN2C) < $< > $@
+
+clean:
+	-rm -f *.elf *.lst *.bin *.inc

contrib/loaders/flash/rsl10/rom_launcher.S

@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+/***************************************************************************
+ *   Copyright (C) 2022 by Toms Stūrmanis                                  *
+ *   toms.sturmanis@gmail.com                                              *
+ ***************************************************************************/
+
+	.text
+	.syntax unified
+	.cpu cortex-m4
+	.thumb
+    .align 8
+
+/*
+ * Params :
+ * r0-r2 = arguments
+ * r3 = target address in rom
+ */
+
+	.thumb_func
+	.global _start
+_start:
+launch_program_in_rom:
+    // variables are already set, addres to jump is in r3
+    blx r3
+exit:
+	// Wait for OpenOCD
+	bkpt	#0x00

contrib/loaders/flash/rsl10/rom_launcher.inc

@@ -0,0 +1,2 @@
+/* Autogenerated with ../../../../src/helper/bin2char.sh */
+0x98,0x47,0x00,0xbe,

doc/openocd.texi

@@ -7396,6 +7396,31 @@ flash bank $_FLASHNAME rp2040_flash $_FLASHBASE $_FLASHSIZE 1 32 $_TARGETNAME
 @end example
 @end deffn
 
+@deffn {Flash Driver} {rsl10}
+Supports Onsemi RSL10 microcontroller flash memory.  Uses functions
+stored in ROM to control flash memory interface.
+
+@example
+flash bank $_FLASHNAME rsl10 $_FLASHBASE $_FLASHSIZE 0 0 $_TARGETNAME
+@end example
+
+@deffn {Command} {rsl10 lock} key1 key2 key3 key4
+Writes @var{key1 key2 key3 key4} words to @var{0x81044 0x81048 0x8104c
+0x8050}. Locks debug port by writing @var{0x4C6F634B} to @var{0x81040}.
+
+To unlock use the @command{rsl10 unlock key1 key2 key3 key4} command.
+@end deffn
+
+@deffn {Command} {rsl10 unlock} key1 key2 key3 key4
+Unlocks debug port, by writing @var{key1 key2 key3 key4} words to
+registers through DAP, and clears @var{0x81040} address in flash to 0x1.
+@end deffn
+
+@deffn {Command} {rsl10 mass_erase}
+Erases all unprotected flash sectors.
+@end deffn
+@end deffn
+
 @deffn {Flash Driver} {sim3x}
 All members of the SiM3 microcontroller family from Silicon Laboratories
 include internal flash and use ARM Cortex-M3 cores. It supports both JTAG

src/flash/nor/Makefile.am

@@ -56,6 +56,7 @@ NOR_DRIVERS = \
 	%D%/psoc6.c \
 	%D%/renesas_rpchf.c \
 	%D%/rp2040.c \
+	%D%/rsl10.c \
 	%D%/sfdp.c \
 	%D%/sh_qspi.c \
 	%D%/sim3x.c \

src/flash/nor/drivers.c

@@ -78,6 +78,7 @@ extern const struct flash_driver w600_flash;
 extern const struct flash_driver xcf_flash;
 extern const struct flash_driver xmc1xxx_flash;
 extern const struct flash_driver xmc4xxx_flash;
+extern const struct flash_driver rsl10_flash;
 
 /**
  * The list of built-in flash drivers.
@@ -153,6 +154,7 @@ static const struct flash_driver * const flash_drivers[] = {
 	&xmc1xxx_flash,
 	&xmc4xxx_flash,
 	&w600_flash,
+	&rsl10_flash,
 	NULL,
 };
 

tcl/target/rsl10.cfg

@@ -0,0 +1,70 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+#
+# RSL10: ARM Cortex-M3
+#
+
+source [find target/swj-dp.tcl]
+
+if { [info exists CHIPNAME] } {
+	set _CHIPNAME $CHIPNAME
+} else {
+	set _CHIPNAME rsl10
+}
+
+if { [info exists WORKAREASIZE] } {
+   set _WORKAREASIZE $WORKAREASIZE
+} else {
+   set _WORKAREASIZE 0x8000
+}
+
+if { [info exists CPUTAPID] } {
+	set _CPUTAPID $CPUTAPID
+} else {
+	set _CPUTAPID 0x2ba01477
+}
+
+swj_newdap $_CHIPNAME cpu -expected-id $_CPUTAPID
+dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME cortex_m -dap $_CHIPNAME.dap
+
+$_TARGETNAME configure -work-area-phys 0x200000 -work-area-size $_WORKAREASIZE -work-area-backup 0
+
+# TODO: configure reset
+# reset_config srst_only srst_nogate connect_assert_srst
+
+$_TARGETNAME configure -event examine-fail rsl10_lock_warning
+
+proc rsl10_check_connection {} {
+    set target [target current]
+    set dap [$target cget -dap]
+
+	set IDR [$dap apreg 0 0xfc]
+	if {$IDR != 0x24770011} {
+		echo "Error: Cannot access RSL10 AP, maybe connection problem!"
+		return 1
+	}
+    return 0
+}
+
+proc rsl10_lock_warning {} {
+    if {[rsl10_check_connection]} {return}
+
+    poll off
+    echo "****** WARNING ******"
+    echo "RSL10 device probably has lock engaged."
+    echo "Debug access is denied."
+    echo "Use 'rsl10 unlock key1 key2 key3 key4' to erase and unlock the device."
+    echo "****** ....... ******"
+    echo ""
+}
+
+flash bank $_CHIPNAME.main rsl10 0x00100000 0x60000 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvr1 rsl10 0x00080000 0x800 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvr2 rsl10 0x00080800 0x800 0 0 $_TARGETNAME
+flash bank $_CHIPNAME.nvr3 rsl10 0x00081000 0x800 0 0 $_TARGETNAME
+
+# TODO: implement flashing for nvr4
+# flash bank $_CHIPNAME.nvr4 rsl10 0x00081800 0x400 0 0 $_TARGETNAME