David Brownell <david-b@pacbell.net>:

NAND support for DaVinci-family drivers, with HW ECC support.
Declare the NAND chip on the DM355 EVM board.

Currently tested on DM355 for Linux interop using the standard
large page (2KB) chip in the EVM socket; "hwecc1" and "hwecc4"
work fine.  (Using hwecc4 relies on patches that haven't quite
made it through the Linux-MTD bottlenecks yet.)

Not yet tested:  1-bit on small-page (although it's hard to see
how that could fail); 4-bit on small page (picky layout issues);
the "hwecc_infix" mode (primarily for older boot ROMs; testing
there is blocked on having new bootloader code).


git-svn-id: svn://svn.berlios.de/openocd/trunk@1903 b42882b7-edfa-0310-969c-e2dbd0fdcd60

doc/openocd.texi

@@ -2804,6 +2804,23 @@ As noted above, the @command{nand device} command allows
 driver-specific options and behaviors.
 Some controllers also activate controller-specific commands.
 
+@deffn {NAND Driver} davinci
+This driver handles the NAND controllers found on DaVinci family
+chips from Texas Instruments.
+It takes three extra parameters:
+address of the NAND chip;
+hardware ECC mode to use (hwecc1, hwecc4, hwecc4_infix);
+address of the AEMIF controller on this processor.
+@example
+nand device davinci dm355.arm 0x02000000 hwecc4 0x01e10000
+@end example
+All DaVinci processors support the single-bit ECC hardware,
+and newer ones also support the four-bit ECC hardware.
+The @code{write_page} and @code{read_page} methods are used
+to implement those ECC modes, unless they are disabled using
+the @command{nand raw_access} command.
+@end deffn
+
 @deffn {NAND Driver} lpc3180
 These controllers require an extra @command{nand device}
 parameter:  the clock rate used by the controller.

src/flash/Makefile.am

@@ -6,7 +6,7 @@ AM_CPPFLAGS = \
 METASOURCES = AUTO
 noinst_LTLIBRARIES = libflash.la
 libflash_la_SOURCES = \
-	flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c \
+	flash.c lpc2000.c cfi.c non_cfi.c at91sam7.c davinci_nand.c \
 	str7x.c str9x.c aduc702x.c nand.c nand_ecc.c nand_ecc_kw.c \
 	lpc3180_nand_controller.c stellaris.c str9xpec.c stm32x.c tms470.c \
 	ecos.c orion_nand.c s3c24xx_nand.c s3c2410_nand.c s3c2412_nand.c \

src/flash/nand.c

@@ -48,6 +48,7 @@ static int nand_write_page(struct nand_device_s *device, u32 page, u8 *data, u32
 
 /* NAND flash controller
  */
+extern nand_flash_controller_t davinci_nand_controller;
 extern nand_flash_controller_t lpc3180_nand_controller;
 extern nand_flash_controller_t orion_nand_controller;
 extern nand_flash_controller_t s3c2410_nand_controller;
@@ -59,6 +60,7 @@ extern nand_flash_controller_t s3c2443_nand_controller;
 
 static nand_flash_controller_t *nand_flash_controllers[] =
 {
+	&davinci_nand_controller,
 	&lpc3180_nand_controller,
 	&orion_nand_controller,
 	&s3c2410_nand_controller,

src/target/board/dm355evm.cfg

@@ -105,7 +105,15 @@ proc dm355evm_init {} {
 	# FIXME setup
 }
 
+# NAND -- socket has two chipselects, MT29F16G08FAA puts 1GByte on each one.
+#
+# NOTE:  "hwecc4" here presumes that if you're using the standard 2GB NAND
+# you either (a) have 'new' DM355 chips, with boot ROMs that don't need to
+# use "hwecc4_infix" for the UBL; or else (b) aren't updating anything that
+# needs infix layout ... like an old UBL, old U-Boot, old MVL kernel, etc.
+nand device davinci 0 0x02000000 hwecc4 0x01e10000
+nand device davinci 0 0x02004000 hwecc4 0x01e10000
+
 # FIXME
-#  - declare the NAND flash; use the 4-bit ECC
 #  - support writing UBL with its header (new layout only with new ROMs)
-#  - support writing ABL/U-Boot with its header (both layouts)
+#  - support writing ABL/U-Boot with its header (new layout)