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target aarch64: rework memory read/write to use 8/16/32 bit operations

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The existing code only used Memory Access mode to read memory,
which uses 32 bit operations only.
Rework the code to check the alignment/size of the read/write operation,
and use the Memory Access mode to read aligned 32 bit memory.
When using unaligned access, or 8 or 16 bit reads, use LDR{BHW} and STR{BHW}
instead.

The exception handling is still the same as it was before (meaning it breaks
when things go wrong), but I can now read an 8 bit register correctly.

Change-Id: I739a5ee825c0226ed4a89c32895cc2a047b8dc15
Signed-off-by: Bas Vermeulen <bas@daedalean.ai>
Reviewed-on: http://openocd.zylin.com/4301
Tested-by: jenkins
Reviewed-by: Matthias Welwarsky <matthias@welwarsky.de>
Reviewed-by: Paul Fertser <fercerpav@gmail.com>
This commit is contained in:
Bas Vermeulen
2017-11-26 22:31:55 +01:00
committed by Paul Fertser
parent bb976e3c38
commit ada631cc5f
3 changed files with 284 additions and 187 deletions
Download Patch File Download Diff File Expand all files Collapse all files

445
src/target/aarch64.c
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File diff suppressed because it is too large Load Diff

12
src/target/armv8_opcodes.c
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@@ -42,6 +42,12 @@ static const uint32_t a64_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_DCCIVAC] = ARMV8_SYS(SYSTEM_DCCIVAC, 0),
[ARMV8_OPC_ICIVAU] = ARMV8_SYS(SYSTEM_ICIVAU, 0),
[ARMV8_OPC_HLT] = ARMV8_HLT(11),
[ARMV8_OPC_LDRB_IP] = ARMV8_LDRB_IP(1, 0),
[ARMV8_OPC_LDRH_IP] = ARMV8_LDRH_IP(1, 0),
[ARMV8_OPC_LDRW_IP] = ARMV8_LDRW_IP(1, 0),
[ARMV8_OPC_STRB_IP] = ARMV8_STRB_IP(1, 0),
[ARMV8_OPC_STRH_IP] = ARMV8_STRH_IP(1, 0),
[ARMV8_OPC_STRW_IP] = ARMV8_STRW_IP(1, 0),
};
static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
@@ -63,6 +69,12 @@ static const uint32_t t32_opcodes[ARMV8_OPC_NUM] = {
[ARMV8_OPC_DCCIVAC] = ARMV4_5_MCR(15, 0, 0, 7, 14, 1),
[ARMV8_OPC_ICIVAU] = ARMV4_5_MCR(15, 0, 0, 7, 5, 1),
[ARMV8_OPC_HLT] = ARMV8_HLT_A1(11),
[ARMV8_OPC_LDRB_IP] = ARMV4_5_LDRB_IP(1, 0),
[ARMV8_OPC_LDRH_IP] = ARMV4_5_LDRH_IP(1, 0),
[ARMV8_OPC_LDRW_IP] = ARMV4_5_LDRW_IP(1, 0),
[ARMV8_OPC_STRB_IP] = ARMV4_5_STRB_IP(1, 0),
[ARMV8_OPC_STRH_IP] = ARMV4_5_STRH_IP(1, 0),
[ARMV8_OPC_STRW_IP] = ARMV4_5_STRW_IP(1, 0),
};
void armv8_select_opcodes(struct armv8_common *armv8, bool state_is_aarch64)

14
src/target/armv8_opcodes.h
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@@ -159,6 +159,14 @@
#define ARMV8_MOVFSP_32(Rt) (0x11000000 | (0x1f << 5) | (Rt))
#define ARMV8_MOVTSP_32(Rt) (0x11000000 | (Rt << 5) | (0x1F))
#define ARMV8_LDRB_IP(Rd, Rn) (0x38401400 | (Rn << 5) | Rd)
#define ARMV8_LDRH_IP(Rd, Rn) (0x78402400 | (Rn << 5) | Rd)
#define ARMV8_LDRW_IP(Rd, Rn) (0xb8404400 | (Rn << 5) | Rd)
#define ARMV8_STRB_IP(Rd, Rn) (0x38001400 | (Rn << 5) | Rd)
#define ARMV8_STRH_IP(Rd, Rn) (0x78002400 | (Rn << 5) | Rd)
#define ARMV8_STRW_IP(Rd, Rn) (0xb8004400 | (Rn << 5) | Rd)
#define ARMV8_SYS(System, Rt) (0xD5080000 | ((System) << 5) | Rt)
enum armv8_opcode {
@@ -180,6 +188,12 @@ enum armv8_opcode {
ARMV8_OPC_DCCIVAC,
ARMV8_OPC_ICIVAU,
ARMV8_OPC_HLT,
ARMV8_OPC_STRB_IP,
ARMV8_OPC_STRH_IP,
ARMV8_OPC_STRW_IP,
ARMV8_OPC_LDRB_IP,
ARMV8_OPC_LDRH_IP,
ARMV8_OPC_LDRW_IP,
ARMV8_OPC_NUM,
};