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flash: fix typos and duplicated words

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Fix typos and duplicated words in comments and strings.

Change-Id: I64282c7018462deefeeb8e5f4d0d81942425b3fc
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/5758
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
Reviewed-by: Christopher Head <chead@zaber.com>
This commit is contained in:
Antonio Borneo
2020-07-12 00:00:47 +02:00
parent f5cc8360fd
commit 9db3e9879d
42 changed files with 125 additions and 125 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/flash/nand/driver.h
View File

@@ -94,7 +94,7 @@ typedef int (*nand_driver_walker_t)(struct nand_flash_controller *c, void *);
* Walk the list of drivers, encapsulating the data structure type.
* Application state/context can be passed through the @c x pointer.
* @param f The callback function to invoke for each function.
* @param x For use as private data storate, passed directly to @c f.
* @param x For use as private data storage, passed directly to @c f.
* @returns ERROR_OK if successful, or the non-zero return value of @c f.
* This allows a walker to terminate the loop early.
*/

2
src/flash/nand/fileio.c
View File

@@ -206,7 +206,7 @@ int nand_fileio_read(struct nand_device *nand, struct nand_fileio_state *s)
} else if (s->oob_format & NAND_OOB_SW_ECC_KW) {
/*
* In this case eccpos is not used as
* the ECC data is always stored contigously
* the ECC data is always stored contiguously
* at the end of the OOB area. It consists
* of 10 bytes per 512-byte data block.
*/

2
src/flash/nand/lpc3180.c
View File

@@ -232,7 +232,7 @@ static int lpc3180_init(struct nand_device *nand)
/* FLASHCLK_CTRL = 0x05 (enable clock for SLC flash controller) */
target_write_u32(target, 0x400040c8, 0x05);
/* after reset set other registers of SLC so reset calling is here at the begining*/
/* after reset set other registers of SLC so reset calling is here at the beginning */
lpc3180_reset(nand);
/* SLC_CFG = 0x (Force nCE assert, DMA ECC enabled, ECC enabled, DMA burst enabled,

24
src/flash/nand/lpc32xx.c
View File

@@ -42,7 +42,7 @@ extern int nand_correct_data(struct nand_device *nand, u_char *dat,
* read/write data to the SLC controller.
* - DMA descriptors will be put at start of working area,
* - Hardware generated ECC will be stored at ECC_OFFS
* - OOB wil be read/written from/to SPARE_OFFS
* - OOB will be read/written from/to SPARE_OFFS
* - Actual page data will be read from/to DATA_OFFS
* There are unused holes between the used areas.
*/
@@ -317,7 +317,7 @@ static int lpc32xx_init(struct nand_device *nand)
}
/* after reset set other registers of SLC,
* so reset calling is here at the begining
* so reset calling is here at the beginning
*/
retval = lpc32xx_reset(nand);
if (ERROR_OK != retval)
@@ -769,7 +769,7 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
* 2. Copy generated ECC data from Register to Spare Area
* 3. X'fer next 256 bytes of data from Memory to Flash.
* 4. Copy generated ECC data from Register to Spare Area.
* 5. X'fer 16 byets of Spare area from Memory to Flash.
* 5. X'fer 16 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Small Block NAND
* ----------------------------------------------------------
* 1. X'fer 256 bytes of data from Flash to Memory.
@@ -779,13 +779,13 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
* 5. X'fer 16 bytes of Spare area from Flash to Memory.
* Write Operation Sequence for Large Block NAND
* ----------------------------------------------------------
* 1. Steps(1-4) of Write Operations repeate for four times
* 1. Steps(1-4) of Write Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Large Block NAND
* ----------------------------------------------------------
* 1. Steps(1-4) of Read Operations repeate for four times
* 1. Steps(1-4) of Read Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
@@ -842,7 +842,7 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
* 2. Copy generated ECC data from Register to Spare Area
* 3. X'fer next 256 bytes of data from Memory to Flash.
* 4. Copy generated ECC data from Register to Spare Area.
* 5. X'fer 16 byets of Spare area from Memory to Flash.
* 5. X'fer 16 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Small Block NAND
* ----------------------------------------------------------
* 1. X'fer 256 bytes of data from Flash to Memory.
@@ -852,13 +852,13 @@ static int lpc32xx_make_dma_list(uint32_t target_mem_base, uint32_t page_size,
* 5. X'fer 16 bytes of Spare area from Flash to Memory.
* Write Operation Sequence for Large Block NAND
* ----------------------------------------------------------
* 1. Steps(1-4) of Write Operations repeate for four times
* 1. Steps(1-4) of Write Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Memory to Flash.
* Read Operation Sequence for Large Block NAND
* ----------------------------------------------------------
* 1. Steps(1-4) of Read Operations repeate for four times
* 1. Steps(1-4) of Read Operations repeated for four times
* which generates 16 DMA descriptors to X'fer 2048 bytes of
* data & 32 bytes of ECC data.
* 2. X'fer 64 bytes of Spare area from Flash to Memory.
@@ -1044,7 +1044,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
target_mem_base = pworking_area->address;
/*
* Skip writting page which has all 0xFF data as this will
* Skip writing page which has all 0xFF data as this will
* generate 0x0 value.
*/
if (data && !oob) {
@@ -1102,7 +1102,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
return retval;
}
/* Write first decriptor to DMA controller */
/* Write first descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
sizeof(dmac_ll_t) / 4,
(uint8_t *)dmalist);
@@ -1159,7 +1159,7 @@ static int lpc32xx_write_page_slc(struct nand_device *nand,
return retval;
}
/* Write OOB decriptor to DMA controller */
/* Write OOB descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
sizeof(dmac_ll_t) / 4,
(uint8_t *)(&dmalist[nll-1]));
@@ -1487,7 +1487,7 @@ static int lpc32xx_read_page_slc(struct nand_device *nand,
return retval;
}
/* Write first decriptor to DMA controller */
/* Write first descriptor to DMA controller */
retval = target_write_memory(target, 0x31000100, 4,
sizeof(dmac_ll_t) / 4, (uint8_t *)dmalist);
if (ERROR_OK != retval) {

16
src/flash/nand/mx3.c
View File

@@ -149,7 +149,7 @@ static int imx31_init(struct nand_device *nand)
uint32_t gpr_register_content;
target_read_u32(target, MX3_GPR, &gpr_register_content);
if (gpr_register_content & 0x00000060) {
LOG_ERROR("pins mode overrided by GPR");
LOG_ERROR("pins mode overridden by GPR");
return ERROR_FAIL;
}
}
@@ -414,10 +414,10 @@ static int imx31_write_page(struct nand_device *nand, uint32_t page,
if (oob) {
if (mx3_nf_info->flags.hw_ecc_enabled) {
/*
* part of spare block will be overrided by hardware
* part of spare block will be overridden by hardware
* ECC generator
*/
LOG_DEBUG("part of spare block will be overrided by hardware ECC generator");
LOG_DEBUG("part of spare block will be overridden by hardware ECC generator");
}
target_write_buffer(target, MX3_NF_SPARE_BUFFER0, oob_size, oob);
}
@@ -530,7 +530,7 @@ static int initialize_nf_controller(struct nand_device *nand)
struct mx3_nf_controller *mx3_nf_info = nand->controller_priv;
struct target *target = nand->target;
/*
* resets NAND flash controller in zero time ? I dont know.
* resets NAND flash controller in zero time ? I don't know.
*/
target_write_u16(target, MX3_NF_CFG1, MX3_NF_BIT_RESET_EN);
{
@@ -680,18 +680,18 @@ static int do_data_output(struct nand_device *nand)
target_read_u16 (target, MX3_NF_ECCSTATUS, &ecc_status);
switch (ecc_status & 0x000c) {
case 1 << 2:
LOG_DEBUG("main area readed with 1 (correctable) error");
LOG_DEBUG("main area read with 1 (correctable) error");
break;
case 2 << 2:
LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
LOG_DEBUG("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
}
switch (ecc_status & 0x0003) {
case 1:
LOG_DEBUG("spare area readed with 1 (correctable) error");
LOG_DEBUG("spare area read with 1 (correctable) error");
break;
case 2:
LOG_DEBUG("main area readed with more than 1 (incorrectable) error");
LOG_DEBUG("main area read with more than 1 (incorrectable) error");
return ERROR_NAND_OPERATION_FAILED;
}
}

12
src/flash/nand/mxc.c
View File

@@ -136,7 +136,7 @@ NAND_DEVICE_COMMAND_HANDLER(mxc_nand_device_command)
(nand->target->endianness == TARGET_LITTLE_ENDIAN);
/*
* should factory bad block indicator be swaped
* should factory bad block indicator be swapped
* as a workaround for how the nfc handles pages.
*/
if (CMD_ARGC > 4 && strcmp(CMD_ARGV[4], "biswap") == 0) {
@@ -181,7 +181,7 @@ static const struct command_registration mxc_sub_command_handlers[] = {
.name = "biswap",
.mode = COMMAND_EXEC,
.handler = handle_mxc_biswap_command,
.help = "Turns on/off bad block information swaping from main area, "
.help = "Turns on/off bad block information swapping from main area, "
"without parameter query status.",
.usage = "bank_id ['enable'|'disable']",
},
@@ -400,7 +400,7 @@ static int mxc_command(struct nand_device *nand, uint8_t command)
mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break;
default:
/* Ohter command use the default 'One page data out' FDO */
/* Other command use the default 'One page data out' FDO */
mxc_nf_info->optype = MXC_NF_DATAOUT_PAGE;
break;
}
@@ -502,10 +502,10 @@ static int mxc_write_page(struct nand_device *nand, uint32_t page,
if (oob) {
if (mxc_nf_info->flags.hw_ecc_enabled) {
/*
* part of spare block will be overrided by hardware
* part of spare block will be overridden by hardware
* ECC generator
*/
LOG_DEBUG("part of spare block will be overrided "
LOG_DEBUG("part of spare block will be overridden "
"by hardware ECC generator");
}
if (nfc_is_v1())
@@ -710,7 +710,7 @@ static int initialize_nf_controller(struct nand_device *nand)
uint16_t work_mode = 0;
uint16_t temp;
/*
* resets NAND flash controller in zero time ? I dont know.
* resets NAND flash controller in zero time ? I don't know.
*/
target_write_u16(target, MXC_NF_CFG1, MXC_NF_BIT_RESET_EN);
if (mxc_nf_info->mxc_version == MXC_VERSION_MX27)

6
src/flash/nor/at91sam3.c
View File

@@ -21,7 +21,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
****************************************************************************/
/* Some of the the lower level code was based on code supplied by
/* Some of the lower level code was based on code supplied by
* ATMEL under this copyright. */
/* BEGIN ATMEL COPYRIGHT */
@@ -3095,7 +3095,7 @@ FLASH_BANK_COMMAND_HANDLER(sam3_flash_bank_command)
}
/**
* Remove all chips from the internal list without distingushing which one
* Remove all chips from the internal list without distinguishing which one
* is owned by this bank. This simplification works only for one shot
* deallocation like current flash_free_all_banks()
*/
@@ -3398,7 +3398,7 @@ static int sam3_write(struct flash_bank *bank,
struct sam3_bank_private *pPrivate;
uint8_t *pagebuffer;
/* incase we bail further below, set this to null */
/* in case we bail further below, set this to null */
pagebuffer = NULL;
/* ignore dumb requests */

6
src/flash/nor/at91sam4.c
View File

@@ -22,7 +22,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
****************************************************************************/
/* Some of the the lower level code was based on code supplied by
/* Some of the lower level code was based on code supplied by
* ATMEL under this copyright. */
/* BEGIN ATMEL COPYRIGHT */
@@ -2509,7 +2509,7 @@ FLASH_BANK_COMMAND_HANDLER(sam4_flash_bank_command)
}
/**
* Remove all chips from the internal list without distingushing which one
* Remove all chips from the internal list without distinguishing which one
* is owned by this bank. This simplification works only for one shot
* deallocation like current flash_free_all_banks()
*/
@@ -2873,7 +2873,7 @@ static int sam4_write(struct flash_bank *bank,
struct sam4_bank_private *pPrivate;
uint8_t *pagebuffer;
/* incase we bail further below, set this to null */
/* in case we bail further below, set this to null */
pagebuffer = NULL;
/* ignore dumb requests */

8
src/flash/nor/at91sam7.c
View File

@@ -254,7 +254,7 @@ static void at91sam7_read_clock_info(struct flash_bank *bank)
at91sam7_info->mck_freq = tmp;
}
/* Setup the timimg registers for nvbits or normal flash */
/* Setup the timing registers for nvbits or normal flash */
static void at91sam7_set_flash_mode(struct flash_bank *bank, int mode)
{
uint32_t fmr, fmcn = 0, fws = 0;
@@ -377,7 +377,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
/* re-calculate master clock frequency */
at91sam7_read_clock_info(t_bank);
/* no timming */
/* no timing */
at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
/* check protect state */
@@ -415,7 +415,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
/* calculate master clock frequency */
at91sam7_read_clock_info(t_bank);
/* no timming */
/* no timing */
at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
/* check protect state */
@@ -623,7 +623,7 @@ static int at91sam7_read_part_info(struct flash_bank *bank)
/* calculate master clock frequency */
at91sam7_read_clock_info(t_bank);
/* no timming */
/* no timing */
at91sam7_set_flash_mode(t_bank, FMR_TIMING_NONE);
/* check protect state */

6
src/flash/nor/at91samd.c
View File

@@ -41,7 +41,7 @@
#define SAMD_NVMCTRL_CTRLA 0x00 /* NVM control A register */
#define SAMD_NVMCTRL_CTRLB 0x04 /* NVM control B register */
#define SAMD_NVMCTRL_PARAM 0x08 /* NVM parameters register */
#define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interupt Flag Status & Clear */
#define SAMD_NVMCTRL_INTFLAG 0x18 /* NVM Interrupt Flag Status & Clear */
#define SAMD_NVMCTRL_STATUS 0x18 /* NVM status register */
#define SAMD_NVMCTRL_ADDR 0x1C /* NVM address register */
#define SAMD_NVMCTRL_LOCK 0x20 /* NVM Lock section register */
@@ -52,8 +52,8 @@
/* NVMCTRL commands. See Table 20-4 in 42129F–SAM–10/2013 */
#define SAMD_NVM_CMD_ER 0x02 /* Erase Row */
#define SAMD_NVM_CMD_WP 0x04 /* Write Page */
#define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxilary Row */
#define SAMD_NVM_CMD_WAP 0x06 /* Write Auxilary Page */
#define SAMD_NVM_CMD_EAR 0x05 /* Erase Auxiliary Row */
#define SAMD_NVM_CMD_WAP 0x06 /* Write Auxiliary Page */
#define SAMD_NVM_CMD_LR 0x40 /* Lock Region */
#define SAMD_NVM_CMD_UR 0x41 /* Unlock Region */
#define SAMD_NVM_CMD_SPRM 0x42 /* Set Power Reduction Mode */

6
src/flash/nor/atsame5.c
View File

@@ -31,10 +31,10 @@
#include <target/cortex_m.h>
/* A note to prefixing.
* Definitions and functions ingerited from at91samd.c without
* any change retained the original prefix samd_ so they eventualy
* Definitions and functions inherited from at91samd.c without
* any change retained the original prefix samd_ so they eventually
* may go to samd_common.h and .c
* As currently there are olny 3 short functions identical with
* As currently there are only 3 short functions identical with
* the original source, no common file was created. */
#define SAME5_PAGES_PER_BLOCK 16

2
src/flash/nor/atsamv.c
View File

@@ -25,7 +25,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
/* Some of the the lower level code was based on code supplied by
/* Some of the lower level code was based on code supplied by
* ATMEL under this copyright. */
/* BEGIN ATMEL COPYRIGHT */

18
src/flash/nor/cfi.c
View File

@@ -1178,7 +1178,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
* r6: error test pattern
*/
/* see contib/loaders/flash/armv4_5_cfi_intel_32.s for src */
/* see contrib/loaders/flash/armv4_5_cfi_intel_32.s for src */
static const uint32_t word_32_code[] = {
0xe4904004, /* loop: ldr r4, [r0], #4 */
0xe5813000, /* str r3, [r1] */
@@ -1196,7 +1196,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
0xeafffffe /* done: b -2 */
};
/* see contib/loaders/flash/armv4_5_cfi_intel_16.s for src */
/* see contrib/loaders/flash/armv4_5_cfi_intel_16.s for src */
static const uint32_t word_16_code[] = {
0xe0d040b2, /* loop: ldrh r4, [r0], #2 */
0xe1c130b0, /* strh r3, [r1] */
@@ -1214,7 +1214,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
0xeafffffe /* done: b -2 */
};
/* see contib/loaders/flash/armv4_5_cfi_intel_8.s for src */
/* see contrib/loaders/flash/armv4_5_cfi_intel_8.s for src */
static const uint32_t word_8_code[] = {
0xe4d04001, /* loop: ldrb r4, [r0], #1 */
0xe5c13000, /* strb r3, [r1] */
@@ -1249,7 +1249,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
cfi_intel_clear_status_register(bank);
/* If we are setting up the write_algorith, we need target_code_src
/* If we are setting up the write_algorithm, we need target_code_src
* if not we only need target_code_size. */
/* However, we don't want to create multiple code paths, so we
@@ -1364,7 +1364,7 @@ static int cfi_intel_write_block(struct flash_bank *bank, const uint8_t *buffer,
if (retval != ERROR_OK) {
cfi_intel_clear_status_register(bank);
LOG_ERROR(
"Execution of flash algorythm failed. Can't fall back. Please report.");
"Execution of flash algorithm failed. Can't fall back. Please report.");
retval = ERROR_FLASH_OPERATION_FAILED;
/* retval = ERROR_TARGET_RESOURCE_NOT_AVAILABLE; */
/* FIXME To allow fall back or recovery, we must save the actual status
@@ -1653,7 +1653,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buff
* R10 = unlock2_addr
* R11 = unlock2_cmd */
/* see contib/loaders/flash/armv4_5_cfi_span_32.s for src */
/* see contrib/loaders/flash/armv4_5_cfi_span_32.s for src */
static const uint32_t armv4_5_word_32_code[] = {
/* 00008100 <sp_32_code>: */
0xe4905004, /* ldr r5, [r0], #4 */
@@ -1685,7 +1685,7 @@ static int cfi_spansion_write_block(struct flash_bank *bank, const uint8_t *buff
0xeafffffe /* b 8154 <sp_32_done> */
};
/* see contib/loaders/flash/armv4_5_cfi_span_16.s for src */
/* see contrib/loaders/flash/armv4_5_cfi_span_16.s for src */
static const uint32_t armv4_5_word_16_code[] = {
/* 00008158 <sp_16_code>: */
0xe0d050b2, /* ldrh r5, [r0], #2 */
@@ -2406,7 +2406,7 @@ static int cfi_write(struct flash_bank *bank, const uint8_t *buffer, uint32_t of
break;
}
if (retval == ERROR_OK) {
/* Increment pointers and decrease count on succesful block write */
/* Increment pointers and decrease count on successful block write */
buffer += blk_count;
write_p += blk_count;
count -= blk_count;
@@ -2795,7 +2795,7 @@ int cfi_probe(struct flash_bank *bank)
*for
*all
*CFI
*flashs
*flashes
**/
cfi_read_0002_pri_ext(bank);
break;

2
src/flash/nor/core.h
View File

@@ -248,7 +248,7 @@ int get_flash_bank_by_num(unsigned int num, struct flash_bank **bank);
* @a instance is driver-specific.
* @param name_index The index to the string in args containing the
* bank identifier.
* @param bank On output, contians a pointer to the bank or NULL.
* @param bank On output, contains a pointer to the bank or NULL.
* @returns ERROR_OK on success, or an error indicating the problem.
*/
COMMAND_HELPER(flash_command_get_bank, unsigned name_index,

6
src/flash/nor/driver.h
View File

@@ -120,7 +120,7 @@ struct flash_driver {
*
* @param bank The bank to protect or unprotect.
* @param set If non-zero, enable protection; if 0, disable it.
* @param first The first sector to (un)protect, typicaly 0.
* @param first The first sector to (un)protect, typically 0.
* @param last The last sector to (un)project, typically N-1.
* @returns ERROR_OK if successful; otherwise, an error code.
*/
@@ -202,14 +202,14 @@ struct flash_driver {
int (*info)(struct flash_bank *bank, char *buf, int buf_size);
/**
* A more gentle flavor of filash_driver_s::probe, performing
* A more gentle flavor of flash_driver_s::probe, performing
* setup with less noise. Generally, driver routines should test
* to see if the bank has already been probed; if it has, the
* driver probably should not perform its probe a second time.
*
* This callback is often called from the inside of other
* routines (e.g. GDB flash downloads) to autoprobe the flash as
* it is programing the flash.
* it is programming the flash.
*
* @param bank - the bank to probe
* @returns ERROR_OK if successful; otherwise, an error code.

2
src/flash/nor/dsp5680xx_flash.c
View File

@@ -107,7 +107,7 @@ static int dsp5680xx_flash_protect_check(struct flash_bank *bank)
}
/**
* Protection funcionality is not implemented.
* Protection functionality is not implemented.
* The current implementation applies/removes security on the chip.
* The chip is effectively secured/unsecured after the first reset
* following the execution of this function.

2
src/flash/nor/em357.c
View File

@@ -466,7 +466,7 @@ static int em357_write_block(struct flash_bank *bank, const uint8_t *buffer,
struct armv7m_algorithm armv7m_info;
int retval = ERROR_OK;
/* see contib/loaders/flash/stm32x.s for src, the same is used here except for
/* see contrib/loaders/flash/stm32x.s for src, the same is used here except for
* a modified *_FLASH_BASE */
static const uint8_t em357_flash_write_code[] = {

4
src/flash/nor/fm3.c
View File

@@ -276,7 +276,7 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
if (retval != ERROR_OK)
return retval;
/* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash acccess) */
/* FASZR = 0x01, Enables CPU Programming Mode (16-bit Flash access) */
retval = target_write_u32(target, 0x40000000, 0x0001);
if (retval != ERROR_OK)
return retval;
@@ -336,7 +336,7 @@ static int fm3_erase(struct flash_bank *bank, unsigned int first,
destroy_reg_param(&reg_params[1]);
destroy_reg_param(&reg_params[2]);
/* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash acccess) */
/* FASZR = 0x02, Enables CPU Run Mode (32-bit Flash access) */
retval = target_write_u32(target, 0x40000000, 0x0002);
if (retval != ERROR_OK)
return retval;

8
src/flash/nor/kinetis.c
View File

@@ -79,7 +79,7 @@
*
*/
/* Addressess */
/* Addresses */
#define FCF_ADDRESS 0x00000400
#define FCF_FPROT 0x8
#define FCF_FSEC 0xc
@@ -506,7 +506,7 @@ COMMAND_HANDLER(kinetis_mdm_halt)
}
}
LOG_DEBUG("MDM: halt succeded after %d attempts.", tries);
LOG_DEBUG("MDM: halt succeeded after %d attempts.", tries);
target_poll(target);
/* enable polling in case kinetis_check_flash_security_status disabled it */
@@ -1429,7 +1429,7 @@ static int kinetis_fill_fcf(struct flash_bank *bank, uint8_t *fcf)
bank_iter = k_bank->bank;
if (bank_iter == NULL) {
LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplette", bank_idx);
LOG_WARNING("Missing bank %u configuration, FCF protection flags may be incomplete", bank_idx);
continue;
}
@@ -2850,7 +2850,7 @@ static int kinetis_blank_check(struct flash_bank *bank)
if (result == ERROR_OK) {
bank->sectors[i].is_erased = !(ftfx_fstat & 0x01);
} else {
LOG_DEBUG("Ignoring errored PFlash sector blank-check");
LOG_DEBUG("Ignoring error on PFlash sector blank-check");
kinetis_ftfx_clear_error(bank->target);
bank->sectors[i].is_erased = -1;
}

2
src/flash/nor/kinetis_ke.c
View File

@@ -1229,7 +1229,7 @@ static int kinetis_ke_blank_check(struct flash_bank *bank)
if (result == ERROR_OK) {
bank->sectors[i].is_erased = !(fstat & (FTMRX_FSTAT_MGSTAT0_MASK | FTMRX_FSTAT_MGSTAT1_MASK));
} else {
LOG_DEBUG("Ignoring errored PFlash sector blank-check");
LOG_DEBUG("Ignoring error on PFlash sector blank-check");
bank->sectors[i].is_erased = -1;
}
}

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