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tcl: [3/3] prepare for jimtcl 0.81 'expr' syntax change

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Jimtcl commit 1843b79a03dd ("expr: TIP 526, only support a single
arg") drops the support for multi-argument syntax for the TCL
command 'expr'.

Fix manually the remaining lines that don't match simple patterns
and would require dedicated boring scripting.
Remove the 'expr' command where appropriate.

Change-Id: Ia75210c8447f88d38515addab4a836af9103096d
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: http://openocd.zylin.com/6161
Tested-by: jenkins
Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
Antonio Borneo
2021-04-10 18:28:52 +02:00
parent f855fdcf0d
commit 64d89d5ee1
33 changed files with 109 additions and 109 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
tcl/bitsbytes.tcl
View File

@@ -36,7 +36,7 @@ proc create_mask { MSB LSB } {
# Result: 0x02340000
proc extract_bitfield { VALUE MSB LSB } {
return [expr [create_mask $MSB $LSB] & $VALUE]
return [expr {[create_mask $MSB $LSB] & $VALUE}]
}
@@ -47,7 +47,7 @@ proc extract_bitfield { VALUE MSB LSB } {
# Result: 0x00000234
#
proc normalize_bitfield { VALUE MSB LSB } {
return [expr [extract_bitfield $VALUE $MSB $LSB ] >> $LSB]
return [expr {[extract_bitfield $VALUE $MSB $LSB ] >> $LSB}]
}
proc show_normalize_bitfield { VALUE MSB LSB } {

8
tcl/board/at91sam9261-ek.cfg
View File

@@ -29,9 +29,9 @@ proc at91sam9261ek_reset_init { } {
;# set master_pll_div 1
;# set master_pll_mul 13
set val [expr $::AT91_WDT_WDV] ;# Counter Value
set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
set val $::AT91_WDT_WDV ;# Counter Value
set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt
set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt
@@ -42,7 +42,7 @@ proc at91sam9261ek_reset_init { } {
set config(matrix_ebicsa_val) [expr {$::AT91_MATRIX_DBPUC | $::AT91_MATRIX_CS1A_SDRAMC}]
;# SDRAMC_CR - Configuration register
set val [expr $::AT91_SDRAMC_NC_9]
set val $::AT91_SDRAMC_NC_9
set val [expr {$val | $::AT91_SDRAMC_NR_13}]
set val [expr {$val | $::AT91_SDRAMC_NB_4}]
set val [expr {$val | $::AT91_SDRAMC_CAS_3}]

10
tcl/board/at91sam9263-ek.cfg
View File

@@ -24,9 +24,9 @@ proc at91sam9263ek_reset_init { } {
set config(master_pll_div) 14
set config(master_pll_mul) 171
set val [expr $::AT91_WDT_WDV] ;# Counter Value
set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
set val $::AT91_WDT_WDV ;# Counter Value
set val [expr {$val | $::AT91_WDT_WDDIS}] ;# Watchdog Disable
set val [expr {$val | $::AT91_WDT_WDD}] ;# Delta Value
set val [expr {$val | $::AT91_WDT_WDDBGHLT}] ;# Debug Halt
set val [expr {$val | $::AT91_WDT_WDIDLEHLT}] ;# Idle Halt
@@ -36,13 +36,13 @@ proc at91sam9263ek_reset_init { } {
;# EBI_CSA, no pull-ups for D[15:0], CS1 SDRAM, CS3 NAND Flash
set config(matrix_ebicsa_addr) $::AT91_MATRIX_EBI0CSA
set val [expr $::AT91_MATRIX_EBI0_DBPUC]
set val $::AT91_MATRIX_EBI0_DBPUC
set val [expr {$val | $::AT91_MATRIX_EBI0_VDDIOMSEL_3_3V}]
set val [expr {$val | $::AT91_MATRIX_EBI0_CS1A_SDRAMC}]
set config(matrix_ebicsa_val) $val
;# SDRAMC_CR - Configuration register
set val [expr $::AT91_SDRAMC_NC_9]
set val $::AT91_SDRAMC_NC_9
set val [expr {$val | $::AT91_SDRAMC_NR_13}]
set val [expr {$val | $::AT91_SDRAMC_NB_4}]
set val [expr {$val | $::AT91_SDRAMC_CAS_3}]

8
tcl/board/at91sam9g20-ek.cfg
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@@ -77,25 +77,25 @@ proc at91sam9g20_reset_init { } {
# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
mww 0xfffffc20 0x00004001
while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
mww 0xfffffc28 0x202a3f01
while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
# Wait for MCKRDY signal from PMC_SR to assert.
mww 0xfffffc30 0x00000101
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
# Now change PMC_MCKR register to select PLLA.
# Wait for MCKRDY signal from PMC_SR to assert.
mww 0xfffffc30 0x00001302
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
# Processor and master clocks are now operating and stable at maximum frequency possible:
# -> MCLK = 132.096 MHz

2
tcl/board/dm355evm.cfg
View File

@@ -87,7 +87,7 @@ proc dm355evm_init {} {
mmw $addr 0x2000 0
# wait for READY
while { [expr [mrw $addr] & 0x8000] == 0 } { sleep 1 }
while { [expr {[mrw $addr] & 0x8000}] == 0 } { sleep 1 }
# set IO_READY; then LOCK and PWRSAVE; then PWRDN
mmw $addr 0x4000 0

2
tcl/board/embedded-artists_lpc2478-32.cfg
View File

@@ -125,7 +125,7 @@ proc init_board {} {
#
proc enable_pll {} {
# Disconnect PLL in case it is already connected
if {[expr [read_register 0xE01FC080] & 0x03] == 3} {
if {[expr {[read_register 0xE01FC080] & 0x03}] == 3} {
# Disconnect it, but leave it enabled
# (This MUST be done in two steps)
mww 0xE01FC080 0x00000001 ;# PLLCON: disconnect PLL

4
tcl/board/hilscher_nxhx10.cfg
View File

@@ -34,7 +34,7 @@ proc mread32 {addr} {
proc init_clocks { } {
puts "Enabling all clocks "
set accesskey [mread32 0x101c0070]
mww 0x101c0070 [expr $accesskey]
mww 0x101c0070 $accesskey
mww 0x101c0028 0x00007511
}
@@ -42,7 +42,7 @@ proc init_clocks { } {
proc init_sdrambus { } {
puts "Initializing external SDRAM Bus 16 Bit "
set accesskey [mread32 0x101c0070]
mww 0x101c0070 [expr $accesskey]
mww 0x101c0070 $accesskey
mww 0x101c0C40 0x00000050
puts "Configuring SDRAM controller for K4S561632E (32MB) "

8
tcl/board/icnova_imx53_sodimm.cfg
View File

@@ -69,7 +69,7 @@ proc init_l2cc { } {
set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1
arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */
@@ -139,7 +139,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
; # make sure change is effective
while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
@@ -157,7 +157,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
; # Restore the default values in the Gate registers
mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
@@ -243,7 +243,7 @@ proc setup_pll { PLL_ADDR CLK } {
mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
}

16
tcl/board/icnova_sam9g45_sodimm.cfg
View File

@@ -89,27 +89,27 @@ proc at91sam9g45_init { } {
# Wait for MOSCS in PMC_SR to assert indicating oscillator is again stable after change to CKGR_MOR.
mww 0xfffffc20 0x00004001
while { [expr [read_register 0xfffffc68] & 0x01] != 1 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x01}] != 1 } { sleep 1 }
# Set PLLA Register for 792.576 MHz (divider: bypass, multiplier: 43).
# Wait for LOCKA signal in PMC_SR to assert indicating PLLA is stable.
#mww 0xfffffc28 0x202a3f01
mww 0xfffffc28 0x20c73f03
while { [expr [read_register 0xfffffc68] & 0x02] != 2 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x02}] != 2 } { sleep 1 }
# Set master system clock prescaler divide by 6 and processor clock divide by 2 in PMC_MCKR.
# Wait for MCKRDY signal from PMC_SR to assert.
#mww 0xfffffc30 0x00000101
mww 0xfffffc30 0x00001301
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
# Now change PMC_MCKR register to select PLLA.
# Wait for MCKRDY signal from PMC_SR to assert.
mww 0xfffffc30 0x00001302
while { [expr [read_register 0xfffffc68] & 0x08] != 8 } { sleep 1 }
while { [expr {[read_register 0xfffffc68] & 0x08}] != 8 } { sleep 1 }
# Processor and master clocks are now operating and stable at maximum frequency possible:
# -> MCLK = 132.096 MHz
@@ -214,7 +214,7 @@ proc at91sam9g45_init { } {
sleep 1
# 9. Enable DLL Reset (set DLL bit)
set CR [expr [read_register 0xffffe608] | 0x80]
set CR [expr {[read_register 0xffffe608] | 0x80}]
mww 0xffffe608 $CR
# 10. mode register cycle to reset the DLL
@@ -236,7 +236,7 @@ proc at91sam9g45_init { } {
# 12.3 delay 10 cycles
# 13. disable DLL reset (clear DLL bit)
set CR [expr [read_register 0xffffe608] & 0xffffff7f]
set CR [expr {[read_register 0xffffe608] & 0xffffff7f}]
mww 0xffffe608 $CR
# 14. mode register set cycle
@@ -244,7 +244,7 @@ proc at91sam9g45_init { } {
mww 0x70000000 0x1
# 15. program OCD field (set OCD bits)
set CR [expr [read_register 0xffffe608] | 0x7000]
set CR [expr {[read_register 0xffffe608] | 0x7000}]
mww 0xffffe608 $CR
# 16. (EMRS1)
@@ -253,7 +253,7 @@ proc at91sam9g45_init { } {
# 16.1 delay 2 cycles
# 17. disable OCD field (clear OCD bits)
set CR [expr [read_register 0xffffe608] & 0xffff8fff]
set CR [expr {[read_register 0xffffe608] & 0xffff8fff}]
mww 0xffffe608 $CR
# 18. (EMRS1)

8
tcl/board/imx53-m53evk.cfg
View File

@@ -65,7 +65,7 @@ proc init_l2cc { } {
set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1
arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */
@@ -135,7 +135,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
; # make sure change is effective
while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
@@ -153,7 +153,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
; # Restore the default values in the Gate registers
mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
@@ -239,7 +239,7 @@ proc setup_pll { PLL_ADDR CLK } {
mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
}

8
tcl/board/imx53loco.cfg
View File

@@ -70,7 +70,7 @@ proc init_l2cc { } {
set tR [arm mrc 15 0 1 0 1]
; #bic r0, r0, #0x2
; #mcr 15, 0, r0, c1, c0, 1
arm mcr 15 0 1 0 1 [expr $tR & ~(1<<2)]
arm mcr 15 0 1 0 1 [expr {$tR & ~(1 << 2)}]
; #/* reconfigure L2 cache aux control reg */
; #mov r0, #0xC0 /* tag RAM */
@@ -140,7 +140,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CBCMR}] 0x00016154
; # change uart clk parent to pll2
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000]
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCMR1}]] & 0xfcffffff | 0x01000000}]
; # make sure change is effective
while {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CDHIPR}]] != 0} { sleep 1 }
@@ -158,7 +158,7 @@ proc init_clock { } {
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CCSR}] 0x0
; # make uart div=6
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr [mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a]
mww [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}] [expr {[mrw [expr {$CCM_BASE_ADDR + $CLKCTL_CSCDR1}]] & 0xffffffc0 | 0x0a}]
; # Restore the default values in the Gate registers
mww [expr {$CCM_BASE_ADDR + 0x68}] 0xFFFFFFFF
@@ -244,7 +244,7 @@ proc setup_pll { PLL_ADDR CLK } {
mww [expr {$PLL_ADDR + $PLL_DP_HFS_MFN}] $DP_MFN
mww [expr {$PLL_ADDR + $PLL_DP_CTL}] 0x00001232
while {[expr [mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1] == 0} { sleep 1 }
while {[expr {[mrw [expr {$PLL_ADDR + $PLL_DP_CTL}]] & 0x1}] == 0} { sleep 1 }
}

2
tcl/board/nxp_imx7sabre.cfg
View File

@@ -27,7 +27,7 @@ proc imx7_uart_dbgconf { } {
}
proc check_bits_set_32 { addr mask } {
while { [expr [mrw $addr] & $mask == 0] } { }
while { [expr {[mrw $addr] & $mask} == 0] } { }
}
proc apply_dcd { } {

2
tcl/chip/atmel/at91/at91_pmc.cfg
View File

@@ -87,7 +87,7 @@ set AT91_PMC_USBS_PLLA [expr {0 << 0}]
set AT91_PMC_USBS_UPLL [expr {1 << 0}]
set AT91_PMC_OHCIUSBDIV [expr {0xF << 8}] ;# Divider for USB OHCI Clock
;# set AT91_PMC_PCKR(n) [expr ($AT91_PMC + 0x40 + ((n) * 4))] ;# Programmable Clock 0-N Registers
;# set AT91_PMC_PCKR(n) [expr {$AT91_PMC + 0x40 + ((n) * 4)}] ;# Programmable Clock 0-N Registers
set AT91_PMC_CSSMCK [expr {0x1 << 8}] ;# CSS or Master Clock Selection
set AT91_PMC_CSSMCK_CSS [expr {0 << 8}]
set AT91_PMC_CSSMCK_MCK [expr {1 << 8}]

18
tcl/chip/atmel/at91/at91sam9_init.cfg
View File

@@ -11,7 +11,7 @@ proc at91sam9_reset_start { } {
jtag_rclk 8
halt
wait_halt 10000
set rstc_mr_val [expr $::AT91_RSTC_KEY]
set rstc_mr_val $::AT91_RSTC_KEY
set rstc_mr_val [expr {$rstc_mr_val | (5 << 8)}]
set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
mww $::AT91_RSTC_MR $rstc_mr_val ;# RSTC_MR : enable user reset.
@@ -24,25 +24,25 @@ proc at91sam9_reset_init { config } {
set ckgr_mor [expr {$::AT91_PMC_MOSCEN | (255 << 8)}]
mww $::AT91_CKGR_MOR $ckgr_mor ;# CKGR_MOR - enable main osc.
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS] != $::AT91_PMC_MOSCS } { sleep 1 }
while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MOSCS}] != $::AT91_PMC_MOSCS } { sleep 1 }
set pllar_val [expr $::AT91_PMC_PLLA_WR_ERRATA] ;# Bit 29 must be 1 when prog
set pllar_val $::AT91_PMC_PLLA_WR_ERRATA ;# Bit 29 must be 1 when prog
set pllar_val [expr {$pllar_val | $::AT91_PMC_OUT}]
set pllar_val [expr {$pllar_val | $::AT91_PMC_PLLCOUNT}]
set pllar_val [expr ($pllar_val | ($config(master_pll_mul) - 1) << 16)]
set pllar_val [expr ($pllar_val | $config(master_pll_div))]
set pllar_val [expr {$pllar_val | ($config(master_pll_mul) - 1) << 16}]
set pllar_val [expr {$pllar_val | $config(master_pll_div)}]
mww $::AT91_CKGR_PLLAR $pllar_val ;# CKGR_PLLA - (18.432MHz/13)*141 = 199.9 MHz
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA] != $::AT91_PMC_LOCKA } { sleep 1 }
while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_LOCKA}] != $::AT91_PMC_LOCKA } { sleep 1 }
;# PCK/2 = MCK Master Clock from PLLA
set mckr_val [expr $::AT91_PMC_CSS_PLLA]
set mckr_val $::AT91_PMC_CSS_PLLA
set mckr_val [expr {$mckr_val | $::AT91_PMC_PRES_1}]
set mckr_val [expr {$mckr_val | $::AT91SAM9_PMC_MDIV_2}]
set mckr_val [expr {$mckr_val | $::AT91_PMC_PDIV_1}]
mww $::AT91_PMC_MCKR $mckr_val ;# PMC_MCKR (MCLK: 0x102 - (CLK/2)MHZ, 0x202 - (CLK/3)MHz)
while { [expr [mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY] != $::AT91_PMC_MCKRDY } { sleep 1 }
while { [expr {[mrw $::AT91_PMC_SR] & $::AT91_PMC_MCKRDY}] != $::AT91_PMC_MCKRDY } { sleep 1 }
## switch JTAG clock to highspeed clock
jtag_rclk 0
@@ -50,7 +50,7 @@ proc at91sam9_reset_init { config } {
arm7_9 dcc_downloads enable ;# Enable faster DCC downloads
arm7_9 fast_memory_access enable
set rstc_mr_val [expr ($::AT91_RSTC_KEY)]
set rstc_mr_val $::AT91_RSTC_KEY
set rstc_mr_val [expr {$rstc_mr_val | $::AT91_RSTC_URSTEN}]
mww $::AT91_RSTC_MR $rstc_mr_val ;# user reset enable

2
tcl/chip/atmel/at91/usarts.tcl
View File

@@ -63,7 +63,7 @@ proc show_mmr_USx_MR_helper { NAME ADDR VAL } {
}
echo [format "\tParity: %s " $s]
set x [expr 5 + [show_normalize_bitfield $VAL 7 6]]
set x [expr {5 + [show_normalize_bitfield $VAL 7 6]}]
echo [format "\tDatabits: %d" $x]
set x [show_normalize_bitfield $VAL 13 12]

2
tcl/chip/st/spear/quirk_no_srst.tcl
View File

@@ -24,7 +24,7 @@ set sp_reset_mode ""
proc sp_is_halted {} {
global sp_target_name
return [expr [string compare [$sp_target_name curstate] "halted" ] == 0]
return [expr {[string compare [$sp_target_name curstate] "halted" ] == 0}]
}
# wait for reset button to be pressed, causing CPU to get halted

8
tcl/chip/st/spear/spear3xx.tcl
View File

@@ -19,7 +19,7 @@ proc sp3xx_clock_default {} {
mww 0xfca00014 0x0ffffff8 ;# set pll timeout to minimum (100us ?!?)
# DDRCORE disable to change frequency
set val [expr ([mrw 0xfca8002c] & ~0x20000000) | 0x40000000]
set val [expr {([mrw 0xfca8002c] & ~0x20000000) | 0x40000000}]
mww 0xfca8002c $val
mww 0xfca8002c $val ;# Yes, write twice!
@@ -29,7 +29,7 @@ proc sp3xx_clock_default {} {
mww 0xfca80008 0x00001c0e ;# enable
mww 0xfca80008 0x00001c06 ;# strobe
mww 0xfca80008 0x00001c0e
while { [expr [mrw 0xfca80008] & 0x01] == 0x00 } { sleep 1 }
while { [expr {[mrw 0xfca80008] & 0x01}] == 0x00 } { sleep 1 }
# programming PLL2
mww 0xfca80018 0xa600010c ;# M=166, P=1, N=12
@@ -37,13 +37,13 @@ proc sp3xx_clock_default {} {
mww 0xfca80014 0x00001c0e ;# enable
mww 0xfca80014 0x00001c06 ;# strobe
mww 0xfca80014 0x00001c0e
while { [expr [mrw 0xfca80014] & 0x01] == 0x00 } { sleep 1 }
while { [expr {[mrw 0xfca80014] & 0x01}] == 0x00 } { sleep 1 }
mww 0xfca80028 0x00000082 ;# enable plltimeen
mww 0xfca80024 0x00000511 ;# set hclkdiv="/2" & pclkdiv="/2"
mww 0xfca00000 0x00000004 ;# setting SYSCTL to NORMAL mode
while { [expr [mrw 0xfca00000] & 0x20] != 0x20 } { sleep 1 }
while { [expr {[mrw 0xfca00000] & 0x20}] != 0x20 } { sleep 1 }
# Select source of DDR clock
#mmw 0xfca80020 0x10000000 0x70000000 ;# PLL1

2
tcl/fpga/xilinx-xadc.cfg
View File

@@ -16,7 +16,7 @@ proc xadc_cmd {cmd addr data} {
READ 0x01
WRITE 0x02
}
return [expr ($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)]
return [expr {($cmds($cmd) << 26) | ($addr << 16) | ($data << 0)}]
}
# XADC register addresses

2
tcl/memory.tcl
View File

@@ -58,7 +58,7 @@ set ACCESS_WIDTH_ANY [expr {$ACCESS_WIDTH_8 + $ACCESS_WIDTH_16 + $ACCESS_WIDTH_
set UNKNOWN(0,ACCESS_WIDTH) $ACCESS_WIDTH_NONE
proc iswithin { ADDRESS BASE LEN } {
return [expr ((($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0))]
return [expr {(($ADDRESS - $BASE) >= 0) && (($BASE + $LEN - $ADDRESS) > 0)}]
}
proc address_info { ADDRESS } {

4
tcl/mmr_helpers.tcl
View File

@@ -2,7 +2,7 @@
proc proc_exists { NAME } {
set n [info commands $NAME]
set l [string length $n]
return [expr $l != 0]
return [expr {$l != 0}]
}
# Give: REGISTER name - must be a global variable.
@@ -52,7 +52,7 @@ proc show_mmr32_bits { NAMES VAL } {
echo -n " "
for { set y 7 } { $y >= 0 } { incr y -1 } {
echo -n [format " %d%*s | " [expr !!($VAL & (1 << ($x + $y)))] [expr {$w -1}] ""]
echo -n [format " %d%*s | " [expr {!!($VAL & (1 << ($x + $y)))}] [expr {$w -1}] ""]
}
echo ""
}

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