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Add new target type: OpenRISC

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Add support for OpenRISC target. This implementation
supports the adv_debug_sys debug unit core. The mohor
dbg_if is not supported. Support for mohor TAP core
and Altera Virtual JTAG core are also provided.

Change-Id: I3b1cfab1bbb28e497c4fca6ed1bd3a4362609b72
Signed-off-by: Franck Jullien <franck.jullien@gmail.com>
Reviewed-on: http://openocd.zylin.com/1547
Tested-by: jenkins
Reviewed-by: Andreas Fritiofson <andreas.fritiofson@gmail.com>
This commit is contained in:
Franck Jullien
2013-08-08 23:45:47 +02:00
committed by Spencer Oliver
parent d19fafc8bd
commit 4e79b48e2c
16 changed files with 3220 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
configure.ac
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@@ -1261,6 +1261,7 @@ AC_CONFIG_FILES([
src/jtag/hla/Makefile
src/jtag/aice/Makefile
src/transport/Makefile
src/target/openrisc/Makefile
src/xsvf/Makefile
src/svf/Makefile
src/target/Makefile

56
doc/openocd.texi
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@@ -4179,6 +4179,17 @@ There are several variants defined:
@code{pxa26x} ... instruction register length is 5 bits
@item @code{pxa3xx} ... instruction register length is 11 bits
@end itemize
@item @code{openrisc} -- this is an OpenRISC 1000 core.
The current implementation supports two JTAG TAP cores:
@itemize @minus
@item @code{OpenCores TAP} (See: @emph{http://opencores.org/project,jtag})
@item @code{Altera Virtual JTAG TAP} (See: @emph{http://www.altera.com/literature/ug/ug_virtualjtag.pdf})
@end itemize
And two debug interfaces cores:
@itemize @minus
@item @code{Advanced debug interface} (See: @emph{http://opencores.org/project,adv_debug_sys})
@item @code{SoC Debug Interface} (See: @emph{http://opencores.org/project,dbg_interface})
@end itemize
@end itemize
@end deffn
@@ -7493,6 +7504,51 @@ the peripherals.
@xref{targetevents,,Target Events}.
@end deffn
@section OpenRISC Architecture
The OpenRISC CPU is a soft core. It is used in a programmable SoC which can be
configured with any of the TAP / Debug Unit available.
@subsection TAP and Debug Unit selection commands
@deffn Command {tap_select} (@option{vjtag}|@option{mohor})
Select between the Altera Virtual JTAG and Mohor TAP.
@end deffn
@deffn Command {du_select} (@option{adv}|@option{mohor}) [option]
Select between the Advanced Debug Interface and the classic one.
An option can be passed as a second argument to the debug unit.
When using the Advanced Debug Interface, option = 1 means the RTL core is
configured with ADBG_USE_HISPEED = 1. This configuration skips status checking
between bytes while doing read or write bursts.
@end deffn
@subsection Registers commands
@deffn Command {addreg} [name] [address] [feature] [reg_group]
Add a new register in the cpu register list. This register will be
included in the generated target descriptor file.
@strong{[feature]} must be "org.gnu.gdb.or1k.group[0..10]".
@strong{[reg_group]} can be anything. The default register list defines "system",
"dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic"
and "timer" groups.
@emph{example:}
@example
addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
@end example
@end deffn
@deffn Command {readgroup} (@option{group})
Display all registers in @emph{group}.
@emph{group} can be "system",
"dmmu", "immu", "dcache", "icache", "mac", "debug", "perf", "power", "pic",
"timer" or any new group created with addreg command.
@end deffn
@anchor{softwaredebugmessagesandtracing}
@section Software Debug Messages and Tracing
@cindex Linux-ARM DCC support

21
src/helper/binarybuffer.c
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@@ -397,3 +397,24 @@ int hexify(char *hex, const char *bin, int count, int out_maxlen)
return cmd_len;
}
void buffer_shr(void *_buf, unsigned buf_len, unsigned count)
{
unsigned i;
unsigned char *buf = _buf;
unsigned bytes_to_remove;
unsigned shift;
bytes_to_remove = count / 8;
shift = count - (bytes_to_remove * 8);
for (i = 0; i < (buf_len - 1); i++)
buf[i] = (buf[i] >> shift) | ((buf[i+1] << (8 - shift)) & 0xff);
buf[(buf_len - 1)] = buf[(buf_len - 1)] >> shift;
if (bytes_to_remove) {
memmove(buf, &buf[bytes_to_remove], buf_len - bytes_to_remove);
memset(&buf[buf_len - bytes_to_remove], 0, bytes_to_remove);
}
}

1
src/helper/binarybuffer.h
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@@ -238,5 +238,6 @@ void bit_copy_discard(struct bit_copy_queue *q);
* used in ti-icdi driver and gdb server */
int unhexify(char *bin, const char *hex, int count);
int hexify(char *hex, const char *bin, int count, int out_maxlen);
void buffer_shr(void *_buf, unsigned buf_len, unsigned count);
#endif /* BINARYBUFFER_H */

3
src/target/Makefile.am
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@@ -6,6 +6,9 @@ else
OOCD_TRACE_FILES =
endif
SUBDIRS = openrisc
libtarget_la_LIBADD = $(top_builddir)/src/target/openrisc/libopenrisc.la
BIN2C = $(top_builddir)/src/helper/bin2char$(EXEEXT_FOR_BUILD)
DEBUG_HANDLER = $(srcdir)/xscale/debug_handler.bin

15
src/target/openrisc/Makefile.am Normal file
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@@ -0,0 +1,15 @@
include $(top_srcdir)/common.mk
noinst_LTLIBRARIES = libopenrisc.la
libopenrisc_la_SOURCES = $(OPENRISC_SRC)
OPENRISC_SRC = \
or1k.c \
or1k_du_adv.c \
or1k_tap_mohor.c \
or1k_tap_vjtag.c
noinst_HEADERS = \
or1k.h \
or1k_du.h \
or1k_tap.h

1472
src/target/openrisc/or1k.c Normal file
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159
src/target/openrisc/or1k.h Normal file
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@@ -0,0 +1,159 @@
/***************************************************************************
* Copyright (C) 2011 by Julius Baxter *
* julius@opencores.org *
* *
* Copyright (C) 2013 by Marek Czerski *
* ma.czerski@gmail.com *
* *
* Copyright (C) 2013 by Franck Jullien *
* elec4fun@gmail.com *
* *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef OR1K_H
#define OR1K_H
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <target/target.h>
/* SPR groups start address */
#define GROUP0 (0 << 11)
#define GROUP1 (1 << 11)
#define GROUP2 (2 << 11)
#define GROUP3 (3 << 11)
#define GROUP4 (4 << 11)
#define GROUP5 (5 << 11)
#define GROUP6 (6 << 11)
#define GROUP7 (7 << 11)
#define GROUP8 (8 << 11)
#define GROUP9 (9 << 11)
#define GROUP10 (10 << 11)
/* OR1K registers */
enum or1k_reg_nums {
OR1K_REG_R0 = 0,
OR1K_REG_R1,
OR1K_REG_R2,
OR1K_REG_R3,
OR1K_REG_R4,
OR1K_REG_R5,
OR1K_REG_R6,
OR1K_REG_R7,
OR1K_REG_R8,
OR1K_REG_R9,
OR1K_REG_R10,
OR1K_REG_R11,
OR1K_REG_R12,
OR1K_REG_R13,
OR1K_REG_R14,
OR1K_REG_R15,
OR1K_REG_R16,
OR1K_REG_R17,
OR1K_REG_R18,
OR1K_REG_R19,
OR1K_REG_R20,
OR1K_REG_R21,
OR1K_REG_R22,
OR1K_REG_R23,
OR1K_REG_R24,
OR1K_REG_R25,
OR1K_REG_R26,
OR1K_REG_R27,
OR1K_REG_R28,
OR1K_REG_R29,
OR1K_REG_R30,
OR1K_REG_R31,
OR1K_REG_PPC,
OR1K_REG_NPC,
OR1K_REG_SR,
OR1KNUMCOREREGS
};
struct or1k_jtag {
struct jtag_tap *tap;
int or1k_jtag_inited;
int or1k_jtag_module_selected;
uint8_t *current_reg_idx;
struct or1k_tap_ip *tap_ip;
struct or1k_du *du_core;
};
struct or1k_common {
struct or1k_jtag jtag;
struct reg_cache *core_cache;
uint32_t core_regs[OR1KNUMCOREREGS];
int nb_regs;
struct or1k_core_reg *arch_info;
};
static inline struct or1k_common *
target_to_or1k(struct target *target)
{
return (struct or1k_common *)target->arch_info;
}
struct or1k_core_reg {
const char *name;
uint32_t list_num; /* Index in register cache */
uint32_t spr_num; /* Number in architecture's SPR space */
struct target *target;
struct or1k_common *or1k_common;
const char *feature; /* feature name in XML tdesc file */
const char *group; /* register group in XML tdesc file */
};
struct or1k_core_reg_init {
const char *name;
uint32_t spr_num; /* Number in architecture's SPR space */
const char *feature; /* feature name in XML tdesc file */
const char *group; /* register group in XML tdesc file */
};
/* ORBIS32 Trap instruction */
#define OR1K_TRAP_INSTR 0x21000001
enum or1k_debug_reg_nums {
OR1K_DEBUG_REG_DMR1 = 0,
OR1K_DEBUG_REG_DMR2,
OR1K_DEBUG_REG_DCWR0,
OR1K_DEBUG_REG_DCWR1,
OR1K_DEBUG_REG_DSR,
OR1K_DEBUG_REG_DRR,
OR1K_DEBUG_REG_NUM
};
#define NO_SINGLE_STEP 0
#define SINGLE_STEP 1
/* OR1K Debug registers and bits needed for resuming */
#define OR1K_DEBUG_REG_BASE GROUP6 /* Debug registers Base address */
#define OR1K_DMR1_CPU_REG_ADD (OR1K_DEBUG_REG_BASE + 16) /* Debug Mode Register 1 0x3010 */
#define OR1K_DMR1_ST 0x00400000 /* Single-step trace */
#define OR1K_DMR1_BT 0x00800000 /* Branch trace */
#define OR1K_DMR2_WGB 0x003ff000 /* Watchpoints generating breakpoint */
#define OR1K_DSR_TE 0x00002000 /* Trap exception */
/* OR1K Instruction cache registers needed for invalidating instruction
* memory during adding and removing breakpoints.
*/
#define OR1K_ICBIR_CPU_REG_ADD ((4 << 11) + 2) /* IC Block Invalidate Register 0x2002 */
#endif

77
src/target/openrisc/or1k_du.h Normal file
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@@ -0,0 +1,77 @@
/***************************************************************************
* Copyright (C) 2013 Franck Jullien *
* elec4fun@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef OR1K_DU
#define OR1K_DU
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#define CPU_STALL 0
#define CPU_UNSTALL 1
#define CPU_RESET 0
#define CPU_NOT_RESET 1
int or1k_du_adv_register(void);
/* Linear list over all available or1k debug unit */
extern struct list_head du_list;
struct or1k_du {
const char *name;
struct list_head list;
int options;
int (*or1k_jtag_init)(struct or1k_jtag *jtag_info);
int (*or1k_is_cpu_running)(struct or1k_jtag *jtag_info, int *running);
int (*or1k_cpu_stall)(struct or1k_jtag *jtag_info, int action);
int (*or1k_cpu_reset)(struct or1k_jtag *jtag_info, int action);
int (*or1k_jtag_read_cpu)(struct or1k_jtag *jtag_info,
uint32_t addr, int count, uint32_t *value);
int (*or1k_jtag_write_cpu)(struct or1k_jtag *jtag_info,
uint32_t addr, int count, const uint32_t *value);
int (*or1k_jtag_read_memory)(struct or1k_jtag *jtag_info, uint32_t addr, uint32_t size,
int count, uint8_t *buffer);
int (*or1k_jtag_write_memory)(struct or1k_jtag *jtag_info, uint32_t addr, uint32_t size,
int count, const uint8_t *buffer);
};
static inline struct or1k_du *or1k_jtag_to_du(struct or1k_jtag *jtag_info)
{
return (struct or1k_du *)jtag_info->du_core;
}
static inline struct or1k_du *or1k_to_du(struct or1k_common *or1k)
{
struct or1k_jtag *jtag = &or1k->jtag;
return (struct or1k_du *)jtag->du_core;
}
#endif

900
src/target/openrisc/or1k_du_adv.c Normal file
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43
src/target/openrisc/or1k_tap.h Normal file
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@@ -0,0 +1,43 @@
/***************************************************************************
* Copyright (C) 2012 by Franck Jullien *
* elec4fun@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef _OR1K_TAP_H_
#define _OR1K_TAP_H_
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <helper/list.h>
#include "or1k.h"
int or1k_tap_vjtag_register(void);
int or1k_tap_mohor_register(void);
/* Linear list over all available or1k taps */
extern struct list_head tap_list;
struct or1k_tap_ip {
struct list_head list;
int (*init)(struct or1k_jtag *jtag_info);
const char *name;
};
#endif

65
src/target/openrisc/or1k_tap_mohor.c Normal file
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@@ -0,0 +1,65 @@
/***************************************************************************
* Copyright (C) 2013 by Franck Jullien *
* elec4fun@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "or1k_tap.h"
#include "or1k.h"
#include <jtag/jtag.h>
#define OR1K_TAP_INST_DEBUG 0x8
static int or1k_tap_mohor_init(struct or1k_jtag *jtag_info)
{
LOG_DEBUG("Initialising OpenCores JTAG TAP");
/* Put TAP into state where it can talk to the debug interface
* by shifting in correct value to IR.
*/
/* Ensure TAP is reset - maybe not necessary*/
jtag_add_tlr();
struct jtag_tap *tap = jtag_info->tap;
struct scan_field field;
uint8_t ir_value = OR1K_TAP_INST_DEBUG;
field.num_bits = tap->ir_length;
field.out_value = &ir_value;
field.in_value = NULL;
jtag_add_ir_scan(tap, &field, TAP_IDLE);
return jtag_execute_queue();
}
static struct or1k_tap_ip mohor_tap = {
.name = "mohor",
.init = or1k_tap_mohor_init,
};
int or1k_tap_mohor_register(void)
{
list_add_tail(&mohor_tap.list, &tap_list);
return 0;
}

310
src/target/openrisc/or1k_tap_vjtag.c Normal file
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@@ -0,0 +1,310 @@
/***************************************************************************
* Copyright (C) 2013 by Franck Jullien *
* elec4fun@gmail.com *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include "or1k_tap.h"
#include "or1k.h"
#include <jtag/jtag.h>
/* Contains constants relevant to the Altera Virtual JTAG
* device, which are not included in the BSDL.
* As of this writing, these are constant across every
* device which supports virtual JTAG.
*/
/* These are commands for the FPGA's IR. */
#define ALTERA_CYCLONE_CMD_USER1 0x0E
#define ALTERA_CYCLONE_CMD_USER0 0x0C
/* These defines are for the virtual IR (not the FPGA's)
* The virtual TAP was defined in hardware to match the OpenCores native
* TAP in both IR size and DEBUG command.
*/
#define ALT_VJTAG_IR_SIZE 4
#define ALT_VJTAG_CMD_DEBUG 0x8
/* SLD node ID. */
#define JTAG_TO_AVALON_NODE_ID 0x84
#define VJTAG_NODE_ID 0x08
#define SIGNAL_TAP_NODE_ID 0x00
#define SERIAL_FLASH_LOADER_NODE_ID 0x04
#define VER(x) ((x >> 27) & 0x1f)
#define NB_NODES(x) ((x >> 19) & 0xff)
#define ID(x) ((x >> 19) & 0xff)
#define MANUF(x) ((x >> 8) & 0x7ff)
#define M_WIDTH(x) ((x >> 0) & 0xff)
#define INST_ID(x) ((x >> 0) & 0xff)
/* tap instructions - Mohor JTAG TAP */
#define OR1K_TAP_INST_IDCODE 0x2
#define OR1K_TAP_INST_DEBUG 0x8
static char *id_to_string(unsigned char id)
{
switch (id) {
case VJTAG_NODE_ID:
return "Virtual JTAG";
case JTAG_TO_AVALON_NODE_ID:
return "JTAG to avalon bridge";
case SIGNAL_TAP_NODE_ID:
return "Signal TAP";
case SERIAL_FLASH_LOADER_NODE_ID:
return "Serial Flash Loader";
}
return "unknown";
}
static unsigned char guess_addr_width(unsigned char number_of_nodes)
{
unsigned char width = 0;
while (number_of_nodes) {
number_of_nodes >>= 1;
width++;
}
return width;
}
static int or1k_tap_vjtag_init(struct or1k_jtag *jtag_info)
{
LOG_DEBUG("Initialising Altera Virtual JTAG TAP");
/* Put TAP into state where it can talk to the debug interface
* by shifting in correct value to IR.
*/
/* Ensure TAP is reset - maybe not necessary*/
jtag_add_tlr();
/* You can use a custom JTAG controller to discover transactions
* necessary to enumerate all Virtual JTAG megafunction instances
* from your design atruntime. All SLD nodes and the virtual JTAG
* registers that they contain are targeted by two Instruction Register
* values, USER0 and USER1.
*
* The USER1 instruction targets the virtual IR of either the sld_hub
* or a SLD node. That is,when the USER1 instruction is issued to
* the device, the subsequent DR scans target a specific virtual
* IR chain based on an address field contained within the DR scan.
* The table below shows how the virtual IR, the DR target of the
* USER1 instruction is interpreted.
*
* The VIR_VALUE in the table below is the virtual IR value for the
* target SLD node. The width of this field is m bits in length,
* where m is the length of the largest VIR for all of the SLD nodes
* in the design. All SLD nodes with VIR lengths of fewer than m
* bits must pad VIR_VALUE with zeros up to a length of m.
*
* -------------------------------+-------------------------------
* m + n - 1 m | m -1 0
* -------------------------------+-------------------------------
* ADDR [(n – 1)..0] | VIR_VALUE [(m – 1)..0]
* -------------------------------+-------------------------------
*
* The ADDR bits act as address values to signal the active SLD node
* that the virtual IR shift targets. ADDR is n bits in length, where
* n bits must be long enough to encode all SLD nodes within the design,
* as shown below.
*
* n = CEIL(log2(Number of SLD_nodes +1))
*
* The SLD hub is always 0 in the address map.
*
* Discovery and enumeration of the SLD instances within a design
* requires interrogation of the sld_hub to determine the dimensions
* of the USER1 DR (m and n) and associating each SLD instance, specifically
* the Virtual JTAG megafunction instances, with an address value
* contained within the ADDR bits of the USER1 DR.
*
* The SLD hub contains the HUB IP Configuration Register and SLD_NODE_INFO
* register for each SLD node in the design. The HUB IP configuration register provides
* information needed to determine the dimensions of the USER1 DR chain. The
* SLD_NODE_INFO register is used to determine the address mapping for Virtual
* JTAG instance in your design. This register set is shifted out by issuing the
* HUB_INFO instruction. Both the ADDR bits for the SLD hub and the HUB_INFO
* instruction is 0 × 0.
* Because m and n are unknown at this point, the DR register
* (ADDR bits + VIR_VALUE) must be filled with zeros. Shifting a sequence of 64 zeroes
* into the USER1 DR is sufficient to cover the most conservative case for m and n.
*/
uint8_t t[4];
struct scan_field field;
struct jtag_tap *tap = jtag_info->tap;
/* Select VIR */
buf_set_u32(t, 0, tap->ir_length, ALTERA_CYCLONE_CMD_USER1);
field.num_bits = tap->ir_length;
field.out_value = t;
field.in_value = NULL;
jtag_add_ir_scan(tap, &field, TAP_IDLE);
/* Select the SLD Hub */
field.num_bits = 64;
field.out_value = NULL;
field.in_value = NULL;
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
/* HUB IP Configuration Register
*
* When the USER1 and HUB_INFO instruction sequence is issued, the
* USER0 instruction must be applied to enable the target register
* of the HUB_INFO instruction. The HUB IP configuration register
* is shifted out using eight four-bit nibble scans of the DR register.
* Each four-bit scan must pass through the UPDATE_DR state before
* the next four-bit scan. The 8 scans are assembled into a 32-bit
* value with the definitions shown in the table below.
*
* --------------------------------------------------------------------------------
* NIBBLE7 | NIBBLE6 | NIBBLE5 | NIBBLE4 | NIBBLE3 | NIBBLE2 | NIBBLE1 | NIBBLE0
* ----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+-----
* | | | | | | | | | | | | | | |
* ----+----+----+----+----+----+----+----+----+----+----+----+----+----+----+-----
* HUB IP version| N | ALTERA_MFG_ID (0x06E) | SUM (m, n)
* --------------+-------------------+------------------------+--------------------
*/
/* Select VDR */
buf_set_u32(t, 0, tap->ir_length, ALTERA_CYCLONE_CMD_USER0);
field.num_bits = tap->ir_length;
field.out_value = t;
field.in_value = NULL;
jtag_add_ir_scan(tap, &field, TAP_IDLE);
int retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
uint8_t nibble;
uint32_t hub_info = 0;
for (int i = 0; i < 8; i++) {
field.num_bits = 4;
field.out_value = NULL;
field.in_value = &nibble;
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
hub_info = ((hub_info >> 4) | ((nibble & 0xf) << 28));
}
int nb_nodes = NB_NODES(hub_info);
int m_width = M_WIDTH(hub_info);
LOG_DEBUG("SLD HUB Configuration register");
LOG_DEBUG("------------------------------");
LOG_DEBUG("m_width = %d", m_width);
LOG_DEBUG("manufacturer_id = 0x%02x", MANUF(hub_info));
LOG_DEBUG("nb_of_node = %d", nb_nodes);
LOG_DEBUG("version = %d", VER(hub_info));
LOG_DEBUG("VIR length = %d", guess_addr_width(nb_nodes) + m_width);
/* Because the number of SLD nodes is now known, the Nodes on the hub can be
* enumerated by repeating the 8 four-bit nibble scans, once for each Node,
* to yield the SLD_NODE_INFO register of each Node. The DR nibble shifts
* are a continuation of the HUB_INFO DR shift used to shift out the Hub IP
* Configuration register.
*
* The order of the Nodes as they are shifted out determines the ADDR
* values for the Nodes, beginning with, for the first Node SLD_NODE_INFO
* shifted out, up to and including, for the last node on the hub. The
* tables below show the SLD_NODE_INFO register and a their functional descriptions.
*
* --------------+-----------+---------------+----------------
* 31 27 | 26 19 | 18 8 | 7 0
* --------------+-----------+---------------+----------------
* Node Version | NODE ID | NODE MFG_ID | NODE INST ID
*
*/
int vjtag_node_address = -1;
int node_index;
uint32_t node_info = 0;
for (node_index = 0; node_index < nb_nodes; node_index++) {
for (int i = 0; i < 8; i++) {
field.num_bits = 4;
field.out_value = NULL;
field.in_value = &nibble;
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
retval = jtag_execute_queue();
if (retval != ERROR_OK)
return retval;
node_info = ((node_info >> 4) | ((nibble & 0xf) << 28));
}
LOG_DEBUG("Node info register");
LOG_DEBUG("--------------------");
LOG_DEBUG("instance_id = %d", ID(node_info));
LOG_DEBUG("manufacturer_id = 0x%02x", MANUF(node_info));
LOG_DEBUG("node_id = %d (%s)", ID(node_info),
id_to_string(ID(node_info)));
LOG_DEBUG("version = %d", VER(node_info));
if (ID(node_info) == VJTAG_NODE_ID)
vjtag_node_address = node_index + 1;
}
if (vjtag_node_address < 0) {
LOG_ERROR("No VJTAG TAP instance found !");
return ERROR_FAIL;
}
/* Select VIR */
t[0] = ALTERA_CYCLONE_CMD_USER1;
field.num_bits = tap->ir_length;
field.out_value = t;
field.in_value = NULL;
jtag_add_ir_scan(tap, &field, TAP_IDLE);
/* Send the DEBUG command to the VJTAG IR */
buf_set_u32(t, 0, field.num_bits, (vjtag_node_address << m_width) | ALT_VJTAG_CMD_DEBUG);
field.num_bits = guess_addr_width(nb_nodes) + m_width;
field.out_value = t;
field.in_value = NULL;
jtag_add_dr_scan(tap, 1, &field, TAP_IDLE);
/* Select the VJTAG DR */
t[0] = ALTERA_CYCLONE_CMD_USER0;
field.num_bits = tap->ir_length;
field.out_value = t;
field.in_value = NULL;
jtag_add_ir_scan(tap, &field, TAP_IDLE);
return jtag_execute_queue();
}
static struct or1k_tap_ip vjtag_tap = {
.name = "vjtag",
.init = or1k_tap_vjtag_init,
};
int or1k_tap_vjtag_register(void)
{
list_add_tail(&vjtag_tap.list, &tap_list);
return 0;
}

2
src/target/target.c
View File

@@ -101,6 +101,7 @@ extern struct target_type hla_target;
extern struct target_type nds32_v2_target;
extern struct target_type nds32_v3_target;
extern struct target_type nds32_v3m_target;
extern struct target_type or1k_target;
static struct target_type *target_types[] = {
&arm7tdmi_target,
@@ -128,6 +129,7 @@ static struct target_type *target_types[] = {
&nds32_v2_target,
&nds32_v3_target,
&nds32_v3m_target,
&or1k_target,
NULL,
};

42
tcl/board/or1k_generic.cfg Normal file
View File

@@ -0,0 +1,42 @@
# If you want to use the VJTAG TAP, you must set your FPGA TAP ID here
set FPGATAPID 0x020b30dd
# Choose your TAP core (VJTAG or MOHOR)
set TAP_TYPE VJTAG
# Set your chip name
set CHIPNAME or1200
source [find target/or1k.cfg]
# Set the adapter speed
adapter_khz 3000
# Enable the target description feature
gdb_target_description enable
# Add a new register in the cpu register list. This register will be
# included in the generated target descriptor file.
# format is addreg [name] [address] [feature] [reg_group]
addreg rtest 0x1234 org.gnu.gdb.or1k.group0 system
# Override default init_reset
proc init_reset {mode} {
soft_reset_halt
resume
}
# Target initialization
init
echo "Halting processor"
halt
foreach name [target names] {
set y [$name cget -endian]
set z [$name cget -type]
puts [format "Chip is %s, Endian: %s, type: %s" \
$name $y $z]
}
set c_blue "\033\[01;34m"
set c_reset "\033\[0m"
puts [format "%sTarget ready...%s" $c_blue $c_reset]

53
tcl/target/or1k.cfg Normal file
View File

@@ -0,0 +1,53 @@
set _ENDIAN big
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME or1k
}
if { [info exists TAP_TYPE] } {
set _TAP_TYPE $TAP_TYPE
} else {
puts "You need to select a tap type"
shutdown
}
# Configure the target
if { [string compare $_TAP_TYPE "VJTAG"] == 0 } {
if { [info exists FPGATAPID] } {
set _FPGATAPID $FPGATAPID
} else {
puts "You need to set your FPGA JTAG ID"
shutdown
}
jtag newtap $_CHIPNAME cpu -irlen 10 -expected-id $_FPGATAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
# Select the TAP core we are using
tap_select vjtag
} else {
# OpenCores Mohor JTAG TAP ID
set _CPUTAPID 0x14951185
jtag newtap $_CHIPNAME cpu -irlen 4 -expected-id $_CPUTAPID
set _TARGETNAME $_CHIPNAME.cpu
target create $_TARGETNAME or1k -endian $_ENDIAN -chain-position $_TARGETNAME
# Select the TAP core we are using
tap_select mohor
}
# Select the debug unit core we are using. This debug unit as an option.
proc ADBG_USE_HISPEED {} { return 1 }
# If ADBG_USE_HISPEED is set (options bit 1), status bits will be skipped
# on burst reads and writes to improve download speeds.
# This option must match the RTL configured option.
du_select adv [ADBG_USE_HISPEED]