linuxmsm/openocd
0
0
Fork 0
mirror of https://github.com/linux-msm/openocd.git synced 2026-02-25 13:15:07 -08:00
Code Issues Packages Projects Releases Wiki Activity

- merged XScale branch back into trunk

Browse Source 
- fixed some compiler warnigns in amt_jtagaccel.c, bitbang.c, parport.c
- free working area and register stuff if str7x block write algorithm failed
- check PC after exiting a target algorithm in armv4_5.c


git-svn-id: svn://svn.berlios.de/openocd/trunk@135 b42882b7-edfa-0310-969c-e2dbd0fdcd60
This commit is contained in:
drath
2007-03-28 16:31:55 +00:00
parent 5ed126c4f9
commit 4a5f45e87d
21 changed files with 5039 additions and 75 deletions
Download Patch File Download Diff File Expand all files Collapse all files

9
src/flash/str7x.c
View File

@@ -451,7 +451,7 @@ int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
u32 address = bank->base + offset;
reg_param_t reg_params[5];
armv4_5_algorithm_t armv4_5_info;
int retval;
int retval = ERROR_OK;
u32 str7x_flash_write_code[] = {
/* write: */
@@ -537,12 +537,13 @@ int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
if ((retval = target->type->run_algorithm(target, 0, NULL, 5, reg_params, str7x_info->write_algorithm->address, str7x_info->write_algorithm->address + (19 * 4), 10000, &armv4_5_info)) != ERROR_OK)
{
ERROR("error executing str7x flash write algorithm");
return ERROR_FLASH_OPERATION_FAILED;
break;
}
if (buf_get_u32(reg_params[4].value, 0, 32) != 0x00)
{
return ERROR_FLASH_OPERATION_FAILED;
retval = ERROR_FLASH_OPERATION_FAILED;
break;
}
buffer += thisrun_count * 8;
@@ -558,7 +559,7 @@ int str7x_write_block(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 cou
destroy_reg_param(&reg_params[3]);
destroy_reg_param(&reg_params[4]);
return ERROR_OK;
return retval;
}
int str7x_write(struct flash_bank_s *bank, u8 *buffer, u32 offset, u32 count)

21
src/helper/fileio.c
View File

@@ -242,22 +242,23 @@ int fileio_open(fileio_t *fileio, char *url, enum fileio_access access,
enum fileio_pri_type pri_type, void *pri_info, enum fileio_sec_type sec_type)
{
int retval = ERROR_OK;
if ((!url) || (strlen(url) < 3))
char *resource_identifier = NULL;
/* try to identify file location */
if ((resource_identifier = strstr(url, "bootp://")) && (resource_identifier == url))
{
snprintf(fileio->error_str, FILEIO_MAX_ERROR_STRING, "invalid file url");
return ERROR_INVALID_ARGUMENTS;
ERROR("bootp resource location isn't supported yet");
return ERROR_FILEIO_RESOURCE_TYPE_UNKNOWN;
}
if ((url[0] == '/') || (isalpha(url[0])) || ((url[1] == ':') && (url[2] == '\\')))
else if ((resource_identifier = strstr(url, "tftp://")) && (resource_identifier == url))
{
fileio->location = FILEIO_LOCAL;
ERROR("tftp resource location isn't supported yet");
return ERROR_FILEIO_RESOURCE_TYPE_UNKNOWN;
}
else
{
ERROR("couldn't identify resource location from URL '%s'", url);
snprintf(fileio->error_str, FILEIO_MAX_ERROR_STRING, "couldn't identify resource location from URL '%s'", url);
return ERROR_FILEIO_LOCATION_UNKNOWN;
/* default to local files */
fileio->location = FILEIO_LOCAL;
}
fileio->access = access;

2
src/jtag/amt_jtagaccel.c
View File

@@ -385,7 +385,7 @@ int amt_jtagaccel_execute_queue(void)
break;
case JTAG_SLEEP:
#ifdef _DEBUG_JTAG_IO_
DEBUG("sleep", cmd->cmd.sleep->us);
DEBUG("sleep %i", cmd->cmd.sleep->us);
#endif
jtag_sleep(cmd->cmd.sleep->us);
break;

2
src/jtag/bitbang.c
View File

@@ -248,7 +248,7 @@ int bitbang_execute_queue(void)
break;
case JTAG_SLEEP:
#ifdef _DEBUG_JTAG_IO_
DEBUG("sleep", cmd->cmd.sleep->us);
DEBUG("sleep %i", cmd->cmd.sleep->us);
#endif
jtag_sleep(cmd->cmd.sleep->us);
break;

2
src/jtag/parport.c
View File

@@ -375,7 +375,7 @@ int parport_init(void)
dataport = parport_port;
statusport = parport_port + 1;
DEBUG("requesting privileges for parallel port 0x%x...", dataport);
DEBUG("requesting privileges for parallel port 0x%lx...", dataport);
#if PARPORT_USE_GIVEIO == 1
if (parport_get_giveio_access() != 0)
#else /* PARPORT_USE_GIVEIO */

2
src/openocd.c
View File

@@ -18,7 +18,7 @@
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-03-15 14:30 CET)"
#define OPENOCD_VERSION "Open On-Chip Debugger (2007-03-28 18:30 CEST)"
#ifdef HAVE_CONFIG_H
#include "config.h"

4
src/target/Makefile.am
View File

@@ -3,7 +3,7 @@ METASOURCES = AUTO
noinst_LIBRARIES = libtarget.a
libtarget_a_SOURCES = target.c register.c breakpoints.c armv4_5.c embeddedice.c etm.c arm7tdmi.c arm9tdmi.c \
arm_jtag.c arm7_9_common.c algorithm.c arm920t.c arm720t.c armv4_5_mmu.c armv4_5_cache.c arm_disassembler.c \
arm966e.c arm926ejs.c etb.c
arm966e.c arm926ejs.c etb.c xscale.c arm_simulator.c
noinst_HEADERS = target.h register.h armv4_5.h embeddedice.h etm.h arm7tdmi.h arm9tdmi.h \
arm_jtag.h arm7_9_common.h arm920t.h arm720t.h armv4_5_mmu.h armv4_5_cache.h breakpoints.h algorithm.h \
arm_disassembler.h arm966e.h arm926ejs.h etb.h
arm_disassembler.h arm966e.h arm926ejs.h etb.h xscale.h arm_simulator.h

35
src/target/arm_disassembler.c
View File

@@ -835,6 +835,9 @@ int evaluate_misc_instr(u32 opcode, u32 address, arm_instruction_t *instruction)
snprintf(instruction->text, 128, "0x%8.8x\t0x%8.8x\tBLX%s r%i",
address, opcode, COND(opcode), Rm);
instruction->info.b_bl_bx_blx.reg_operand = Rm;
instruction->info.b_bl_bx_blx.target_address = -1;
}
/* Enhanced DSP add/subtracts */
@@ -1078,6 +1081,18 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
instruction->info.data_proc.shifter_operand.immediate_shift.shift_imm = shift_imm;
instruction->info.data_proc.shifter_operand.immediate_shift.shift = shift;
/* LSR encodes a shift by 32 bit as 0x0 */
if ((shift == 0x1) && (shift_imm == 0x0))
shift_imm = 0x20;
/* ASR encodes a shift by 32 bit as 0x0 */
if ((shift == 0x2) && (shift_imm == 0x0))
shift_imm = 0x20;
/* ROR by 32 bit is actually a RRX */
if ((shift == 0x3) && (shift_imm == 0x0))
shift = 0x4;
if ((shift_imm == 0x0) && (shift == 0x0))
{
snprintf(shifter_operand, 32, "r%i", Rm);
@@ -1090,22 +1105,19 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
}
else if (shift == 0x1) /* LSR */
{
if (shift_imm == 0x0)
shift_imm = 0x32;
snprintf(shifter_operand, 32, "r%i, LSR #0x%x", Rm, shift_imm);
}
else if (shift == 0x2) /* ASR */
{
if (shift_imm == 0x0)
shift_imm = 0x32;
snprintf(shifter_operand, 32, "r%i, ASR #0x%x", Rm, shift_imm);
}
else if (shift == 0x3) /* ROR or RRX */
else if (shift == 0x3) /* ROR */
{
if (shift_imm == 0x0) /* RRX */
snprintf(shifter_operand, 32, "r%i, RRX", Rm);
else
snprintf(shifter_operand, 32, "r%i, ROR #0x%x", Rm, shift_imm);
snprintf(shifter_operand, 32, "r%i, ROR #0x%x", Rm, shift_imm);
}
else if (shift == 0x4) /* RRX */
{
snprintf(shifter_operand, 32, "r%i, RRX", Rm);
}
}
}
@@ -1130,7 +1142,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
{
snprintf(shifter_operand, 32, "r%i, ASR r%i", Rm, Rs);
}
else if (shift == 0x3) /* ROR or RRX */
else if (shift == 0x3) /* ROR */
{
snprintf(shifter_operand, 32, "r%i, ROR r%i", Rm, Rs);
}
@@ -1159,7 +1171,7 @@ int evaluate_data_proc(u32 opcode, u32 address, arm_instruction_t *instruction)
return ERROR_OK;
}
int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
{
/* clear fields, to avoid confusion */
memset(instruction, 0, sizeof(arm_instruction_t));
@@ -1302,3 +1314,4 @@ int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction)
ERROR("should never reach this point");
return -1;
}

36
src/target/arm_disassembler.h
View File

@@ -126,28 +126,30 @@ typedef struct arm_b_bl_bx_blx_instr_s
u32 target_address;
} arm_b_bl_bx_blx_instr_t;
union arm_shifter_operand
{
struct {
u32 immediate;
} immediate;
struct {
u8 Rm;
u8 shift;
u8 shift_imm;
} immediate_shift;
struct {
u8 Rm;
u8 shift;
u8 Rs;
} register_shift;
};
typedef struct arm_data_proc_instr_s
{
int variant; /* 0: immediate, 1: immediate_shift, 2: register_shift */
u8 S;
u8 Rn;
u8 Rd;
union
{
struct {
u8 immediate;
} immediate;
struct {
u8 Rm;
u8 shift;
u8 shift_imm;
} immediate_shift;
struct {
u8 Rm;
u8 shift;
u8 Rs;
} register_shift;
} shifter_operand;
union arm_shifter_operand shifter_operand;
} arm_data_proc_instr_t;
typedef struct arm_load_store_instr_s
@@ -192,7 +194,7 @@ typedef struct arm_instruction_s
} arm_instruction_t;
extern int evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
extern int arm_evaluate_opcode(u32 opcode, u32 address, arm_instruction_t *instruction);
#define COND(opcode) (arm_condition_strings[(opcode & 0xf0000000)>>28])

684
src/target/arm_simulator.c Normal file
View File

File diff suppressed because it is too large Load Diff

31
src/target/arm_simulator.h Normal file
View File

@@ -0,0 +1,31 @@
/***************************************************************************
* Copyright (C) 2006 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef ARM_SIMULATOR_H
#define ARM_SIMULATOR_H
#include "target.h"
#include "types.h"
extern int arm_simulate_step(target_t *target, u32 *dry_run_pc);
#define ERROR_ARM_SIMULATOR_NOT_IMPLEMENTED (-1000)
#endif /* ARM_SIMULATOR_H */

9
src/target/armv4_5.c
View File

@@ -442,7 +442,7 @@ int handle_armv4_5_disassemble_command(struct command_context_s *cmd_ctx, char *
for (i = 0; i < count; i++)
{
target_read_u32(target, address, &opcode);
evaluate_opcode(opcode, address, &cur_instruction);
arm_evaluate_opcode(opcode, address, &cur_instruction);
command_print(cmd_ctx, "%s", cur_instruction.text);
address += (thumb) ? 2 : 4;
}
@@ -598,6 +598,13 @@ int armv4_5_run_algorithm(struct target_s *target, int num_mem_params, mem_param
}
}
if ((retval != ERROR_TARGET_TIMEOUT) &&
(buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32) != exit_point))
{
WARNING("target reentered debug state, but not at the desired exit point: 0x%4.4x",
buf_get_u32(armv4_5->core_cache->reg_list[15].value, 0, 32));
}
breakpoint_remove(target, exit_point);
for (i = 0; i < num_mem_params; i++)

10
src/target/armv4_5.h
View File

@@ -213,6 +213,11 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
*/
#define ARMV4_5_MCR(CP, op1, Rd, CRn, CRm, op2) (0xee000010 | (CRm) | ((op2) << 5) | ((CP) << 8) | ((Rd) << 12) | ((CRn) << 16) | ((op1) << 21))
/* Breakpoint instruction (ARMv5)
* Im: 16-bit immediate
*/
#define ARMV5_BKPT(Im) (0xe1200070 | ((Im & 0xfff0) << 8) | (Im & 0xf))
/* Thumb mode instructions
*/
@@ -266,4 +271,9 @@ extern int armv4_5_invalidate_core_regs(target_t *target);
*/
#define ARMV4_5_T_B(Imm) ((0xe000 | (Imm)) | ((0xe000 | (Imm)) << 16))
/* Breakpoint instruction (ARMv5) (Thumb state)
* Im: 8-bit immediate
*/
#define ARMV5_T_BKPT(Im) ((0xbe00 | Im) | ((0xbe00 | Im) << 16))
#endif /* ARMV4_5_H */

89
src/target/target.c
View File

@@ -79,6 +79,7 @@ extern target_type_t arm9tdmi_target;
extern target_type_t arm920t_target;
extern target_type_t arm966e_target;
extern target_type_t arm926ejs_target;
extern target_type_t xscale_target;
target_type_t *target_types[] =
{
@@ -88,6 +89,7 @@ target_type_t *target_types[] =
&arm720t_target,
&arm966e_target,
&arm926ejs_target,
&xscale_target,
NULL,
};
@@ -727,60 +729,107 @@ int target_read_buffer(struct target_s *target, u32 address, u32 size, u8 *buffe
return ERROR_OK;
}
void target_read_u32(struct target_s *target, u32 address, u32 *value)
int target_read_u32(struct target_s *target, u32 address, u32 *value)
{
u8 value_buf[4];
target->type->read_memory(target, address, 4, 1, value_buf);
*value = target_buffer_get_u32(target, value_buf);
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, *value);
int retval = target->type->read_memory(target, address, 4, 1, value_buf);
if (retval == ERROR_OK)
{
*value = target_buffer_get_u32(target, value_buf);
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, *value);
}
else
{
*value = 0x0;
DEBUG("address: 0x%8.8x failed", address);
}
return retval;
}
void target_read_u16(struct target_s *target, u32 address, u16 *value)
int target_read_u16(struct target_s *target, u32 address, u16 *value)
{
u8 value_buf[2];
target->type->read_memory(target, address, 2, 1, value_buf);
int retval = target->type->read_memory(target, address, 2, 1, value_buf);
*value = target_buffer_get_u16(target, value_buf);
DEBUG("address: 0x%8.8x, value: 0x%4.4x", address, *value);
if (retval == ERROR_OK)
{
*value = target_buffer_get_u16(target, value_buf);
DEBUG("address: 0x%8.8x, value: 0x%4.4x", address, *value);
}
else
{
*value = 0x0;
DEBUG("address: 0x%8.8x failed", address);
}
return retval;
}
void target_read_u8(struct target_s *target, u32 address, u8 *value)
int target_read_u8(struct target_s *target, u32 address, u8 *value)
{
target->type->read_memory(target, address, 1, 1, value);
int retval = target->type->read_memory(target, address, 1, 1, value);
DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, *value);
if (retval == ERROR_OK)
{
DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, *value);
}
else
{
*value = 0x0;
DEBUG("address: 0x%8.8x failed", address);
}
return retval;
}
void target_write_u32(struct target_s *target, u32 address, u32 value)
int target_write_u32(struct target_s *target, u32 address, u32 value)
{
int retval;
u8 value_buf[4];
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
target_buffer_set_u32(target, value_buf, value);
target->type->write_memory(target, address, 4, 1, value_buf);
if ((retval = target->type->write_memory(target, address, 4, 1, value_buf)) != ERROR_OK)
{
DEBUG("failed: %i", retval);
}
return retval;
}
void target_write_u16(struct target_s *target, u32 address, u16 value)
int target_write_u16(struct target_s *target, u32 address, u16 value)
{
int retval;
u8 value_buf[2];
DEBUG("address: 0x%8.8x, value: 0x%8.8x", address, value);
target_buffer_set_u16(target, value_buf, value);
target->type->write_memory(target, address, 2, 1, value_buf);
if ((retval = target->type->write_memory(target, address, 2, 1, value_buf)) != ERROR_OK)
{
DEBUG("failed: %i", retval);
}
return retval;
}
void target_write_u8(struct target_s *target, u32 address, u8 value)
int target_write_u8(struct target_s *target, u32 address, u8 value)
{
int retval;
DEBUG("address: 0x%8.8x, value: 0x%2.2x", address, value);
target->type->read_memory(target, address, 1, 1, &value);
if ((retval = target->type->read_memory(target, address, 1, 1, &value)) != ERROR_OK)
{
DEBUG("failed: %i", retval);
}
return retval;
}
int target_register_user_commands(struct command_context_s *cmd_ctx)

14
src/target/target.h
View File

@@ -50,6 +50,8 @@ enum daemon_startup_mode
DAEMON_RESET, /* reset target (behaviour defined by reset_mode */
};
extern enum daemon_startup_mode startup_mode;
enum target_reset_mode
{
RESET_RUN = 0, /* reset and let target run */
@@ -222,12 +224,12 @@ extern u16 target_buffer_get_u16(target_t *target, u8 *buffer);
extern void target_buffer_set_u32(target_t *target, u8 *buffer, u32 value);
extern void target_buffer_set_u16(target_t *target, u8 *buffer, u16 value);
void target_read_u32(struct target_s *target, u32 address, u32 *value);
void target_read_u16(struct target_s *target, u32 address, u16 *value);
void target_read_u8(struct target_s *target, u32 address, u8 *value);
void target_write_u32(struct target_s *target, u32 address, u32 value);
void target_write_u16(struct target_s *target, u32 address, u16 value);
void target_write_u8(struct target_s *target, u32 address, u8 value);
int target_read_u32(struct target_s *target, u32 address, u32 *value);
int target_read_u16(struct target_s *target, u32 address, u16 *value);
int target_read_u8(struct target_s *target, u32 address, u8 *value);
int target_write_u32(struct target_s *target, u32 address, u32 value);
int target_write_u16(struct target_s *target, u32 address, u16 value);
int target_write_u8(struct target_s *target, u32 address, u8 value);
#define ERROR_TARGET_INVALID (-300)
#define ERROR_TARGET_INIT_FAILED (-301)

3175
src/target/xscale.c Normal file
View File

File diff suppressed because it is too large Load Diff

145
src/target/xscale.h Normal file
View File

@@ -0,0 +1,145 @@
/***************************************************************************
* Copyright (C) 2005 by Dominic Rath *
* Dominic.Rath@gmx.de *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program; if not, write to the *
* Free Software Foundation, Inc., *
* 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. *
***************************************************************************/
#ifndef XSCALE_H
#define XSCALE_H
#include "target.h"
#include "register.h"
#include "armv4_5.h"
#include "armv4_5_mmu.h"
#define XSCALE_COMMON_MAGIC 0x58534341
typedef struct xscale_jtag_s
{
/* position in JTAG scan chain */
int chain_pos;
/* IR length and instructions */
int ir_length;
u32 dbgrx;
u32 dbgtx;
u32 ldic;
u32 dcsr;
} xscale_jtag_t;
enum xscale_debug_reason
{
XSCALE_DBG_REASON_GENERIC,
XSCALE_DBG_REASON_RESET,
XSCALE_DBG_REASON_TB_FULL,
};
typedef struct xscale_common_s
{
int common_magic;
/* XScale registers (CP15, DBG) */
reg_cache_t *reg_cache;
/* pxa250, pxa255, pxa27x, ixp42x, ... */
char *variant;
xscale_jtag_t jtag_info;
/* current state of the debug handler */
int handler_installed;
int handler_running;
u32 handler_address;
/* target-endian buffers with exception vectors */
u32 low_vectors[8];
u32 high_vectors[8];
/* static low vectors */
u8 static_low_vectors_set; /* bit field with static vectors set by the user */
u8 static_high_vectors_set; /* bit field with static vectors set by the user */
u32 static_low_vectors[8];
u32 static_high_vectors[8];
/* DCache cleaning */
u32 cache_clean_address;
/* whether hold_rst and ext_dbg_break should be set */
int hold_rst;
int external_debug_break;
/* breakpoint / watchpoint handling */
int force_hw_bkpts;
int dbr_available;
int dbr0_used;
int dbr1_used;
int ibcr_available;
int ibcr0_used;
int ibcr1_used;
u32 arm_bkpt;
u16 thumb_bkpt;
u8 vector_catch;
int trace_buffer_enabled;
int trace_buffer_fill;
int arch_debug_reason;
/* armv4/5 common stuff */
armv4_5_common_t armv4_5_common;
/* MMU/Caches */
armv4_5_mmu_common_t armv4_5_mmu;
u32 cp15_control_reg;
/* possible future enhancements that go beyond XScale common stuff */
void *arch_info;
} xscale_common_t;
typedef struct xscale_reg_s
{
int dbg_handler_number;
target_t *target;
} xscale_reg_t;
enum
{
XSCALE_MAINID, /* 0 */
XSCALE_CACHETYPE,
XSCALE_CTRL,
XSCALE_AUXCTRL,
XSCALE_TTB,
XSCALE_DAC,
XSCALE_FSR,
XSCALE_FAR,
XSCALE_PID,
XSCALE_CPACCESS,
XSCALE_IBCR0, /* 10 */
XSCALE_IBCR1,
XSCALE_DBR0,
XSCALE_DBR1,
XSCALE_DBCON,
XSCALE_TBREG,
XSCALE_CHKPT0,
XSCALE_CHKPT1,
XSCALE_DCSR,
XSCALE_TX,
XSCALE_RX, /* 20 */
XSCALE_TXRXCTRL,
};
#endif /* XSCALE_H */

7
src/target/xscale/build.sh Normal file
View File

@@ -0,0 +1,7 @@
arm-none-eabi-gcc -c debug_handler.S -o debug_handler.o
arm-none-eabi-ld -EL -n -Tdebug_handler.cmd debug_handler.o -o debug_handler.out
arm-none-eabi-objcopy -O binary debug_handler.out debug_handler.bin
#arm-none-eabi-gcc -mbig-endian -c debug_handler.S -o debug_handler_be.o
#arm-none-eabi-ld -EB -n -Tdebug_handler.cmd debug_handler_be.o -o debug_handler_be.out
#arm-none-eabi-objcopy -O binary debug_handler_be.out debug_handler_be.bin

718
src/target/xscale/debug_handler.S Normal file
View File

File diff suppressed because it is too large Load Diff

49
src/target/xscale/debug_handler.cmd Normal file
View File

@@ -0,0 +1,49 @@
/* identify the Entry Point */
ENTRY(reset_handler)
/* specify the mini-ICache memory areas */
MEMORY
{
mini_icache_0 (x) : ORIGIN = 0x0, LENGTH = 1024 /* first part of mini icache (sets 0-31) */
mini_icache_1 (x) : ORIGIN = 0x400, LENGTH = 1024 /* second part of mini icache (sets 0-31) */
}
/* now define the output sections */
SECTIONS
{
.part1 :
{
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
*(.part1)
} >mini_icache_0
.part2 :
{
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
LONG(0)
*(.part2)
FILL(0x0)
} >mini_icache_1
/DISCARD/ :
{
*(.text)
*(.glue_7)
*(.glue_7t)
*(.data)
*(.bss)
}
}

Some files were not shown because too many files have changed in this diff Show More