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Renamed mx2/imx27 to mxc.
Renamed all functions, enums, structs and defines from mx2/imx27 to mxc. This is in preparation of adding support for mx35 NFC(v2). Change-Id: I92ad23f0cfab605215bbf0d5846c5c288423facf Signed-off-by: Erik Ahlén <erik.ahlen@avalonenterprise.com> Reviewed-on: http://openocd.zylin.com/267 Tested-by: jenkins Reviewed-by: Øyvind Harboe <oyvindharboe@gmail.com>
This commit is contained in:
Erik Ahlén
committed by
Øyvind Harboe
Øyvind Harboe
parent
c10a315f91
commit
46cc1df722
@@ -38,7 +38,7 @@ extern struct nand_flash_controller s3c2412_nand_controller;
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extern struct nand_flash_controller s3c2440_nand_controller;
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extern struct nand_flash_controller s3c2443_nand_controller;
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extern struct nand_flash_controller s3c6400_nand_controller;
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extern struct nand_flash_controller imx27_nand_flash_controller;
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extern struct nand_flash_controller mxc_nand_flash_controller;
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extern struct nand_flash_controller imx31_nand_flash_controller;
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extern struct nand_flash_controller at91sam9_nand_controller;
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extern struct nand_flash_controller nuc910_nand_controller;
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@@ -57,7 +57,7 @@ static struct nand_flash_controller *nand_flash_controllers[] =
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&s3c2440_nand_controller,
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&s3c2443_nand_controller,
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&s3c6400_nand_controller,
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&imx27_nand_flash_controller,
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&mxc_nand_flash_controller,
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&imx31_nand_flash_controller,
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&at91sam9_nand_controller,
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&nuc910_nand_controller,
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File diff suppressed because it is too large
Load Diff
@@ -21,88 +21,88 @@
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***************************************************************************/
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/*
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* Freescale iMX2* OpenOCD NAND Flash controller support.
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* based on Freescale iMX3* OpenOCD NAND Flash controller support.
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* Freescale iMX OpenOCD NAND Flash controller support.
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* based on Freescale iMX2* and iMX3* OpenOCD NAND Flash controller support.
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*
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* Many thanks to Ben Dooks for writing s3c24xx driver.
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*/
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#define MX2_NF_BASE_ADDR 0xd8000000
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#define MX2_NF_BUFSIZ (MX2_NF_BASE_ADDR + 0xe00)
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#define MX2_NF_BUFADDR (MX2_NF_BASE_ADDR + 0xe04)
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#define MX2_NF_FADDR (MX2_NF_BASE_ADDR + 0xe06)
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#define MX2_NF_FCMD (MX2_NF_BASE_ADDR + 0xe08)
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#define MX2_NF_BUFCFG (MX2_NF_BASE_ADDR + 0xe0a)
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#define MX2_NF_ECCSTATUS (MX2_NF_BASE_ADDR + 0xe0c)
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#define MX2_NF_ECCMAINPOS (MX2_NF_BASE_ADDR + 0xe0e)
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#define MX2_NF_ECCSPAREPOS (MX2_NF_BASE_ADDR + 0xe10)
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#define MX2_NF_FWP (MX2_NF_BASE_ADDR + 0xe12)
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#define MX2_NF_LOCKSTART (MX2_NF_BASE_ADDR + 0xe14)
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#define MX2_NF_LOCKEND (MX2_NF_BASE_ADDR + 0xe16)
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#define MX2_NF_FWPSTATUS (MX2_NF_BASE_ADDR + 0xe18)
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#define MXC_NF_BASE_ADDR 0xd8000000
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#define MXC_NF_BUFSIZ (MXC_NF_BASE_ADDR + 0xe00)
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#define MXC_NF_BUFADDR (MXC_NF_BASE_ADDR + 0xe04)
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#define MXC_NF_FADDR (MXC_NF_BASE_ADDR + 0xe06)
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#define MXC_NF_FCMD (MXC_NF_BASE_ADDR + 0xe08)
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#define MXC_NF_BUFCFG (MXC_NF_BASE_ADDR + 0xe0a)
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#define MXC_NF_ECCSTATUS (MXC_NF_BASE_ADDR + 0xe0c)
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#define MXC_NF_ECCMAINPOS (MXC_NF_BASE_ADDR + 0xe0e)
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#define MXC_NF_ECCSPAREPOS (MXC_NF_BASE_ADDR + 0xe10)
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#define MXC_NF_FWP (MXC_NF_BASE_ADDR + 0xe12)
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#define MXC_NF_LOCKSTART (MXC_NF_BASE_ADDR + 0xe14)
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#define MXC_NF_LOCKEND (MXC_NF_BASE_ADDR + 0xe16)
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#define MXC_NF_FWPSTATUS (MXC_NF_BASE_ADDR + 0xe18)
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/*
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* all bits not marked as self-clearing bit
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*/
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#define MX2_NF_CFG1 (MX2_NF_BASE_ADDR + 0xe1a)
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#define MX2_NF_CFG2 (MX2_NF_BASE_ADDR + 0xe1c)
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#define MXC_NF_CFG1 (MXC_NF_BASE_ADDR + 0xe1a)
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#define MXC_NF_CFG2 (MXC_NF_BASE_ADDR + 0xe1c)
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#define MX2_NF_MAIN_BUFFER0 (MX2_NF_BASE_ADDR + 0x0000)
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#define MX2_NF_MAIN_BUFFER1 (MX2_NF_BASE_ADDR + 0x0200)
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#define MX2_NF_MAIN_BUFFER2 (MX2_NF_BASE_ADDR + 0x0400)
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#define MX2_NF_MAIN_BUFFER3 (MX2_NF_BASE_ADDR + 0x0600)
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#define MX2_NF_SPARE_BUFFER0 (MX2_NF_BASE_ADDR + 0x0800)
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#define MX2_NF_SPARE_BUFFER1 (MX2_NF_BASE_ADDR + 0x0810)
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#define MX2_NF_SPARE_BUFFER2 (MX2_NF_BASE_ADDR + 0x0820)
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#define MX2_NF_SPARE_BUFFER3 (MX2_NF_BASE_ADDR + 0x0830)
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#define MX2_NF_MAIN_BUFFER_LEN 512
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#define MX2_NF_SPARE_BUFFER_LEN 16
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#define MX2_NF_LAST_BUFFER_ADDR ((MX2_NF_SPARE_BUFFER3) + \
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MX2_NF_SPARE_BUFFER_LEN - 2)
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#define MXC_NF_MAIN_BUFFER0 (MXC_NF_BASE_ADDR + 0x0000)
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#define MXC_NF_MAIN_BUFFER1 (MXC_NF_BASE_ADDR + 0x0200)
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#define MXC_NF_MAIN_BUFFER2 (MXC_NF_BASE_ADDR + 0x0400)
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#define MXC_NF_MAIN_BUFFER3 (MXC_NF_BASE_ADDR + 0x0600)
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#define MXC_NF_SPARE_BUFFER0 (MXC_NF_BASE_ADDR + 0x0800)
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#define MXC_NF_SPARE_BUFFER1 (MXC_NF_BASE_ADDR + 0x0810)
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#define MXC_NF_SPARE_BUFFER2 (MXC_NF_BASE_ADDR + 0x0820)
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#define MXC_NF_SPARE_BUFFER3 (MXC_NF_BASE_ADDR + 0x0830)
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#define MXC_NF_MAIN_BUFFER_LEN 512
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#define MXC_NF_SPARE_BUFFER_LEN 16
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#define MXC_NF_LAST_BUFFER_ADDR ((MXC_NF_SPARE_BUFFER3) + \
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MXC_NF_SPARE_BUFFER_LEN - 2)
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/* bits in MX2_NF_CFG1 register */
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#define MX2_NF_BIT_SPARE_ONLY_EN (1<<2)
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#define MX2_NF_BIT_ECC_EN (1<<3)
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#define MX2_NF_BIT_INT_DIS (1<<4)
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#define MX2_NF_BIT_BE_EN (1<<5)
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#define MX2_NF_BIT_RESET_EN (1<<6)
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#define MX2_NF_BIT_FORCE_CE (1<<7)
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/* bits in MXC_NF_CFG1 register */
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#define MXC_NF_BIT_SPARE_ONLY_EN (1<<2)
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#define MXC_NF_BIT_ECC_EN (1<<3)
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#define MXC_NF_BIT_INT_DIS (1<<4)
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#define MXC_NF_BIT_BE_EN (1<<5)
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#define MXC_NF_BIT_RESET_EN (1<<6)
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#define MXC_NF_BIT_FORCE_CE (1<<7)
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/* bits in MX2_NF_CFG2 register */
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/* bits in MXC_NF_CFG2 register */
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/*Flash Command Input*/
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#define MX2_NF_BIT_OP_FCI (1<<0)
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#define MXC_NF_BIT_OP_FCI (1<<0)
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/*
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* Flash Address Input
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*/
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#define MX2_NF_BIT_OP_FAI (1<<1)
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#define MXC_NF_BIT_OP_FAI (1<<1)
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/*
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* Flash Data Input
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*/
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#define MX2_NF_BIT_OP_FDI (1<<2)
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#define MXC_NF_BIT_OP_FDI (1<<2)
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/* see "enum mx_dataout_type" below */
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#define MX2_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
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#define MX2_NF_BIT_OP_DONE (1<<15)
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#define MXC_NF_BIT_DATAOUT_TYPE(x) ((x)<<3)
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#define MXC_NF_BIT_OP_DONE (1<<15)
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#define MX2_CCM_CGR2 0x53f80028
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#define MX2_GPR 0x43fac008
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/*#define MX2_PCSR 0x53f8000c*/
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#define MX2_FMCR 0x10027814
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#define MX2_FMCR_NF_16BIT_SEL (1<<4)
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#define MX2_FMCR_NF_FMS (1<<5)
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#define MXC_CCM_CGR2 0x53f80028
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#define MXC_GPR 0x43fac008
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/*#define MXC_PCSR 0x53f8000c*/
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#define MXC_FMCR 0x10027814
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#define MXC_FMCR_NF_16BIT_SEL (1<<4)
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#define MXC_FMCR_NF_FMS (1<<5)
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enum mx_dataout_type {
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MX2_NF_DATAOUT_PAGE = 1,
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MX2_NF_DATAOUT_NANDID = 2,
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MX2_NF_DATAOUT_NANDSTATUS = 4,
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enum mxc_dataout_type {
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MXC_NF_DATAOUT_PAGE = 1,
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MXC_NF_DATAOUT_NANDID = 2,
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MXC_NF_DATAOUT_NANDSTATUS = 4,
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};
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enum mx_nf_finalize_action {
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MX2_NF_FIN_NONE,
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MX2_NF_FIN_DATAOUT,
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enum mxc_nf_finalize_action {
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MXC_NF_FIN_NONE,
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MXC_NF_FIN_DATAOUT,
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};
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struct mx2_nf_flags {
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struct mxc_nf_flags {
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unsigned host_little_endian:1;
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unsigned target_little_endian:1;
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unsigned nand_readonly:1;
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@@ -110,8 +110,8 @@ struct mx2_nf_flags {
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unsigned hw_ecc_enabled:1;
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};
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struct mx2_nf_controller {
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enum mx_dataout_type optype;
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enum mx_nf_finalize_action fin;
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struct mx2_nf_flags flags;
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struct mxc_nf_controller {
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enum mxc_dataout_type optype;
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enum mxc_nf_finalize_action fin;
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struct mxc_nf_flags flags;
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};
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@@ -61,4 +61,4 @@ proc tx27_init { } {
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nand probe 0
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}
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nand device tx27.nand imx27 $_TARGETNAME hwecc
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nand device tx27.nand mxc $_TARGETNAME hwecc
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