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psoc6: Run flash algorithm asynchronously to improve performance
Existing psoc6 driver starts flash algorithm for each Flash row. This is suboptimal from performance point of view, starting/stopping flash algorithm for each row adds significant overhead. This change starts flash algorithm and leaves it running asynchronously while driver performs flash operations. Performance gain is 170...250% depending on probe: flash write_image img_256k.bin | w/o this change | with this change | ----------------------------------|-----------------|------------------| KitProg2/CMSIS-DAP, SWD @ 1 MHz | 4 KiB/s | 10 KiB/s | J-Link Ultra, SWD @ 1 MHz | 17 KiB/s | 31 KiB/s | J-Link Ultra, SWD @ 4 MHz | 33 KiB/s | 57 KiB/s | Change-Id: I5bd582584b35af67600c4d197829eb7aeeec7e3f Signed-off-by: Bohdan Tymkiv <bhdt@cypress.com> Reviewed-on: http://openocd.zylin.com/4472 Tested-by: jenkins Reviewed-by: Tomas Vanek <vanekt@fbl.cz>
This commit is contained in:
committed by
Tomas Vanek
parent
b941e2e727
commit
4440bf1fcd
File diff suppressed because it is too large
Load Diff
@@ -82,19 +82,30 @@ proc psoc6_deassert_post { target } {
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$target arp_examine
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global RESET_MODE
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global TARGET
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if { $RESET_MODE ne "run" } {
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$target arp_poll
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$target arp_poll
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set st [$target curstate]
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if { $st eq "reset" } {
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# we assume running state follows
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# if reset accidentally halts, waiting is useless
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catch { $target arp_waitstate running 100 }
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set st [$target curstate]
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}
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if { $st eq "running" } {
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echo "$target: Ran after reset and before halt..."
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$target arp_halt
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if { $target eq "${TARGET}.cm0" } {
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# Try to cleanly reset whole system
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# and halt the CM0 at entry point
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psoc6 reset_halt
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$target arp_waitstate halted 100
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} else {
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$target arp_halt
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}
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}
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}
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}
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@@ -133,3 +144,7 @@ if { $_ENABLE_CM0 } {
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# Use CM0+ by default on dual-core devices
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targets ${TARGET}.cm0
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}
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if {[using_jtag]} {
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swj_newdap $_CHIPNAME bs -irlen 18 -expected-id 0x2e200069
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}
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