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https://github.com/linux-msm/openocd.git
synced 2026-02-25 13:15:07 -08:00
update 'flash bank' usage in scripts
Sets $_FLASHNAME to "$_CHIPNAME.flash" and passes it as the first argument to 'flash bank'.
This commit is contained in:
@@ -10,4 +10,5 @@ reset_config trst_and_srst separate
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# flash bank <driver> <base> <size> <chip_width> <bus_width>
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# 29LV650 64Mbit Flash
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flash bank cfi 0x00000000 0x800000 2 2 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x00000000 0x800000 2 2 0
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@@ -9,4 +9,5 @@ jtag_nsrst_delay 800
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reset_config trst_and_srst separate
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# works for P30 flash
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flash bank cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x00000000 0x2000000 2 2 $_TARGETNAME
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@@ -4,7 +4,8 @@
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source [find target/at91rm9200.cfg]
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# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
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flash bank cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x10000000 0x00800000 2 2 $_TARGETNAME
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# ETM9 trace port connector present on this board, 16 data pins.
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if { [info exists ETM_DRIVER] } {
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@@ -122,4 +122,5 @@ $_TARGETNAME configure -work-area-phys 0x00000000 -work-area-size 0x1000 -work-a
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#M29DW323DB - not working
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#flash bank cfi <base> <size> <chip width> <bus width> <target#>
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flash bank cfi 0x50000000 0x0400000 2 2 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x50000000 0x0400000 2 2 0
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@@ -33,4 +33,5 @@ $_TARGETNAME configure -event reset-init {
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#flash configuration
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#flash bank <driver> <base> <size> <chip_width> <bus_width> [driver_options ...]
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flash bank cfi 0x00000000 0x1000000 2 2 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x00000000 0x1000000 2 2 0
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@@ -28,7 +28,8 @@ $_TARGETNAME configure -event reset-start {
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}
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# External 16-bit flash at chip select CS7 (SST39VF3201-70, 4 MiB)
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flash bank cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x5C000000 0x400000 2 2 $_TARGETNAME jedec_probe
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$_TARGETNAME configure -event reset-init {
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@@ -68,5 +68,7 @@ $_TARGETNAME configure -event reset-init {
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$_TARGETNAME configure -work-area-phys 0x50000000 -work-area-size 16384 -work-area-backup 0
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#flash bank <driver> <base> <size> <chip_width> <bus_width>
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flash bank str9x 0x00000000 0x00080000 0 0 0
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flash bank str9x 0x00080000 0x00008000 0 0 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
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@@ -12,8 +12,10 @@ jtag_ntrst_delay 250
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# CS0, CS1 -- two banks of CFI flash, 32 MBytes each
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# each bank is 32-bits wide, two 16-bit chips in parallel
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flash bank cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
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flash bank cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x00000000 0x02000000 2 4 $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 4 $_TARGETNAME
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# CS2 low -- FPGA registers
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# CS2 high -- 1 MByte SRAM at 0x0a00.0000 ... last 64K for scratch
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@@ -8,5 +8,7 @@ reset_config trst_and_srst separate
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# Board configs can vary a *LOT* ... parts, jumpers, etc.
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# This GP board boots from cs0 using NOR (2x32M), and also
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# has 64M NAND on cs6.
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flash bank cfi 0x04000000 0x02000000 2 2 $_TARGETNAME
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flash bank cfi 0x06000000 0x02000000 2 2 $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x04000000 0x02000000 2 2 $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x06000000 0x02000000 2 2 $_TARGETNAME
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@@ -19,8 +19,10 @@ etm_dummy config $_TARGETNAME
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# standard boards populate two 16 MB chips, but manufacturing
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# options or an expansion board could change this config.
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flash bank cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
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flash bank cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x00000000 0x01000000 2 2 $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x01000000 0x01000000 2 2 $_TARGETNAME
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proc osk5912_init {} {
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omap5912_reset
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@@ -13,7 +13,8 @@ source [find target/pxa255.cfg]
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$_TARGETNAME configure -work-area-phys 0x4000000 -work-area-size 0x4000 -work-area-backup 0
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# flash bank <driver> <base> <size> <chip_width> <bus_width> <target> [options]
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flash bank cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x00000000 0x80000 2 2 $_TARGETNAME jedec_probe
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proc pxa255_sst_init {} {
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xscale cp15 15 0x00002001 #Enable CP0 and CP13 access
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@@ -54,8 +54,10 @@ $_TARGETNAME configure -event reset-init {
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}
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#flash bank str9x <base> <size> 0 0 <target#> <variant>
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flash bank str9x 0x00000000 0x00080000 0 0 0
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flash bank str9x 0x00080000 0x00008000 0 0 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME str9x 0x00000000 0x00080000 0 0 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME str9x 0x00080000 0x00008000 0 0 0
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# For more information about the configuration files, take a look at:
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# openocd.texi
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@@ -54,7 +54,8 @@ proc srst_deasserted {} { puts "Sensed nSRST deasserted. No action." }
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# boots from NOR on CS0: 8 MBytes CFI flash, 16-bit bus
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# it's really 16MB but the upper 8mb is controller via gpio
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# openocd does not support 'complex reads/writes' to NOR
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flash bank cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x20000000 0x01000000 2 2 $_TARGETNAME
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# writing data to memory does not work without this
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memwrite burst disable
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@@ -115,4 +115,5 @@ arm7_9 dcc_downloads enable # Enable faster DCC downloads
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#####################
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#flash bank cfi <base> <size> <chip width> <bus width> <target#>
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flash bank cfi 0x20000000 0x2000000 2 2 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x20000000 0x2000000 2 2 0
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@@ -121,5 +121,6 @@ arm7_9 dcc_downloads enable # Enable faster DCC downloads
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#####################
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#flash bank cfi <base> <size> <chip width> <bus width> <target#>
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flash bank cfi 0x20000000 0x1000000 2 2 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x20000000 0x1000000 2 2 0
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@@ -91,6 +91,7 @@ $_TARGETNAME configure -event reset-init {
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#####################
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#flash bank cfi <base> <size> <chip width> <bus width> <target#>
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flash bank cfi 0x10000000 0x01000000 2 2 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0x10000000 0x01000000 2 2 0
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@@ -8,7 +8,8 @@ $_TARGETNAME configure -event reset-init { x300t_init }
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# 1MB CFI capable flash
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# flash bank <driver> <base> <size> <chip_width> <bus_width>
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flash bank cfi 0xac000000 0x100000 2 2 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME cfi 0xac000000 0x100000 2 2 0
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proc x300t_init { } {
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# Setup SDRAM config and flash mapping
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@@ -38,7 +38,8 @@ target create $_TARGETNAME arm7tdmi -endian $_ENDIAN -chain-position $_TARGETNAM
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arm7_9 fast_memory_access enable
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arm7_9 dcc_downloads enable
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flash bank ecosflash 0x01000000 0x200000 2 2 $_TARGETNAME ecos/at91eb40a.elf
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME ecosflash 0x01000000 0x200000 2 2 $_TARGETNAME ecos/at91eb40a.elf
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$_TARGETNAME configure -event reset-init {
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# Set up chip selects & timings
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mww 0xFFE00000 0x0100273D
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@@ -35,7 +35,8 @@ $_TARGETNAME configure -work-area-phys 0x10000 -work-area-size 0x2000
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## flash configuration
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# only target number is needed
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flash bank aduc702x 0 0 0 0 0
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME aduc702x 0 0 0 0 0
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## If you use the watchdog, the following code makes sure that the board
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## doesn't reboot when halted via JTAG. Yes, on the older generation
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@@ -42,7 +42,8 @@ arm7_9 fast_memory_access enable
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arm7_9 dcc_downloads enable
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#flash driver
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flash bank ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
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set _FLASHNAME $_CHIPNAME.flash
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flash bank $_FLASHNAME ecosflash 0x01000000 0x200000 2 2 0 ecos/at91eb40a.elf
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# required for usable performance. Used for lots of
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# other things than flash programming.
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