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target: aarch64: access reg SPSR_EL2 only in EL2 and EL3
The register SPSR_EL2 is accessible and it's content is relevant
only when the target is in EL2 or EL3.
Virtualization SW in EL1 can also access it, but this either
triggers a trap to EL2 or returns SPSR_EL1. Debugger should not
mix the real SPSR_EL2 with the virtual register.
Plus, the register is 64 bits wide.
Without this patch, an error:
Error: Opcode 0xd53c4000, DSCR.ERR=1, DSCR.EL=1
is triggered by GDB register window or through GDB command
x/p $SPSR_EL2
or through OpenOCD command
reg SPSR_EL2
Detect the EL and return error if the register cannot be accessed.
Handle the register as 64 bits.
Change-Id: If3792296b36282c08d597dd46cfe044d6b8288ea
Signed-off-by: Antonio Borneo <borneo.antonio@gmail.com>
Reviewed-on: https://review.openocd.org/c/openocd/+/8273
Tested-by: jenkins
This commit is contained in:
@@ -365,9 +365,13 @@ static int armv8_read_reg(struct armv8_common *armv8, int regnum, uint64_t *regv
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value_64 = value;
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break;
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case ARMV8_SPSR_EL2:
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retval = dpm->instr_read_data_r0(dpm,
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ARMV8_MRS(SYSTEM_SPSR_EL2, 0), &value);
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value_64 = value;
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if (curel < SYSTEM_CUREL_EL2) {
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LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel);
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retval = ERROR_FAIL;
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break;
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}
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retval = dpm->instr_read_data_r0_64(dpm,
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ARMV8_MRS(SYSTEM_SPSR_EL2, 0), &value_64);
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break;
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case ARMV8_SPSR_EL3:
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if (curel < SYSTEM_CUREL_EL3) {
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@@ -509,9 +513,13 @@ static int armv8_write_reg(struct armv8_common *armv8, int regnum, uint64_t valu
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ARMV8_MSR_GP(SYSTEM_SPSR_EL1, 0), value);
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break;
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case ARMV8_SPSR_EL2:
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value = value_64;
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retval = dpm->instr_write_data_r0(dpm,
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ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value);
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if (curel < SYSTEM_CUREL_EL2) {
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LOG_DEBUG("SPSR_EL2 not accessible in EL%u", curel);
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retval = ERROR_FAIL;
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break;
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}
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retval = dpm->instr_write_data_r0_64(dpm,
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ARMV8_MSR_GP(SYSTEM_SPSR_EL2, 0), value_64);
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break;
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case ARMV8_SPSR_EL3:
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if (curel < SYSTEM_CUREL_EL3) {
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@@ -1563,7 +1571,7 @@ static const struct {
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NULL},
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{ ARMV8_ESR_EL2, "ESR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
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NULL},
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{ ARMV8_SPSR_EL2, "SPSR_EL2", 32, ARMV8_64_EL2H, REG_TYPE_UINT32, "banked", "net.sourceforge.openocd.banked",
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{ ARMV8_SPSR_EL2, "SPSR_EL2", 64, ARMV8_64_EL2H, REG_TYPE_UINT64, "banked", "net.sourceforge.openocd.banked",
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NULL},
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{ ARMV8_ELR_EL3, "ELR_EL3", 64, ARMV8_64_EL3H, REG_TYPE_CODE_PTR, "banked", "net.sourceforge.openocd.banked",
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