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target: add Espressif ESP32-S3 basic support

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ESP32-S3 is a dual core Xtensa SoC
Not full featured yet. Some of the missing functionality:
-Semihosting
-Flash breakpoints
-Flash loader
-Apptrace
-FreeRTOS

Signed-off-by: Erhan Kurubas <erhan.kurubas@espressif.com>
Change-Id: I44e17088030c96a9be9809f6579a4f16dbfc5794
Reviewed-on: https://review.openocd.org/c/openocd/+/6990
Tested-by: jenkins
Reviewed-by: Ian Thompson <ianst@cadence.com>
Reviewed-by: Antonio Borneo <borneo.antonio@gmail.com>
This commit is contained in:
Erhan Kurubas
2022-05-22 23:17:48 +02:00
committed by Antonio Borneo
parent 77287b8d47
commit 2053120ba1
10 changed files with 1035 additions and 2 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
contrib/loaders/reset/espressif/esp32s3/Makefile Normal file
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@@ -0,0 +1,31 @@
# ESP32 Makefile to compile the SoC reset program
# Copyright (C) 2022 Espressif Systems Ltd.
#
# This program is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation; either version 2 of the License, or
# (at your option) any later version.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/>
# Prefix for ESP32 cross compilers (can include a directory path)
CROSS ?= xtensa-esp32s3-elf-
APP_ARCH := xtensa
APP_CHIP := ESP32S3
APP_CHIP_PATH := $(shell pwd)
SRCS := $(APP_CHIP_PATH)/esp32s3_cpu_reset_handler.S
CFLAGS :=
LDFLAGS :=
INCLUDES :=
DEFINES :=
include ../common.mk

17
contrib/loaders/reset/espressif/esp32s3/cpu_reset_handler_code.inc Normal file
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@@ -0,0 +1,17 @@
/* Autogenerated with ../../../../../src/helper/bin2char.sh */
0x06,0x23,0x00,0x00,0x06,0x18,0x00,0x00,0x38,0x80,0x00,0x60,0xc0,0x80,0x00,0x60,
0xc4,0x80,0x00,0x60,0x90,0x80,0x00,0x60,0x74,0x80,0x00,0x60,0x18,0x32,0x58,0x01,
0x00,0xa0,0x00,0x9c,0x00,0x80,0x00,0x60,0xa1,0x3a,0xd8,0x50,0xac,0x80,0x00,0x60,
0x64,0xf0,0x01,0x60,0x64,0x00,0x02,0x60,0x94,0x80,0x00,0x60,0x48,0xf0,0x01,0x60,
0x48,0x00,0x02,0x60,0xb4,0x80,0x00,0x60,0x2a,0x31,0x1d,0x8f,0xb0,0x80,0x00,0x60,
0x00,0x00,0xb0,0x84,0x04,0x00,0x0c,0x60,0x00,0x00,0x0c,0x60,0x00,0x00,0x0c,0x60,
0x38,0x80,0x00,0x60,0x00,0x30,0x00,0x00,0x50,0x55,0x30,0x41,0xe7,0xff,0x59,0x04,
0x41,0xe7,0xff,0x59,0x04,0x41,0xe6,0xff,0x59,0x04,0x41,0xe6,0xff,0x59,0x04,0x41,
0xe6,0xff,0x31,0xe6,0xff,0x39,0x04,0x31,0xe6,0xff,0x41,0xe6,0xff,0x39,0x04,0x00,
0x60,0xeb,0x03,0x60,0x61,0x04,0x56,0x26,0x05,0x50,0x55,0x30,0x31,0xe3,0xff,0x41,
0xe3,0xff,0x39,0x04,0x41,0xe3,0xff,0x39,0x04,0x41,0xe2,0xff,0x39,0x04,0x41,0xe2,
0xff,0x59,0x04,0x41,0xe2,0xff,0x59,0x04,0x41,0xe2,0xff,0x59,0x04,0x41,0xe1,0xff,
0x31,0xe2,0xff,0x39,0x04,0x41,0xe1,0xff,0x31,0xe2,0xff,0x39,0x04,0x41,0xe1,0xff,
0x59,0x04,0x41,0xe1,0xff,0x0c,0x23,0x39,0x04,0x41,0xe0,0xff,0x0c,0x43,0x39,0x04,
0x52,0x64,0x00,0x41,0xdf,0xff,0x31,0xdf,0xff,0x32,0x64,0x00,0x00,0x70,0x00,0x46,
0xfe,0xff,

152
contrib/loaders/reset/espressif/esp32s3/esp32s3_cpu_reset_handler.S Normal file
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@@ -0,0 +1,152 @@
/***************************************************************************
* Reset stub used by esp32s3 target *
* Copyright (C) 2020 Espressif Systems (Shanghai) Co. Ltd. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#define RTC_CNTL_RESET_STATE_REG 0x60008038
#define RTC_CNTL_RESET_STATE_DEF 0x3000
#define RTC_CNTL_CLK_CONF_REG 0x60008074
#define RTC_CNTL_CLK_CONF_DEF 0x1583218
#define RTC_CNTL_STORE4_REG 0x600080C0
#define RTC_CNTL_STORE5_REG 0x600080C4
#define WDT_WKEY_VALUE 0x50D83AA1
#define TIMG0_WDTWPROTECT_REG 0x6001F064
#define TIMG0_WDTCONFIG0_REG 0x6001F048
#define TIMG1_WDTWPROTECT_REG 0x60020064
#define TIMG1_WDTCONFIG0_REG 0x60020048
#define RTC_CNTL_WDTCONFIG0_REG 0x60008094
#define RTC_CNTL_WDTWPROTECT_REG 0x600080AC
#define RTC_CNTL_OPTIONS0_REG 0x60008000
#define RTC_CNTL_OPTIONS0_DEF 0x1C00A000
#define RTC_CNTL_SW_SYS_RST 0x80000000
#define RTC_CNTL_DIG_PWC_REG 0x60008090
#define RTC_CNTL_SWD_CONF_REG 0x600080B0
#define RTC_CNTL_SWD_CONF_VAL 0x84B00000
#define RTC_CNTL_SWD_WPROTECT_REG 0x600080B4
#define RTC_CNTL_SWD_WKEY_VALUE 0x8F1D312A
#define SYSTEM_CORE_1_CONTROL_0_REG 0x600C0000
#define SYSTEM_CONTROL_CORE_1_RESETING 0x4
#define SYSTEM_CONTROL_CORE_1_CLKGATE_EN 0x2
#define SYSTEM_CORE_1_CONTROL_1_REG 0x600C0004
/* This stub is copied to RTC_SLOW_MEM by OpenOCD, and the CPU starts executing
* it instead of the ROM code (0x40000400). This stub disables watchdogs and
* goes into a loop.
* OpenOCD will then halt the target and perform CPU reset using OCD.
*/
/* Has to be at offset 0. This is the entry point of the CPU, once
* RTC_CNTL_PROCPU_STAT_VECTOR_SEL is cleared.
* CPU will come here after the system reset, triggered by RTC_CNTL_SW_SYS_RST.
*/
.global cpu_at_start_handler
.type cpu_at_start_handler,@function
.align 4
cpu_at_start_handler:
j start
/* Has to be at offset 4. Once the stub code has been uploaded into RTC Slow
* memory, OpenOCD will set the PC to this address, and resume execution.
* The stub will then jump to 'reset' label and perform the reset.
*/
.global cpu_reset_handler
.type cpu_reset_handler,@function
.align 4
cpu_reset_handler:
j reset
.align 4
.literal_position
.align 4
reset:
/* Use a5 as a zero register */
xor a5, a5, a5
/* Select static reset vector 0 (XCHAL_RESET_VECTOR0_VADDR, 0x50000000) */
movi a4, RTC_CNTL_RESET_STATE_REG
s32i a5, a4, 0
/* Set some clock-related RTC registers to the default values */
movi a4, RTC_CNTL_STORE4_REG
s32i a5, a4, 0
movi a4, RTC_CNTL_STORE5_REG
s32i a5, a4, 0
movi a4, RTC_CNTL_DIG_PWC_REG
s32i a5, a4, 0
movi a4, RTC_CNTL_CLK_CONF_REG
movi a3, RTC_CNTL_CLK_CONF_DEF
s32i a3, a4, 0
/* Reset the digital part of the chip (RTC controller doesn't get reset) */
movi a3, (RTC_CNTL_OPTIONS0_DEF | RTC_CNTL_SW_SYS_RST)
movi a4, RTC_CNTL_OPTIONS0_REG
s32i a3, a4, 0
/* Doesn't reach beyond this instruction */
.align 4
start:
/* If running on the APP CPU, skip directly to the parking loop */
rsr.prid a6
extui a6, a6, 1, 1
bnez a6, parking_loop
/* Use a5 as a zero register */
xor a5, a5, a5
/* Disable the watchdogs */
movi a3, WDT_WKEY_VALUE
movi a4, RTC_CNTL_WDTWPROTECT_REG
s32i.n a3, a4, 0
movi a4, TIMG0_WDTWPROTECT_REG
s32i.n a3, a4, 0
movi a4, TIMG1_WDTWPROTECT_REG
s32i.n a3, a4, 0
movi a4, RTC_CNTL_WDTCONFIG0_REG
s32i.n a5, a4, 0
movi a4, TIMG0_WDTCONFIG0_REG
s32i.n a5, a4, 0
movi a4, TIMG1_WDTCONFIG0_REG
s32i.n a5, a4, 0
movi a4, RTC_CNTL_SWD_WPROTECT_REG
movi a3, RTC_CNTL_SWD_WKEY_VALUE
s32i.n a3, a4, 0
movi a4, RTC_CNTL_SWD_CONF_REG
movi a3, RTC_CNTL_SWD_CONF_VAL
s32i.n a3, a4, 0
/* Clear APP_CPU boot address */
movi a4, SYSTEM_CORE_1_CONTROL_1_REG
s32i.n a5, a4, 0
/* Clear APP_CPU clock gating */
movi a4, SYSTEM_CORE_1_CONTROL_0_REG
movi a3, SYSTEM_CONTROL_CORE_1_CLKGATE_EN
s32i.n a3, a4, 0
/* Set and clear APP_CPU reset */
movi a4, SYSTEM_CORE_1_CONTROL_0_REG
movi a3, SYSTEM_CONTROL_CORE_1_RESETING
s32i.n a3, a4, 0
s32i.n a5, a4, 0
/* Restore the reset vector to ROM */
movi a4, RTC_CNTL_RESET_STATE_REG
movi a3, RTC_CNTL_RESET_STATE_DEF
s32i.n a3, a4, 0
parking_loop:
/* PRO and APP CPU will be in this loop, until OpenOCD
* finds the JTAG taps and puts the CPUs into debug mode.
*/
waiti 0
j parking_loop

1
doc/openocd.texi
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@@ -4915,6 +4915,7 @@ compact Thumb2 instruction set. Supports also ARMv6-M and ARMv8-M cores
The current implementation supports eSi-32xx cores.
@item @code{esp32} -- this is an Espressif SoC with dual Xtensa cores.
@item @code{esp32s2} -- this is an Espressif SoC with single Xtensa core.
@item @code{esp32s3} -- this is an Espressif SoC with dual Xtensa cores.
@item @code{fa526} -- resembles arm920 (w/o Thumb).
@item @code{feroceon} -- resembles arm926.
@item @code{hla_target} -- a Cortex-M alternative to work with HL adapters like ST-Link.

6
src/target/espressif/Makefile.am
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@@ -4,7 +4,9 @@ noinst_LTLIBRARIES += %D%/libespressif.la
%D%/esp_xtensa.h \
%D%/esp_xtensa_smp.c \
%D%/esp_xtensa_smp.h \
%D%/esp32.c \
%D%/esp32.h \
%D%/esp32s2.c \
%D%/esp32s2.h \
%D%/esp32.c \
%D%/esp32.h
%D%/esp32s3.c \
%D%/esp32s3.h

659
src/target/espressif/esp32s3.c Normal file
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File diff suppressed because it is too large Load Diff

65
src/target/espressif/esp32s3.h Normal file
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@@ -0,0 +1,65 @@
/***************************************************************************
* ESP32-S3 target for OpenOCD *
* Copyright (C) 2020 Espressif Systems Ltd. *
* *
* This program is free software; you can redistribute it and/or modify *
* it under the terms of the GNU General Public License as published by *
* the Free Software Foundation; either version 2 of the License, or *
* (at your option) any later version. *
* *
* This program is distributed in the hope that it will be useful, *
* but WITHOUT ANY WARRANTY; without even the implied warranty of *
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the *
* GNU General Public License for more details. *
* *
* You should have received a copy of the GNU General Public License *
* along with this program. If not, see <http://www.gnu.org/licenses/>. *
***************************************************************************/
#ifndef OPENOCD_TARGET_ESP32S3_H
#define OPENOCD_TARGET_ESP32S3_H
#include <target/xtensa/xtensa_regs.h>
#define ESP32_S3_DROM_LOW 0x3C000000
#define ESP32_S3_DROM_HIGH 0x3D000000
#define ESP32_S3_IROM_LOW 0x42000000
#define ESP32_S3_IROM_HIGH 0x44000000
/*Number of registers returned directly by the G command
*Corresponds to the amount of regs listed in regformats/reg-xtensa.dat in the gdb source */
#define ESP32_S3_NUM_REGS_G_COMMAND 128
enum esp32s3_reg_id {
/* chip specific registers that extend ISA go after ISA-defined ones */
ESP32_S3_REG_IDX_GPIOOUT = XT_NUM_REGS,
ESP32_S3_REG_IDX_ACCX_0,
ESP32_S3_REG_IDX_ACCX_1,
ESP32_S3_REG_IDX_QACC_H_0,
ESP32_S3_REG_IDX_QACC_H_1,
ESP32_S3_REG_IDX_QACC_H_2,
ESP32_S3_REG_IDX_QACC_H_3,
ESP32_S3_REG_IDX_QACC_H_4,
ESP32_S3_REG_IDX_QACC_L_0,
ESP32_S3_REG_IDX_QACC_L_1,
ESP32_S3_REG_IDX_QACC_L_2,
ESP32_S3_REG_IDX_QACC_L_3,
ESP32_S3_REG_IDX_QACC_L_4,
ESP32_S3_REG_IDX_SAR_BYTE,
ESP32_S3_REG_IDX_FFT_BIT_WIDTH,
ESP32_S3_REG_IDX_UA_STATE_0,
ESP32_S3_REG_IDX_UA_STATE_1,
ESP32_S3_REG_IDX_UA_STATE_2,
ESP32_S3_REG_IDX_UA_STATE_3,
ESP32_S3_REG_IDX_Q0,
ESP32_S3_REG_IDX_Q1,
ESP32_S3_REG_IDX_Q2,
ESP32_S3_REG_IDX_Q3,
ESP32_S3_REG_IDX_Q4,
ESP32_S3_REG_IDX_Q5,
ESP32_S3_REG_IDX_Q6,
ESP32_S3_REG_IDX_Q7,
ESP32_S3_NUM_REGS,
};
#endif /* OPENOCD_TARGET_ESP32S3_H */

2
src/target/target.c
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@@ -107,6 +107,7 @@ extern struct target_type nds32_v3_target;
extern struct target_type nds32_v3m_target;
extern struct target_type esp32_target;
extern struct target_type esp32s2_target;
extern struct target_type esp32s3_target;
extern struct target_type or1k_target;
extern struct target_type quark_x10xx_target;
extern struct target_type quark_d20xx_target;
@@ -145,6 +146,7 @@ static struct target_type *target_types[] = {
&nds32_v3m_target,
&esp32_target,
&esp32s2_target,
&esp32s3_target,
&or1k_target,
&quark_x10xx_target,
&quark_d20xx_target,

21
tcl/board/esp32s3-ftdi.cfg Normal file
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@@ -0,0 +1,21 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# Example OpenOCD configuration file for ESP32-S3 connected via ESP-Prog.
#
# For example, OpenOCD can be started for ESP32-S3 debugging on
#
# openocd -f board/esp32s3-ftdi.cfg
#
# Source the JTAG interface configuration file
source [find interface/ftdi/esp32_devkitj_v1.cfg]
# Source the ESP32-S3 configuration file
source [find target/esp32s3.cfg]
# The speed of the JTAG interface, in kHz. If you get DSR/DIR errors (and they
# do not relate to OpenOCD trying to read from a memory range without physical
# memory being present there), you can try lowering this.
#
# On DevKit-J, this can go as high as 20MHz if CPU frequency is 80MHz, or 26MHz
# if CPU frequency is 160MHz or 240MHz.
adapter speed 20000

83
tcl/target/esp32s3.cfg Normal file
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@@ -0,0 +1,83 @@
# SPDX-License-Identifier: GPL-2.0-or-later
#
# The ESP32-S3 only supports JTAG.
transport select jtag
set CPU_MAX_ADDRESS 0xFFFFFFFF
source [find bitsbytes.tcl]
source [find memory.tcl]
source [find mmr_helpers.tcl]
if { [info exists CHIPNAME] } {
set _CHIPNAME $CHIPNAME
} else {
set _CHIPNAME esp32s3
}
if { [info exists CPUTAPID] } {
set _CPUTAPID $CPUTAPID
} else {
set _CPUTAPID 0x120034e5
}
if { [info exists ESP32_S3_ONLYCPU] } {
set _ONLYCPU $ESP32_S3_ONLYCPU
} else {
set _ONLYCPU 2
}
set _CPU0NAME cpu0
set _CPU1NAME cpu1
set _TARGETNAME_0 $_CHIPNAME.$_CPU0NAME
set _TARGETNAME_1 $_CHIPNAME.$_CPU1NAME
jtag newtap $_CHIPNAME $_CPU0NAME -irlen 5 -expected-id $_CPUTAPID
if { $_ONLYCPU != 1 } {
jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -expected-id $_CPUTAPID
} else {
jtag newtap $_CHIPNAME $_CPU1NAME -irlen 5 -disable -expected-id $_CPUTAPID
}
proc esp32s3_memprot_is_enabled { } {
# TODO: after https://review.openocd.org/c/openocd/+/7016 merged
return 0
}
# PRO-CPU
target create $_TARGETNAME_0 $_CHIPNAME -endian little -chain-position $_TARGETNAME_0 -coreid 0
# APP-CPU
if { $_ONLYCPU != 1 } {
target create $_TARGETNAME_1 $_CHIPNAME -endian little -chain-position $_TARGETNAME_1 -coreid 1
target smp $_TARGETNAME_0 $_TARGETNAME_1
}
$_TARGETNAME_0 xtensa maskisr on
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
$_TARGETNAME_0 configure -event gdb-attach {
$_TARGETNAME_0 xtensa smpbreak BreakIn BreakOut
# necessary to auto-probe flash bank when GDB is connected
halt 1000
if { [esp32s3_memprot_is_enabled] } {
# 'reset halt' to disable memory protection and allow flasher to work correctly
echo "Memory protection is enabled. Reset target to disable it..."
reset halt
}
}
$_TARGETNAME_0 configure -event reset-assert-post { soft_reset_halt }
if { $_ONLYCPU != 1 } {
$_TARGETNAME_1 configure -event gdb-attach {
$_TARGETNAME_1 xtensa smpbreak BreakIn BreakOut
# necessary to auto-probe flash bank when GDB is connected
halt 1000
if { [esp32s3_memprot_is_enabled] } {
# 'reset halt' to disable memory protection and allow flasher to work correctly
echo "Memory protection is enabled. Reset target to disable it..."
reset halt
}
}
$_TARGETNAME_1 configure -event reset-assert-post { soft_reset_halt }
}
gdb_breakpoint_override hard