armv7a ,cortex a : add L1, L2 cache support, va to pa support

src/target/arm_dpm.c

@@ -109,7 +109,7 @@ static int dpm_mcr(struct target *target, int cpnum,
 /* Toggles between recorded core mode (USR, SVC, etc) and a temporary one.
  * Routines *must* restore the original mode before returning!!
  */
-static int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
+int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode)
 {
 	int retval;
 	uint32_t cpsr;

src/target/arm_dpm.h

@@ -133,6 +133,9 @@ int arm_dpm_setup(struct arm_dpm *dpm);
 int arm_dpm_initialize(struct arm_dpm *dpm);
 
 int arm_dpm_read_current_registers(struct arm_dpm *);
+int dpm_modeswitch(struct arm_dpm *dpm, enum arm_mode mode);
+
+
 int arm_dpm_write_dirty_registers(struct arm_dpm *, bool bpwp);
 
 void arm_dpm_report_wfar(struct arm_dpm *, uint32_t wfar);

src/target/armv7a.h

@@ -43,6 +43,56 @@ enum
 #define V2POWPW  5
 #define V2POWUR  6
 #define V2POWUW  7
+/*   L210/L220 cache controller support */
+struct armv7a_l2x_cache {
+	uint32_t base;
+	uint32_t way;
+};
+
+struct armv7a_cachesize
+{
+	uint32_t level_num;
+	/*  cache dimensionning */
+	uint32_t linelen;
+	uint32_t associativity;
+	uint32_t nsets;
+	uint32_t cachesize;
+	/* info for set way operation on cache */
+	uint32_t index;
+	uint32_t index_shift;
+	uint32_t way;
+	uint32_t way_shift;
+};
+
+
+struct armv7a_cache_common
+{
+	int ctype;
+	struct armv7a_cachesize d_u_size;	/* data cache */
+	struct armv7a_cachesize i_size;     /* instruction cache */
+	int i_cache_enabled;
+	int d_u_cache_enabled;
+	/* l2 external unified cache if some */
+	void *l2_cache;
+	int  (*flush_all_data_cache)(struct target *target);
+	int  (*display_cache_info)(struct command_context *cmd_ctx,
+			struct armv7a_cache_common *armv7a_cache);
+};
+
+
+struct armv7a_mmu_common
+{
+	/*  following field mmu working way */
+	int32_t ttbr1_used; /*  -1 not initialized, 0 no ttbr1 1 ttbr1 used and  */
+	uint32_t ttbr0_mask;/*  masked to be used  */
+	uint32_t os_border;
+
+	int (*read_physical_memory)(struct target *target, uint32_t address, uint32_t size, uint32_t count, uint8_t *buffer);
+	struct armv7a_cache_common armv7a_cache;
+	uint32_t mmu_enabled;
+};
+
+
 
 struct armv7a_common
 {
@@ -57,9 +107,13 @@ struct armv7a_common
 	uint32_t debug_base;
 	uint8_t debug_ap;
 	uint8_t memory_ap;
+	/* mdir */
+	uint8_t multi_processor_system;
+	uint8_t cluster_id;
+	uint8_t cpu_id;
 
-	/* Cache and Memory Management Unit */
-	struct armv4_5_mmu_common armv4_5_mmu;
+	/* cache specific to V7 Memory Management Unit compatible with v4_5*/
+	struct armv7a_mmu_common armv7a_mmu;
 
 	int (*examine_debug_reason)(struct target *target);
 	int (*post_debug_entry)(struct target *target);
@@ -112,9 +166,16 @@ target_to_armv7a(struct target *target)
 #define CPUDBG_AUTHSTATUS	0xFB8
 
 int armv7a_arch_state(struct target *target);
+int armv7a_identify_cache(struct target *target);
 struct reg_cache *armv7a_build_reg_cache(struct target *target,
 		struct armv7a_common *armv7a_common);
 int armv7a_init_arch_info(struct target *target, struct armv7a_common *armv7a);
+int armv7a_mmu_translate_va_pa(struct target *target, uint32_t va,
+		uint32_t *val,int meminfo);
+int armv7a_mmu_translate_va(struct target *target,  uint32_t va, uint32_t *val);
+
+int armv7a_handle_cache_info_command(struct command_context *cmd_ctx,
+		struct armv7a_cache_common *armv7a_cache);
 
 extern const struct command_registration armv7a_command_handlers[];
 

src/target/cortex_a.h

@@ -63,6 +63,10 @@ struct cortex_a8_common
 
 	/* Saved cp15 registers */
 	uint32_t cp15_control_reg;
+	/* latest cp15 register value written and cpsr processor mode */
+	uint32_t cp15_control_reg_curr;
+    enum arm_mode curr_mode;
+
 
 	/* Breakpoint register pairs */
 	int brp_num_context;
@@ -73,10 +77,8 @@ struct cortex_a8_common
 	/* Use cortex_a8_read_regs_through_mem for fast register reads */
 	int fast_reg_read;
 
-	/* Flag that helps to resolve what ttb to use: user or kernel */
-	int current_address_mode;
-
 	struct armv7a_common armv7a_common;
+
 };
 
 static inline struct cortex_a8_common *