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Bjorn AnderssonandKonrad Dybcio
a5cc102905
While the introduction of the v8 programming sequence brought functional
eDP support for the 4-lane 8.1Gbps case, it doesn't entirely match the
documented sequences from the programming guide. Further 5.4Gbps,
2.7Gbps and 1.62Gbps, and 2-lane support are both incorrect and
non-functional.
Update the v8 eDP PHY programming sequence to match the programming
sequence validated on Glymur.
This changes the v8-specific parts of the power-on flow:
- AUX configuration:
- update the default v8 AUX config
- program AUX_CFG2 based on link rate
- TX lane configuration:
- add v8 TX lane register programming before PLL enable
- program interface select based on link rate
- use separate 2-lane and 4-lane post-PLL lane enable programming
- PCS configuration:
- add v8 PCS/LDO/AUX-less timing programming
- program LFPS/AUX-less timing based on link rate
- PLL and SSC programming:
- update v8 SSC step values per link rate
- make LOCK_CMP_EN, CMN_CONFIG_1, CORECLK_DIV_MODE0, CORE_CLK_EN and
VCO tune values link-rate specific
- DCC and TSYNC:
- disable DCC before the v8 power-on sequence
- run the v8 TSYNC sequence
- run DCC calibration after PLL lock
- Status polling:
- poll the v8 PHY status register instead of the older status offset
- LDO config:
- use the correct LDO configuration parameters for v8
With these changes the v8 PHY has been validated to lock at 1.62, 2.7,
5.4 and 8.1 Gbps, using both 2 and 4 lanes. Link training now suceeds on
4-lane 8.1Gbps and 2-lane 5.4Gbps.
Assisted-by: Codex:GPT-5.5
Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>