mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy.git
This commit is contained in:
Mark Brown
@@ -39,6 +39,7 @@ properties:
|
||||
- const: mediatek,mt2701-mipi-tx
|
||||
- const: mediatek,mt8173-mipi-tx
|
||||
- const: mediatek,mt8183-mipi-tx
|
||||
- const: mediatek,mt8196-mipi-tx
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
@@ -17,17 +17,21 @@ properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- enum:
|
||||
- qcom,ipq5210-qmp-gen3x1-pcie-phy
|
||||
- qcom,ipq6018-qmp-pcie-phy
|
||||
- qcom,ipq8074-qmp-gen3-pcie-phy
|
||||
- qcom,ipq8074-qmp-pcie-phy
|
||||
- qcom,ipq9574-qmp-gen3x1-pcie-phy
|
||||
- qcom,ipq9574-qmp-gen3x2-pcie-phy
|
||||
- qcom,ipq9650-qmp-gen3x1-pcie-phy
|
||||
- qcom,ipq9650-qmp-gen3x2-pcie-phy
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq5424-qmp-gen3x1-pcie-phy
|
||||
- const: qcom,ipq9574-qmp-gen3x1-pcie-phy
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,ipq5210-qmp-gen3x2-pcie-phy
|
||||
- qcom,ipq5424-qmp-gen3x2-pcie-phy
|
||||
- const: qcom,ipq9574-qmp-gen3x2-pcie-phy
|
||||
|
||||
@@ -61,6 +65,8 @@ properties:
|
||||
"#phy-cells":
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||||
const: 0
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|
||||
refgen-supply: true
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||||
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||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
@@ -72,6 +78,21 @@ required:
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||||
- clock-output-names
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||||
- "#phy-cells"
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||||
|
||||
allOf:
|
||||
- if:
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||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,ipq9650-qmp-gen3x1-pcie-phy
|
||||
- qcom,ipq9650-qmp-gen3x2-pcie-phy
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then:
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required:
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||||
- refgen-supply
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else:
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||||
properties:
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refgen-supply: false
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||||
|
||||
additionalProperties: false
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||||
|
||||
examples:
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||||
|
||||
@@ -18,6 +18,7 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,qcs615-qmp-usb3-dp-phy
|
||||
- qcom,shikra-qmp-usb3-dp-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
@@ -33,12 +34,15 @@ properties:
|
||||
- const: pipe
|
||||
|
||||
resets:
|
||||
maxItems: 2
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||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
reset-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: phy_phy
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||||
- const: dp_phy
|
||||
- const: phy
|
||||
|
||||
vdda-phy-supply: true
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||||
|
||||
@@ -63,6 +67,22 @@ properties:
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- description: offset of the PHY mode register
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description: Clamp and PHY mode register present in the TCSR
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|
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orientation-switch:
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description:
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Flag the PHY as possible handler of USB Type-C orientation switching
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type: boolean
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||||
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ports:
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$ref: /schemas/graph.yaml#/properties/ports
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properties:
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port@0:
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$ref: /schemas/graph.yaml#/properties/port
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description: Output endpoint of the PHY
|
||||
|
||||
port@1:
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||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Incoming endpoint from the USB controller
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
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||||
@@ -78,6 +98,33 @@ required:
|
||||
|
||||
additionalProperties: false
|
||||
|
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allOf:
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- if:
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||||
properties:
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compatible:
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contains:
|
||||
enum:
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- qcom,shikra-qmp-usb3-dp-phy
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then:
|
||||
properties:
|
||||
resets:
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||||
minItems: 3
|
||||
reset-names:
|
||||
minItems: 3
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,qcs615-qmp-usb3-dp-phy
|
||||
then:
|
||||
properties:
|
||||
resets:
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||||
maxItems: 2
|
||||
reset-names:
|
||||
maxItems: 2
|
||||
|
||||
examples:
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||||
- |
|
||||
#include <dt-bindings/clock/qcom,qcs615-gcc.h>
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|
||||
@@ -28,6 +28,7 @@ properties:
|
||||
- qcom,qcm2290-qusb2-phy
|
||||
- qcom,qcs615-qusb2-phy
|
||||
- qcom,sdm660-qusb2-phy
|
||||
- qcom,shikra-qusb2-phy
|
||||
- qcom,sm4250-qusb2-phy
|
||||
- qcom,sm6115-qusb2-phy
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||||
- items:
|
||||
|
||||
@@ -20,6 +20,8 @@ properties:
|
||||
- qcom,eliza-qmp-gen3x2-pcie-phy
|
||||
- qcom,glymur-qmp-gen4x2-pcie-phy
|
||||
- qcom,glymur-qmp-gen5x4-pcie-phy
|
||||
- qcom,hawi-qmp-gen3x2-pcie-phy
|
||||
- qcom,hawi-qmp-gen4x1-pcie-phy
|
||||
- qcom,kaanapali-qmp-gen3x2-pcie-phy
|
||||
- qcom,qcs615-qmp-gen3x1-pcie-phy
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||||
- qcom,qcs8300-qmp-gen4x2-pcie-phy
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||||
@@ -196,6 +198,8 @@ allOf:
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||||
- qcom,eliza-qmp-gen3x2-pcie-phy
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||||
- qcom,glymur-qmp-gen4x2-pcie-phy
|
||||
- qcom,glymur-qmp-gen5x4-pcie-phy
|
||||
- qcom,hawi-qmp-gen3x2-pcie-phy
|
||||
- qcom,hawi-qmp-gen4x1-pcie-phy
|
||||
- qcom,qcs8300-qmp-gen4x2-pcie-phy
|
||||
- qcom,sa8775p-qmp-gen4x2-pcie-phy
|
||||
- qcom,sa8775p-qmp-gen4x4-pcie-phy
|
||||
@@ -223,6 +227,8 @@ allOf:
|
||||
- qcom,eliza-qmp-gen3x2-pcie-phy
|
||||
- qcom,glymur-qmp-gen4x2-pcie-phy
|
||||
- qcom,glymur-qmp-gen5x4-pcie-phy
|
||||
- qcom,hawi-qmp-gen3x2-pcie-phy
|
||||
- qcom,hawi-qmp-gen4x1-pcie-phy
|
||||
- qcom,kaanapali-qmp-gen3x2-pcie-phy
|
||||
- qcom,sm8550-qmp-gen4x2-pcie-phy
|
||||
- qcom,sm8650-qmp-gen4x2-pcie-phy
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/spacemit,k3-combo-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Spacemit K3 PCIE/USB3 Comb PHY
|
||||
|
||||
maintainers:
|
||||
- Inochi Amaoto <inochiama@gmail.com>
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||||
|
||||
properties:
|
||||
compatible:
|
||||
const: spacemit,k3-combo-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 2
|
||||
description:
|
||||
The first one is phy id, the second one is phy type. This
|
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only supports types are PCIe and USB .
|
||||
|
||||
spacemit,apb-spare:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to APB SPARE system controller interface, used for
|
||||
PHY calibration.
|
||||
|
||||
spacemit,apmu:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle-array
|
||||
items:
|
||||
- items:
|
||||
- description: phandle of APMU syscon
|
||||
- description: configuration of the PHY lanes
|
||||
description: |
|
||||
Phandle to control PHY mux configuration. The configuration
|
||||
is described as follows:
|
||||
bit 4: 0 - PCIe A x8 mode, 1 - PCIe lane share mode
|
||||
bit 3: 0 - PCIe A x4 mode, 1 - PCIe A x2 and PCIe B x2 mode
|
||||
bit 2: 0 - PCIe C lane 0 is PCIe mode , 1 - USB mode
|
||||
bit 1: 0 - PCIe C lane 1 is PCIe mode , 1 - USB mode
|
||||
bit 0: 0 - PCIe D lane is PCIe mode , 1 - USB mode
|
||||
|
||||
The bit[3:0] is only valid when bit 4 is 1.
|
||||
|
||||
This mux control does not affect the PHY for PCIe E, it is always
|
||||
in PCIe mode.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#phy-cells"
|
||||
- spacemit,apb-spare
|
||||
- spacemit,apmu
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
phy@81d00000 {
|
||||
compatible = "spacemit,k3-combo-phy";
|
||||
reg = <0x81d00000 0x600000>;
|
||||
#phy-cells = <2>;
|
||||
spacemit,apb-spare = <&apb_spare>;
|
||||
spacemit,apmu = <&apmu 0x00>;
|
||||
};
|
||||
@@ -29879,6 +29879,7 @@ F: drivers/edac/zynqmp_edac.c
|
||||
|
||||
XILINX ZYNQMP PSGTR PHY DRIVER
|
||||
M: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com>
|
||||
M: Radhey Shyam Pandey <radhey.shyam.pandey@amd.com>
|
||||
L: linux-kernel@vger.kernel.org
|
||||
S: Supported
|
||||
T: git https://github.com/Xilinx/linux-xlnx.git
|
||||
|
||||
@@ -387,7 +387,7 @@ static void lynx_10g_backup_pccr_val(struct lynx_lane *lane)
|
||||
*/
|
||||
static bool lynx_10g_pccr_val_enabled(u32 pccr)
|
||||
{
|
||||
return FIELD_PREP(PCCR8_SGMIIa_CFG, pccr) != 0;
|
||||
return FIELD_GET(PCCR8_SGMIIa_CFG, pccr) != 0;
|
||||
}
|
||||
|
||||
static bool lynx_10g_lane_is_3_125g(struct lynx_lane *lane)
|
||||
|
||||
@@ -21,4 +21,5 @@ obj-$(CONFIG_PHY_MTK_MIPI_CSI_0_5) += phy-mtk-mipi-csi-0-5.o
|
||||
phy-mtk-mipi-dsi-drv-y := phy-mtk-mipi-dsi.o
|
||||
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8173.o
|
||||
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8183.o
|
||||
phy-mtk-mipi-dsi-drv-y += phy-mtk-mipi-dsi-mt8196.o
|
||||
obj-$(CONFIG_PHY_MTK_MIPI_DSI) += phy-mtk-mipi-dsi-drv.o
|
||||
|
||||
@@ -0,0 +1,201 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* Copyright (c) 2019 MediaTek Inc.
|
||||
* Author: jitao.shi <jitao.shi@mediatek.com>
|
||||
*
|
||||
* Copyright (c) 2026 Collabora Ltd.
|
||||
* AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
|
||||
*/
|
||||
|
||||
#include "phy-mtk-io.h"
|
||||
#include "phy-mtk-mipi-dsi.h"
|
||||
|
||||
#define MIPITX_LANE_CON 0x0004
|
||||
#define RG_DSI_CPHY_T1DRV_EN BIT(0)
|
||||
#define RG_DSI_ANA_CK_SEL BIT(1)
|
||||
#define RG_DSI_PHY_CK_SEL BIT(2)
|
||||
#define RG_DSI_CPHY_EN BIT(3)
|
||||
#define RG_DSI_PHYCK_INV_EN BIT(4)
|
||||
#define RG_DSI_PWR04_EN BIT(5)
|
||||
#define RG_DSI_BG_LPF_EN BIT(6)
|
||||
#define RG_DSI_BG_CORE_EN BIT(7)
|
||||
#define RG_DSI_PAD_TIEL_SEL BIT(8)
|
||||
|
||||
#define MIPITX_VOLTAGE_SEL 0x0008
|
||||
#define RG_DSI_HSTX_LDO_REF_SEL GENMASK(9, 6)
|
||||
#define RG_DSI_PRD_REF_SEL GENMASK(5, 0)
|
||||
#define RG_DSI_PRD_REF_MINI 0
|
||||
#define RG_DSI_PRD_REF_DEF 4
|
||||
#define RG_DSI_PRD_REF_MAX 7
|
||||
|
||||
#define MIPITX_PRESERVED 0x000c
|
||||
#define MIPITX_PRESERVED_DEF 0xffff0040
|
||||
#define MIPITX_PRESERVED_MINI 0xffff00f0
|
||||
|
||||
#define MIPITX_PLL_PWR 0x0028
|
||||
#define AD_DSI_PLL_SDM_PWR_ON BIT(0)
|
||||
#define AD_DSI_PLL_SDM_ISO_EN BIT(1)
|
||||
#define MIPITX_PLL_CON0 0x002c
|
||||
#define MIPITX_PLL_CON1 0x0030
|
||||
#define RG_DSI_PLL_EN BIT(0)
|
||||
#define RG_DSI_PLL_POSDIV GENMASK(10, 8)
|
||||
#define MIPITX_PLL_CON2 0x0034
|
||||
#define MIPITX_PLL_CON3 0x0038
|
||||
#define MIPITX_PLL_CON4 0x003c
|
||||
#define RG_DSI_PLL_IBIAS GENMASK(11, 10)
|
||||
|
||||
#define MIPITX_D2_SW_CTL_EN 0x015c
|
||||
#define MIPITX_D0_SW_CTL_EN 0x025c
|
||||
#define MIPITX_CK_CKMODE_EN 0x0320
|
||||
#define DSI_CK_CKMODE_EN BIT(0)
|
||||
#define MIPITX_CK_SW_CTL_EN 0x035c
|
||||
#define MIPITX_D1_SW_CTL_EN 0x045c
|
||||
#define MIPITX_D3_SW_CTL_EN 0x055c
|
||||
#define DSI_SW_CTL_EN BIT(0)
|
||||
|
||||
#define DSI_PHY_XTAL_CLK_HZ 26000000
|
||||
#define DSI_PHY_PLL_MIN_RATE_HZ 125000000
|
||||
#define DSI_PHY_PLL_MAX_RATE_HZ 2000000000
|
||||
|
||||
static int mtk_mipi_tx_pll_enable(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
|
||||
void __iomem *base = mipi_tx->regs;
|
||||
u32 voltage = RG_DSI_PRD_REF_MINI;
|
||||
u32 pres = MIPITX_PRESERVED_MINI;
|
||||
unsigned long long pcw_calc;
|
||||
unsigned int txdiv, txdiv0;
|
||||
u32 pcw;
|
||||
|
||||
dev_dbg(mipi_tx->dev, "enable: %u bps\n", mipi_tx->data_rate);
|
||||
|
||||
if (mipi_tx->data_rate >= DSI_PHY_PLL_MAX_RATE_HZ) {
|
||||
/* Select higher signaling voltage for fast data rates */
|
||||
voltage = RG_DSI_PRD_REF_DEF;
|
||||
pres = MIPITX_PRESERVED_DEF;
|
||||
txdiv = 1;
|
||||
txdiv0 = 0;
|
||||
} else if (mipi_tx->data_rate >= 1000000000) {
|
||||
txdiv = 2;
|
||||
txdiv0 = 1;
|
||||
} else if (mipi_tx->data_rate >= 500000000) {
|
||||
txdiv = 4;
|
||||
txdiv0 = 2;
|
||||
} else if (mipi_tx->data_rate > 250000000) {
|
||||
txdiv = 8;
|
||||
txdiv0 = 3;
|
||||
} else if (mipi_tx->data_rate >= 125000000) {
|
||||
txdiv = 16;
|
||||
txdiv0 = 4;
|
||||
} else {
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
pcw_calc = ((u64)(mipi_tx->data_rate / 2) * txdiv) << 24;
|
||||
pcw_calc = div_u64(pcw_calc, DSI_PHY_XTAL_CLK_HZ);
|
||||
|
||||
if (pcw_calc > U32_MAX) {
|
||||
dev_err(mipi_tx->dev, "Calculated PCW=%llu overflow!\n", pcw_calc);
|
||||
return -EINVAL;
|
||||
}
|
||||
pcw = (u32)pcw_calc;
|
||||
|
||||
mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_PRD_REF_SEL, voltage);
|
||||
writel(pres, base + MIPITX_PRESERVED);
|
||||
|
||||
/* Enable the SDM and wait for power to stabilize */
|
||||
mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
|
||||
mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
|
||||
udelay(30);
|
||||
|
||||
/* Disable isolation and program PLL's PCW and dividers */
|
||||
mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
|
||||
writel(pcw, base + MIPITX_PLL_CON0);
|
||||
mtk_phy_update_field(base + MIPITX_PLL_CON1, RG_DSI_PLL_POSDIV, txdiv0);
|
||||
|
||||
/* Enable the PLL and wait for the clock output to stabilize */
|
||||
mtk_phy_set_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
|
||||
udelay(30);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void mtk_mipi_tx_pll_disable(struct clk_hw *hw)
|
||||
{
|
||||
struct mtk_mipi_tx *mipi_tx = mtk_mipi_tx_from_clk_hw(hw);
|
||||
void __iomem *base = mipi_tx->regs;
|
||||
|
||||
mtk_phy_clear_bits(base + MIPITX_PLL_CON1, RG_DSI_PLL_EN);
|
||||
|
||||
mtk_phy_set_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_ISO_EN);
|
||||
mtk_phy_clear_bits(base + MIPITX_PLL_PWR, AD_DSI_PLL_SDM_PWR_ON);
|
||||
}
|
||||
|
||||
static int mtk_mipi_tx_pll_determine_rate(struct clk_hw *hw,
|
||||
struct clk_rate_request *req)
|
||||
{
|
||||
req->rate = clamp_val(req->rate,
|
||||
DSI_PHY_PLL_MIN_RATE_HZ, DSI_PHY_PLL_MAX_RATE_HZ);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct clk_ops mtk_mipi_tx_pll_ops = {
|
||||
.enable = mtk_mipi_tx_pll_enable,
|
||||
.disable = mtk_mipi_tx_pll_disable,
|
||||
.determine_rate = mtk_mipi_tx_pll_determine_rate,
|
||||
.set_rate = mtk_mipi_tx_pll_set_rate,
|
||||
.recalc_rate = mtk_mipi_tx_pll_recalc_rate,
|
||||
};
|
||||
|
||||
static void mtk_mipi_tx_power_on_signal(struct phy *phy)
|
||||
{
|
||||
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
|
||||
void __iomem *base = mipi_tx->regs;
|
||||
|
||||
/* BG_LPF_EN / BG_CORE_EN */
|
||||
writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
|
||||
/* Wait for MIPI core to enable */
|
||||
usleep_range(30, 100);
|
||||
writel(RG_DSI_BG_CORE_EN | RG_DSI_BG_LPF_EN, base + MIPITX_LANE_CON);
|
||||
|
||||
/* Switch OFF each Lane */
|
||||
mtk_phy_clear_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
|
||||
mtk_phy_clear_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
|
||||
mtk_phy_clear_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
|
||||
mtk_phy_clear_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
|
||||
mtk_phy_clear_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
|
||||
|
||||
/*
|
||||
* The MIPI TX drive strength is in the range of 3000 ~ 6000 microamps:
|
||||
* RG_DSI_HSTX_LDO_REF_SEL expresses an offset from the minimum drive
|
||||
* strength (3000uA) and can add a maximum offset of 3000uA, reaching a
|
||||
* maximum drive strength of 3000+3000=6000uA.
|
||||
*/
|
||||
mtk_phy_update_field(base + MIPITX_VOLTAGE_SEL, RG_DSI_HSTX_LDO_REF_SEL,
|
||||
(mipi_tx->mipitx_drive - 3000) / 200);
|
||||
|
||||
mtk_phy_set_bits(base + MIPITX_CK_CKMODE_EN, DSI_CK_CKMODE_EN);
|
||||
}
|
||||
|
||||
static void mtk_mipi_tx_power_off_signal(struct phy *phy)
|
||||
{
|
||||
struct mtk_mipi_tx *mipi_tx = phy_get_drvdata(phy);
|
||||
void __iomem *base = mipi_tx->regs;
|
||||
|
||||
/* Switch ON each lane one by one */
|
||||
mtk_phy_set_bits(base + MIPITX_D0_SW_CTL_EN, DSI_SW_CTL_EN);
|
||||
mtk_phy_set_bits(base + MIPITX_D1_SW_CTL_EN, DSI_SW_CTL_EN);
|
||||
mtk_phy_set_bits(base + MIPITX_D2_SW_CTL_EN, DSI_SW_CTL_EN);
|
||||
mtk_phy_set_bits(base + MIPITX_D3_SW_CTL_EN, DSI_SW_CTL_EN);
|
||||
mtk_phy_set_bits(base + MIPITX_CK_SW_CTL_EN, DSI_SW_CTL_EN);
|
||||
|
||||
writel(RG_DSI_PAD_TIEL_SEL | RG_DSI_BG_CORE_EN, base + MIPITX_LANE_CON);
|
||||
writel(RG_DSI_PAD_TIEL_SEL, base + MIPITX_LANE_CON);
|
||||
}
|
||||
|
||||
const struct mtk_mipitx_data mt8196_mipitx_data = {
|
||||
.mipi_tx_clk_ops = &mtk_mipi_tx_pll_ops,
|
||||
.mipi_tx_enable_signal = mtk_mipi_tx_power_on_signal,
|
||||
.mipi_tx_disable_signal = mtk_mipi_tx_power_off_signal,
|
||||
};
|
||||
@@ -183,6 +183,7 @@ static const struct of_device_id mtk_mipi_tx_match[] = {
|
||||
{ .compatible = "mediatek,mt2701-mipi-tx", .data = &mt2701_mipitx_data },
|
||||
{ .compatible = "mediatek,mt8173-mipi-tx", .data = &mt8173_mipitx_data },
|
||||
{ .compatible = "mediatek,mt8183-mipi-tx", .data = &mt8183_mipitx_data },
|
||||
{ .compatible = "mediatek,mt8196-mipi-tx", .data = &mt8196_mipitx_data },
|
||||
{ /* sentinel */ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, mtk_mipi_tx_match);
|
||||
|
||||
@@ -42,5 +42,5 @@ unsigned long mtk_mipi_tx_pll_recalc_rate(struct clk_hw *hw,
|
||||
extern const struct mtk_mipitx_data mt2701_mipitx_data;
|
||||
extern const struct mtk_mipitx_data mt8173_mipitx_data;
|
||||
extern const struct mtk_mipitx_data mt8183_mipitx_data;
|
||||
|
||||
extern const struct mtk_mipitx_data mt8196_mipitx_data;
|
||||
#endif
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,18 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V10_H_
|
||||
|
||||
/* Only for QMP V10 PHY - PCIE PCS registers */
|
||||
#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG2 0x00c
|
||||
#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG4 0x014
|
||||
#define QPHY_PCIE_V10_PCS_ENDPOINT_REFCLK_DRIVE 0x020
|
||||
#define QPHY_PCIE_V10_PCS_OSC_DTCT_ACTIONS 0x094
|
||||
#define QPHY_PCIE_V10_PCS_EQ_CONFIG1 0x0a4
|
||||
#define QPHY_PCIE_V10_PCS_RXEQEVAL_TIME 0x0f4
|
||||
#define QPHY_PCIE_V10_PCS_POWER_STATE_CONFIG6 0x0f8
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,26 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_PCIE_V10_60_H_
|
||||
#define QCOM_PHY_QMP_PCS_PCIE_V10_60_H_
|
||||
|
||||
/* Only for QMP V10_60 PHY - PCIE PCS registers */
|
||||
#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG2 0x00c
|
||||
#define QPHY_PCIE_V10_60_PCS_TX_RX_CONFIG 0x018
|
||||
#define QPHY_PCIE_V10_60_PCS_ENDPOINT_REFCLK_DRIVE 0x01c
|
||||
#define QPHY_PCIE_V10_60_PCS_OSC_DTCT_ACTIONS 0x090
|
||||
#define QPHY_PCIE_V10_60_PCS_EQ_CONFIG1 0x0a0
|
||||
#define QPHY_PCIE_V10_60_PCS_G3_RXEQEVAL_TIME 0x0f0
|
||||
#define QPHY_PCIE_V10_60_PCS_G4_RXEQEVAL_TIME 0x0f4
|
||||
#define QPHY_PCIE_V10_60_PCS_G4_EQ_CONFIG5 0x108
|
||||
#define QPHY_PCIE_V10_60_PCS_G4_PRE_GAIN 0x15c
|
||||
#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG1 0x17c
|
||||
#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG3 0x184
|
||||
#define QPHY_PCIE_V10_60_PCS_RX_MARGINING_CONFIG5 0x18c
|
||||
#define QPHY_PCIE_V10_60_PCS_G3_FOM_EQ_CONFIG5 0x1ac
|
||||
#define QPHY_PCIE_V10_60_PCS_G4_FOM_EQ_CONFIG5 0x1c0
|
||||
#define QPHY_PCIE_V10_60_PCS_POWER_STATE_CONFIG6 0x1d0
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,22 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_V10_H_
|
||||
#define QCOM_PHY_QMP_PCS_V10_H_
|
||||
|
||||
/* Only for QMP V10 PHY - PCIe PCS registers */
|
||||
#define QPHY_V10_PCS_SW_RESET 0x000
|
||||
#define QPHY_V10_PCS_PCS_STATUS1 0x014
|
||||
#define QPHY_V10_PCS_POWER_DOWN_CONTROL 0x040
|
||||
#define QPHY_V10_PCS_START_CONTROL 0x044
|
||||
#define QPHY_V10_PCS_REFGEN_REQ_CONFIG1 0x0dc
|
||||
#define QPHY_V10_PCS_G12S1_TXDEEMPH_M6DB 0x168
|
||||
#define QPHY_V10_PCS_G3S2_PRE_GAIN 0x170
|
||||
#define QPHY_V10_PCS_RX_SIGDET_LVL 0x188
|
||||
#define QPHY_V10_PCS_RATE_SLEW_CNTRL1 0x198
|
||||
#define QPHY_V10_PCS_PCS_TX_RX_CONFIG 0x1d0
|
||||
#define QPHY_V10_PCS_EQ_CONFIG2 0x1e4
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,23 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_PCS_V10_60_H_
|
||||
#define QCOM_PHY_QMP_PCS_V10_60_H_
|
||||
|
||||
/* Only for QMP V10_60 PHY - PCIe PCS registers */
|
||||
#define QPHY_V10_60_PCS_SW_RESET 0x000
|
||||
#define QPHY_V10_60_PCS_PCS_STATUS1 0x014
|
||||
#define QPHY_V10_60_PCS_POWER_DOWN_CONTROL 0x040
|
||||
#define QPHY_V10_60_PCS_START_CONTROL 0x044
|
||||
#define QPHY_V10_60_PCS_G12S1_TXDEEMPH_M6DB 0x170
|
||||
#define QPHY_V10_60_PCS_G3S2_PRE_GAIN 0x178
|
||||
#define QPHY_V10_60_PCS_RX_SIGDET_LVL 0x190
|
||||
#define QPHY_V10_60_PCS_ELECIDLE_DLY_SEL 0x1b8
|
||||
#define QPHY_V10_60_PCS_PCS_TX_RX_CONFIG1 0x1dc
|
||||
#define QPHY_V10_60_PCS_PCS_TX_RX_CONFIG2 0x1e0
|
||||
#define QPHY_V10_60_PCS_EQ_CONFIG4 0x1f8
|
||||
#define QPHY_V10_60_PCS_EQ_CONFIG5 0x1fc
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,49 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_COM_V10_H_
|
||||
|
||||
/* Only for QMP V10 PHY - QSERDES COM registers */
|
||||
#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE1 0x00
|
||||
#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE1 0x04
|
||||
#define QSERDES_V10_COM_CP_CTRL_MODE1 0x10
|
||||
#define QSERDES_V10_COM_PLL_RCTRL_MODE1 0x14
|
||||
#define QSERDES_V10_COM_PLL_CCTRL_MODE1 0x18
|
||||
#define QSERDES_V10_COM_CORECLK_DIV_MODE1 0x1c
|
||||
#define QSERDES_V10_COM_LOCK_CMP1_MODE1 0x20
|
||||
#define QSERDES_V10_COM_LOCK_CMP2_MODE1 0x24
|
||||
#define QSERDES_V10_COM_DEC_START_MODE1 0x28
|
||||
#define QSERDES_V10_COM_DIV_FRAC_START1_MODE1 0x30
|
||||
#define QSERDES_V10_COM_DIV_FRAC_START2_MODE1 0x34
|
||||
#define QSERDES_V10_COM_DIV_FRAC_START3_MODE1 0x38
|
||||
#define QSERDES_V10_COM_HSCLK_SEL_1 0x3c
|
||||
#define QSERDES_V10_COM_SSC_STEP_SIZE1_MODE0 0x60
|
||||
#define QSERDES_V10_COM_SSC_STEP_SIZE2_MODE0 0x64
|
||||
#define QSERDES_V10_COM_CP_CTRL_MODE0 0x70
|
||||
#define QSERDES_V10_COM_PLL_RCTRL_MODE0 0x74
|
||||
#define QSERDES_V10_COM_PLL_CCTRL_MODE0 0x78
|
||||
#define QSERDES_V10_COM_LOCK_CMP1_MODE0 0x80
|
||||
#define QSERDES_V10_COM_LOCK_CMP2_MODE0 0x84
|
||||
#define QSERDES_V10_COM_DEC_START_MODE0 0x88
|
||||
#define QSERDES_V10_COM_DIV_FRAC_START1_MODE0 0x90
|
||||
#define QSERDES_V10_COM_DIV_FRAC_START2_MODE0 0x94
|
||||
#define QSERDES_V10_COM_DIV_FRAC_START3_MODE0 0x98
|
||||
#define QSERDES_V10_COM_BG_TIMER 0xbc
|
||||
#define QSERDES_V10_COM_SSC_EN_CENTER 0xc0
|
||||
#define QSERDES_V10_COM_SSC_PER1 0xcc
|
||||
#define QSERDES_V10_COM_SSC_PER2 0xd0
|
||||
#define QSERDES_V10_COM_CLK_ENABLE1 0xe0
|
||||
#define QSERDES_V10_COM_SYS_CLK_CTRL 0xe4
|
||||
#define QSERDES_V10_COM_PLL_IVCO 0xf4
|
||||
#define QSERDES_V10_COM_SYSCLK_EN_SEL 0x110
|
||||
#define QSERDES_V10_COM_LOCK_CMP_EN 0x120
|
||||
#define QSERDES_V10_COM_VCO_TUNE_MAP 0x140
|
||||
#define QSERDES_V10_COM_CLK_SELECT 0x164
|
||||
#define QSERDES_V10_COM_CORE_CLK_EN 0x170
|
||||
#define QSERDES_V10_COM_CMN_CONFIG_1 0x174
|
||||
#define QSERDES_V10_COM_ADDITIONAL_MISC_3 0x1bc
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,55 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_COM_V10_60_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_COM_V10_60_H_
|
||||
|
||||
/* Only for QMP V10_60 PHY - QSERDES COM registers */
|
||||
#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE1 0x00
|
||||
#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE1 0x04
|
||||
#define QSERDES_V10_60_COM_CP_CTRL_MODE1 0x10
|
||||
#define QSERDES_V10_60_COM_PLL_RCTRL_MODE1 0x14
|
||||
#define QSERDES_V10_60_COM_PLL_CCTRL_MODE1 0x18
|
||||
#define QSERDES_V10_60_COM_CORECLK_DIV_MODE1 0x1c
|
||||
#define QSERDES_V10_60_COM_LOCK_CMP1_MODE1 0x20
|
||||
#define QSERDES_V10_60_COM_LOCK_CMP2_MODE1 0x24
|
||||
#define QSERDES_V10_60_COM_DEC_START_MODE1 0x28
|
||||
#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE1 0x30
|
||||
#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE1 0x34
|
||||
#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE1 0x38
|
||||
#define QSERDES_V10_60_COM_HSCLK_SEL_1 0x3c
|
||||
#define QSERDES_V10_60_COM_SSC_STEP_SIZE1_MODE0 0x60
|
||||
#define QSERDES_V10_60_COM_SSC_STEP_SIZE2_MODE0 0x64
|
||||
#define QSERDES_V10_60_COM_CP_CTRL_MODE0 0x70
|
||||
#define QSERDES_V10_60_COM_PLL_RCTRL_MODE0 0x74
|
||||
#define QSERDES_V10_60_COM_PLL_CCTRL_MODE0 0x78
|
||||
#define QSERDES_V10_60_COM_CORECLK_DIV_MODE0 0x7c
|
||||
#define QSERDES_V10_60_COM_LOCK_CMP1_MODE0 0x80
|
||||
#define QSERDES_V10_60_COM_LOCK_CMP2_MODE0 0x84
|
||||
#define QSERDES_V10_60_COM_DEC_START_MODE0 0x88
|
||||
#define QSERDES_V10_60_COM_DIV_FRAC_START1_MODE0 0x90
|
||||
#define QSERDES_V10_60_COM_DIV_FRAC_START2_MODE0 0x94
|
||||
#define QSERDES_V10_60_COM_DIV_FRAC_START3_MODE0 0x98
|
||||
#define QSERDES_V10_60_COM_HSCLK_HS_SWITCH_SEL_1 0x9c
|
||||
#define QSERDES_V10_60_COM_BG_TIMER 0xbc
|
||||
#define QSERDES_V10_60_COM_SSC_PER1 0xcc
|
||||
#define QSERDES_V10_60_COM_SSC_PER2 0xd0
|
||||
#define QSERDES_V10_60_COM_BIAS_EN_CLKBUFLR_EN 0xdc
|
||||
#define QSERDES_V10_60_COM_CLK_ENABLE1 0xe0
|
||||
#define QSERDES_V10_60_COM_SYS_CLK_CTRL 0xe4
|
||||
#define QSERDES_V10_60_COM_PLL_IVCO 0xf4
|
||||
#define QSERDES_V10_60_COM_SYSCLK_EN_SEL 0x110
|
||||
#define QSERDES_V10_60_COM_LOCK_CMP_EN 0x120
|
||||
#define QSERDES_V10_60_COM_LOCK_CMP_CFG 0x124
|
||||
#define QSERDES_V10_60_COM_VCO_TUNE_MAP 0x140
|
||||
#define QSERDES_V10_60_COM_CLK_SELECT 0x164
|
||||
#define QSERDES_V10_60_COM_CORE_CLK_EN 0x170
|
||||
#define QSERDES_V10_60_COM_CMN_CONFIG_1 0x174
|
||||
#define QSERDES_V10_60_COM_CMN_MISC1 0x184
|
||||
#define QSERDES_V10_60_COM_CMN_MODE 0x188
|
||||
#define QSERDES_V10_60_COM_VCO_DC_LEVEL_CTRL 0x198
|
||||
#define QSERDES_V10_60_COM_PLL_SPARE_FOR_ECO 0x2b4
|
||||
|
||||
#endif
|
||||
@@ -0,0 +1,47 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
|
||||
*/
|
||||
|
||||
#ifndef QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
|
||||
#define QCOM_PHY_QMP_QSERDES_TXRX_V10_H_
|
||||
|
||||
#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_TX 0x03c
|
||||
#define QSERDES_V10_TX_RES_CODE_LANE_OFFSET_RX 0x040
|
||||
#define QSERDES_V10_TX_LANE_MODE_1 0x084
|
||||
#define QSERDES_V10_TX_LANE_MODE_3 0x08c
|
||||
#define QSERDES_V10_TX_LANE_MODE_4 0x090
|
||||
#define QSERDES_V10_TX_LANE_MODE_5 0x094
|
||||
#define QSERDES_V10_TX_PI_QEC_CTRL 0x0e4
|
||||
|
||||
#define QSERDES_V10_RX_UCDR_FO_GAIN 0x008
|
||||
#define QSERDES_V10_RX_UCDR_SO_GAIN 0x014
|
||||
#define QSERDES_V10_RX_UCDR_SB2_THRESH1 0x04c
|
||||
#define QSERDES_V10_RX_UCDR_SB2_THRESH2 0x050
|
||||
#define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH1 0x0c4
|
||||
#define QSERDES_V10_RX_TX_ADAPT_PRE_THRESH2 0x0c8
|
||||
#define QSERDES_V10_RX_TX_ADAPT_POST_THRESH 0x0cc
|
||||
#define QSERDES_V10_RX_VGA_CAL_CNTRL2 0x0d8
|
||||
#define QSERDES_V10_RX_GM_CAL 0x0dc
|
||||
#define QSERDES_V10_RX_RX_IDAC_TSETTLE_LOW 0x0f8
|
||||
#define QSERDES_V10_RX_SIGDET_ENABLES 0x118
|
||||
#define QSERDES_V10_RX_SIGDET_CNTRL 0x11c
|
||||
#define QSERDES_V10_RX_RX_MODE_00_LOW 0x15c
|
||||
#define QSERDES_V10_RX_RX_MODE_00_HIGH 0x160
|
||||
#define QSERDES_V10_RX_RX_MODE_00_HIGH2 0x164
|
||||
#define QSERDES_V10_RX_RX_MODE_00_HIGH3 0x168
|
||||
#define QSERDES_V10_RX_RX_MODE_00_HIGH4 0x16c
|
||||
#define QSERDES_V10_RX_RX_MODE_01_LOW 0x170
|
||||
#define QSERDES_V10_RX_RX_MODE_01_HIGH 0x174
|
||||
#define QSERDES_V10_RX_RX_MODE_01_HIGH2 0x178
|
||||
#define QSERDES_V10_RX_RX_MODE_01_HIGH3 0x17c
|
||||
#define QSERDES_V10_RX_RX_MODE_01_HIGH4 0x180
|
||||
#define QSERDES_V10_RX_RX_MODE_10_LOW 0x184
|
||||
#define QSERDES_V10_RX_RX_MODE_10_HIGH 0x188
|
||||
#define QSERDES_V10_RX_RX_MODE_10_HIGH2 0x18c
|
||||
#define QSERDES_V10_RX_RX_MODE_10_HIGH3 0x190
|
||||
#define QSERDES_V10_RX_RX_MODE_10_HIGH4 0x194
|
||||
#define QSERDES_V10_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4
|
||||
#define QSERDES_V10_RX_SIGDET_CAL_TRIM 0x1f8
|
||||
|
||||
#endif
|
||||
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Reference in New Issue
Block a user