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Val Packett 76404ffbf0 dt-bindings: clock: qcom,gcc-sc8180x: Add missing GDSCs 
There are 5 more GDSCs that we were ignoring and not putting to sleep,
which are listed in downstream DTS. Add them.

Signed-off-by: Val Packett <val@packett.cool>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-2-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 21:08:51 -05:00
Kathiravan Thirumoorthy 844be6e24a clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC 
Add support for the global clock controller found on IPQ5210 SoC.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-ipq5210_boot_to_shell-v2-2-a87e27c37070@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 20:53:46 -05:00
Bjorn Andersson 1279298702 Merge branch '20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com' into clk-for-7.1 
Merge the IPQ5210 Global clock controller binding through a topic
branch, to allow the constants to also be merged into the DeviceTree
branch.
 2026-03-18 20:53:02 -05:00
Kathiravan Thirumoorthy 20a107bca2 dt-bindings: clock: add Qualcomm IPQ5210 GCC 
Add binding for the Qualcomm IPQ5210 Global Clock Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 20:52:54 -05:00
Krzysztof Kozlowski 04088a6825 clk: qcom: eliza: Cleanup redundant header includes 
Remove unused header includes - drivers do not use any OF API.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-clk-qcom-headers-v1-5-d5c6a3b11b67@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 20:50:06 -05:00
Krzysztof Kozlowski 84b21053fe clk: qcom: milos: Cleanup redundant header includes 
Remove unused header includes - drivers do not use any clk, OF or
PTR_ERR API, but they need declaration of of_device_id table.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-clk-qcom-headers-v1-4-d5c6a3b11b67@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 20:50:06 -05:00
Krzysztof Kozlowski 82e7613f5d clk: qcom: sm8750: Cleanup redundant header includes 
Remove unused header includes - drivers do not use any OF or runtime PM
API, but they need declaration of of_device_id table.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-clk-qcom-headers-v1-3-d5c6a3b11b67@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 20:50:06 -05:00
Krzysztof Kozlowski 320d45700c clk: qcom: glymur: Cleanup redundant header includes 
Remove unused header includes - drivers do not use any OF or runtime PM
API.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-clk-qcom-headers-v1-2-d5c6a3b11b67@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 20:50:06 -05:00
Krzysztof Kozlowski 7b70ccfd5d clk: qcom: kaanapali: Cleanup redundant header includes 
Remove unused header includes - drivers do not use any OF or runtime PM
API.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-clk-qcom-headers-v1-1-d5c6a3b11b67@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-18 20:50:06 -05:00
Val Packett a09a80b44b clk: qcom: dispcc-sm6125: Add missing MDSS resets 
The MDSS resets were left undescribed. Add them to allow resetting the
display subsystem, which is necessary to avoid issues caused by state
left over from the bootloader on various platforms.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260303034847.13870-5-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:45:28 -05:00
Val Packett 67d41a9237 clk: qcom: dispcc-sm6115: Add missing MDSS resets 
The MDSS resets were left undescribed. Add them to allow resetting the
display subsystem, which is necessary to avoid issues caused by state
left over from the bootloader on various platforms.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260303034847.13870-4-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:45:28 -05:00
Bjorn Andersson 8081dbb031 Merge branch '20260303034847.13870-2-val@packett.cool' into clk-for-7.1 
Merge the definition of MDSS resets for SM6115 and SM6125 to allow them
to be made available in the DeviceTree branch.
 2026-03-11 15:44:31 -05:00
Val Packett 0221b14be8 dt-bindings: clock: qcom,dispcc-sm6125: Define MDSS resets 
Add the missing defines for MDSS resets, which are necessary to reset
the display subsystem in order to avoid issues caused by state left over
from the bootloader.

While here, align comment style with other SoCs.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20260303034847.13870-3-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:44:18 -05:00
Val Packett a5c7b4fc84 dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets 
Add the missing defines for MDSS resets, which are necessary to reset
the display subsystem in order to avoid issues caused by state left over
from the bootloader.

While here, align comment style with other SoCs.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20260303034847.13870-2-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:44:18 -05:00
Abel Vesa c69a586344 clk: qcom: Add TCSR clock driver for Eliza 
Add the TCSR clock controller that provides the refclks on Eliza
platform for PCIe, USB and UFS subsystems.

Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-6-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:32:09 -05:00
Taniya Das 3d356ab4a1 clk: qcom: Add support for Global clock controller on Eliza 
Add support for Global clock controller for Eliza Qualcomm SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-5-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:32:08 -05:00
Taniya Das 76cbaa6557 clk: qcom: rpmh: Add support for Eliza rpmh clocks 
Add the RPMH clocks present in Eliza SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-4-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:32:08 -05:00
Bjorn Andersson b671f2f351 Merge branch '20260311-eliza-clocks-v6-1-453c4cf657a2@oss.qualcomm.com' into clk-for-7.1 
Merge DeviceTree bindings for Eliza global, rpmh, and tcsr clock
controllers through a topic branch, in case we need them in the
DeviceTree branch as well.
 2026-03-11 15:31:22 -05:00
Taniya Das b8a86146da dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Eliza 
Update the documentation for RPMH clock controller for Eliza SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-3-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:31:15 -05:00
Taniya Das b7518e0d1c dt-bindings: clock: qcom: Document the Eliza TCSR Clock Controller 
Add bindings documentation for TCSR Clock Controller for Eliza SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-2-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:31:14 -05:00
Taniya Das 8e3a93e7a1 dt-bindings: clock: qcom: document the Eliza Global Clock Controller 
Add bindings documentation for the Global Clock Controller on Qualcomm
Eliza SoC. Reuse the Milos bindings schema since the controller resources
are exactly the same, even though the controllers are incompatible between
them.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-1-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-11 15:31:14 -05:00
Konrad Dybcio 2851b6c6a4 clk: qcom: dispcc[01]-sa8775p: Fix DSI byte clock rate setting 
The clock tree for byte_clk_src is as follows:

   ┌──────byte0_clk_src─────┐
   │                        │
byte0_clk            byte0_div_clk_src
                            │
                     byte0_intf_clk

If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).

Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.

Fixes: e700bfd2f9 ("clk: qcom: Add support for Display clock Controllers on SA8775P")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-5-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-04 10:24:54 -06:00
Konrad Dybcio 7bc48fcdf9 clk: qcom: dispcc-sm4450: Fix DSI byte clock rate setting 
The clock tree for byte_clk_src is as follows:

   ┌──────byte0_clk_src─────┐
   │                        │
byte0_clk            byte0_div_clk_src
                            │
                     byte0_intf_clk

If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).

Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.

Fixes: 76f05f1ec7 ("clk: qcom: Add DISPCC driver support for SM4450")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-4-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-04 10:24:54 -06:00
Konrad Dybcio dd5b76257b clk: qcom: dispcc-milos: Fix DSI byte clock rate setting 
The clock tree for byte_clk_src is as follows:

   ┌──────byte0_clk_src─────┐
   │                        │
byte0_clk            byte0_div_clk_src
                            │
                     byte0_intf_clk

If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).

Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.

Fixes: f40b5217dc ("clk: qcom: Add Display Clock controller (DISPCC) driver for Milos")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-3-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-04 10:24:54 -06:00
Konrad Dybcio e892f4e3f3 clk: qcom: dispcc-kaanapali: Fix DSI byte clock rate setting 
The clock tree for byte_clk_src is as follows:

   ┌──────byte0_clk_src─────┐
   │                        │
byte0_clk            byte0_div_clk_src
                            │
                     byte0_intf_clk

If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).

Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.

Fixes: 6c6750b706 ("clk: qcom: dispcc: Add support for display clock controller Kaanapali")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-2-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-03-04 10:24:53 -06:00