Commit Graph
1475352 Commits
Author SHA1 Message Date
Udit TiwariandKonrad Dybcio 51231839d5 crypto: qce - Add runtime PM and interconnect bandwidth scaling support
The Qualcomm Crypto Engine (QCE) driver currently lacks support for
runtime power management (PM) and interconnect bandwidth control.
As a result, the hardware remains fully powered and clocks stay
enabled even when the device is idle. Additionally, static
interconnect bandwidth votes are held indefinitely, preventing the
system from reclaiming unused bandwidth.

Address this by enabling runtime PM and dynamic interconnect
bandwidth scaling to allow the system to suspend the device when idle
and scale interconnect usage based on actual demand. Improve overall
system efficiency by reducing power usage and optimizing interconnect
resource allocation.

Signed-off-by: Udit Tiwari <udit.tiwari@oss.qualcomm.com>
Tested-by: Pankaj Patil <pankaj.patil@oss.qualcomm.com>
2026-07-31 20:00:24 +02:00
Konrad Dybcio d43969b7f6 Revert "crypto: qce - Mark QCE as BROKEN"
This reverts commit df373d39c6.
2026-07-31 20:00:24 +02:00
Konrad Dybcio 92e3682fb5 ath12k_region_fix_from_baochen 2026-07-31 20:00:24 +02:00
Konrad Dybcio 78918ae2c3 HID: asus: support the Zenbook A16 (UX3607OA) keyboard
The ASUS Zenbook A16 (UX3607OA), a Qualcomm Snapdragon X2 Elite Extreme
(Glymur)-based laptop, carries its main keyboard on an I2C-HID device
with the ID 0B05:4B42. Its Fn/media hotkeys are emitted as vendor-page
(HID_UP_ASUSVENDOR) usages on report 0x5A.

Match the device in hid-asus with the standard I2C keyboard quirks and
add the three usage mappings observed on the hardware:

  0x85 -> KEY_CAMERA  (Fn+F11, camera toggle)
  0x86 -> KEY_PROG1   (Fn+F12, MyASUS key)
  0x5f -> KEY_PROG2   (extra programmable key)

The camera-toggle key reports its usage (0x85) together with a companion
state byte in the same array report ("5a 85 01" / "5a 85 10"). The 0x10
companion aliases the brightness-down vendor usage and spuriously dims
the panel, so add QUIRK_FILTER_CAMERA_COMPANION to zero the companion
slots for this device before input mapping. The quirk is device-gated so
no other ASUS model is affected.

Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2026-07-31 20:00:24 +02:00
Konrad Dybcio 4ee924e578 arm64: dts: qcom: glymur-zenbook-a16: Add Embedded Controller
The Glymur-based Zenbook A16 features an Embedded Controller running
custom ASUS firmware (which is loosely based on the reference Qualcomm
Hamoa EC one with a lot of modifications). It provides keyboard
backlight control, additional temperature sensor readouts, fan speed
monitoring and a number of miscellaneous functions.

Describe it.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2026-07-31 20:00:24 +02:00
Konrad Dybcio e4011cf8fe platform: arm64: Add a driver for the EC found on ASUS Glymur machines
Some Qualcomm Snapdragon X2 Elite (Extreme)-based ASUS laptops (at
least the Zenbook A14 and A16) expose a custom, somewhat
Qualcomm reference-derived EC interface. Introduce a driver to
communicate with said EC, allowing for fan speed reporting, keyboard
backlight setting and receiving of a number of miscellaneous sideband
events.

Assisted-by: Claude Code:claude-opus-4-8
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2026-07-31 20:00:24 +02:00
Konrad Dybcio edec53f698 dt-bindings: embedded-controller: Add ASUS Zenbook A16 EC
Some Qualcomm Snapdragon X2 Elite (Extreme)-based ASUS laptops (at
least the Zenbook A14 and A16) expose a custom, somewhat
Qualcomm reference-derived EC interface. It allows for fan speed
reporting, keyboard backlight setting and receiving of a number of
miscellaneous sideband events.

Introduce a binding for that class of devices.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2026-07-31 20:00:24 +02:00
Konrad Dybcio 20fba35c16 arm64: dts: qcom: glymur: Refrain from overclocking the USB2 controller
The USB2 controller's master clock has two defined operating points:
60 MHz at LOW_SVS and 120 MHz at SVS_L1. The lower one is good enough
for sustaining a High-Speed link, so use that instead.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2026-07-31 20:00:24 +02:00
Konrad Dybcio efa296641b [hack] clk: qcom: gcc-glymur: ignore usb2 pipe clock enable for hdmi on a16 2026-07-31 20:00:24 +02:00
Konrad Dybcio f487dc72b1 arm64: dts: qcom: glymur: Add Asus Zenbook A16 (UX3607OA)
UX3607OA is a variant of the Asus Zenbook A16 built on the Qualcomm
Glymur platform. It comes with an 18-core X2 Elite Extreme SoC, 48GiB
of RAM, NVMe storage, a 2880 x 1800 OLED screen, and the other typical
Glymur platform capabilities.

The hardware wiring is very different versus the 14" SKU - the larger
one is based on the System-In-Package reference design, unlike the
smaller one, which derives from a more common Chip-On-Board base.

Currently working:
- Audio playback (4 speakers)
- GPU, Display
- HDMI port
- Keyboard, touchpad, lid switch
- Privacy LEDs (camera-use, camera-block, mic-mute)
- Charging, Type-C, Type-A port
- Onboard SD Card slot (RTS5329)
- Wi-Fi, Bluetooth (QCC2072)
- Touchscreen should work on the SKUs that have it, but it remains
  untested due to lack of access to such a device

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2026-07-31 20:00:24 +02:00
Konrad Dybcio e8fb37b221 eusb2_repeater_1p2_and_require_supplies 2026-07-31 20:00:24 +02:00
Konrad DybcioandKonrad Dybcio 4a12eafb9c eusb2phy_hack 2026-07-31 20:00:24 +02:00
Krishna KurapatiandKonrad Dybcio 813ffd381a usb: dwc3: qcom: Modify interrupt handling for eUSB2 Phy targets
eUSB2 targets handle wakeup interrupts differently depending on device
speed when operating in host mode.

According to the eUSB2 specification, remote wakeup signaling in host
mode is detected via different data-line assertions based on the
connected device speed.

When a low-speed device is connected, the host repeater drives eD+ to
logic '1' upon detecting a K-state on the USB lines during remote wakeup
(eUSB2 specification, Section 5.5.14).

When a full-speed or high-speed device is connected, the host repeater
drives eD- to logic '1' upon detecting a K-state on the USB line during
remote wakeup (eUSB2 specification, Sections 5.5.15 and 5.5.18).

Since the eUSB2 PHY's "DP" and "DM" interrupt lines monitor the eD+ and
eD- line states, configure the wakeup interrupts accordingly

Signed-off-by: Krishna Kurapati <krishna.kurapati@oss.qualcomm.com>
2026-07-31 20:00:24 +02:00
Konrad Dybcio 5a8653dfad pmh0104_i1_j1 2026-07-31 20:00:24 +02:00
Konrad Dybcio 4511c93909 glymur_drop_double_newline 2026-07-31 20:00:24 +02:00
Konrad DybcioandKonrad Dybcio 08de7a0f3a gcc_collapse_ctrl 2026-07-31 20:00:24 +02:00
Qiang YuandKonrad Dybcio d09476b401 clk: qcom: gcc-glymur: Set FORCE_MEM_CORE_ON/FORCE_PERIPH_CORE_ON for PCIe pipe clocks
Update HPG to recommend setting FORCE_MEM_CORE_ON and FORCE_PERIPH_CORE_ON
for the PCIe PIPE clocks so that the inbound data path works correctly.

Without this, the PCIe link can come up but the endpoint gets stuck
during probe, with the host sometimes seeing a completion timeout
reported by the EP, even though the host can still read the EP's config
space.

Apply FORCE_MEM_CORE_ON/FORCE_PERIPH_CORE_ON to all PCIe pipe clocks on
Glymur (3a, 3b, 4, 5, 6) to avoid this issue.

Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
2026-07-31 20:00:23 +02:00
Konrad Dybcio f3cf0757e8 drm/msm/dsi: Drop dev_pm_opp_set_rate(0)
dev_pm_opp_set_rate(0) removes the vote specified in required-opps but
does not actually park the clock, making it run without the necessary
power backing. Drop the explicit call to it.

Every call site of ops->link_clk_disable() is followed by
pm_runtime_put(), so the power vote will be rescinded if deemed safe.

Fixes: 32d3e0fecc ("drm/msm: dsi: Use OPP API to set clk/perf state")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2026-07-31 20:00:23 +02:00
Konrad Dybcio 1674992aeb drm/msm/dp: Drop dev_pm_opp_set_rate(0)
dev_pm_opp_set_rate(0) removes the vote specified in required-opps but
does not actually park the clock, making it run without the necessary
power backing. Drop the explicit calls to it.

Fixes: c943b4948b ("drm/msm/dp: add displayPort driver support")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2026-07-31 20:00:23 +02:00
Konrad Dybcio 979e969ea8 drm/msm/dpu: Drop sneaky dev_pm_opp_set_rate(0)
dev_pm_opp_set_rate(0) removes the vote specified in required-opps but
does not actually park the clock, making it run without the necessary
power backing. Prevent that from happening when
_dpu_core_perf_get_core_clk_rate() returns 0.

Fixes: 25fdd5933e ("drm/msm: Add SDM845 DPU support")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
2026-07-31 20:00:23 +02:00
Manivannan SadhasivamandKonrad Dybcio 19c8b5ea3b of: property: Create devlink between PCI Host bridge and Root Port suppliers
In the recent times, devicetree started to represent the PCI Host bridge
supplies like PHY in the Root Port nodes as seen in commit 38fcbfbd42
("dt-bindings: PCI: qcom: Move PHY & reset GPIO to Root Port node"). But
the Host bridge drivers still need to control these supplies as a part of
their controller initialization/deinitialization sequence.

So the Host bridge drivers end up parsing the Root Port supplies in their
probe() and controlled them. A downside to this approach is that the
devlink dependency between the suppliers and Host bridge is completely
broken. Due to this, the driver core probes the Host bridge drivers even if
the suppliers are not ready, causing probe deferrals and setup teardowns in
probe().

These probe deferrals sometime happen over 1000 times (as reported in Qcom
Glymur platform) leading to a waste of CPU resources and increase in boot
time. So to fix these unnecessary deferrals, create devlink between the
Host bridge and Root Port suppliers in of_fwnode_add_links(). This will
allow the driver core to probe the Host bridge drivers only when all Root
Port suppliers are available.

Reported-by: Bjorn Andersson <andersson@kernel.org>
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@oss.qualcomm.com>
2026-07-31 20:00:23 +02:00
Yepuri SidduandKonrad Dybcio d4e0195854 Bluetooth: qca: add QCC2072 support
QCC2072 is a BT/WiFi combo SoC that uses different firmware
filenames and requires no external voltage regulators, so add
it as a new SoC type.

The chip supports the wideband speech and valid LE states
capabilities. Its firmware is named using the "orn" prefix and
follows the standard rom-version-based scheme:
    - qca/ornbtfw<ver>.tlv
    - qca/ornnv<ver>.bin

These firmware files are already present in the linux-firmware
repository.

Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
2026-07-31 20:00:23 +02:00
Vivek SahuandKonrad Dybcio 133a46220e dt-bindings: bluetooth: qcom,qcc2072-bt: add bindings for QCC2072
QCC2072 is a WiFi/BT connectivity radios which exposes
UART as an interface for Bluetooth part.
It requires different configuartions and firmware, so
document it as a new compatible string.

Signed-off-by: Vivek Sahu <vivek.sahu@oss.qualcomm.com>
2026-07-31 20:00:23 +02:00
Bjorn AnderssonandKonrad Dybcio bc7903f52c firmware: qcom: scm: Allow QSEECOM on Asus Zenbook A14 (UX3407NA)
In line with other Glymur-based machines, the Asus Zenbook A14
(UX3407NA) exposes EFI variables through the "uefisecapp". Add it to the
QSEECOM allowlist to enable this access.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
2026-07-31 20:00:23 +02:00
Bjorn AnderssonandKonrad Dybcio 5885c241c6 arm64: dts: qcom: glymur: Add Asus Zenbook A14 (UX3407NA)
UX3407NA is a variant of the Asus Zenbook A14 built on the Qualcomm
Glymur platform. It comes with an 18-core X2 Elite SoC, 32GB DDR, and
the other typical Glymur platform capabilities.

The Asus Zenbook uses &pcie3b for NVMe storage, the screen is WUXGA
OLED, it has two USB Type-C ports, one USB Type-A, and one HDMI port.

Signed-off-by: Bjorn Andersson <bjorn.andersson@oss.qualcomm.com>
2026-07-31 20:00:23 +02:00