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qcom-laptops
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12182 Commits
Author SHA1 Message Date
Qiang YuandAbel Vesa ca2beea3e5 clk: qcom: tcsrcc-x1e80100: Migrate to clk_ref helper 
Replace local clk_branch-based clkref definitions with descriptor-based
registration via qcom_clk_ref_probe().

This keeps the x1e80100 driver focused on clock metadata and reuses
common runtime logic for regulator handling, enable/disable sequencing,
and OF provider wiring.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
Link: https://patch.msgid.link/20260714-hamoa_tcsr_qref_0714_2-v1-2-13047922a376@oss.qualcomm.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
 2026-08-05 15:36:04 +03:00
Taniya DasandAbel Vesa ca5b345d50 clk: qcom: Add EVA clock controller driver for Glymur SoC 
Add the Enhanced Video Analytics (EVA) clock controller driver for
the Glymur SoC. The EVACC manages the PLL, RCGs, branch clocks, GDSCs
and resets for the EVA subsystem which handles vision processing
workloads.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260617-evacc_glymur-v2-3-905108dacaaa@oss.qualcomm.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
 2026-08-05 15:36:01 +03:00
Taniya DasandAbel Vesa fd1f76d1f9 clk: qcom: gcc-glymur: Move EVA clocks to critical clock list 
The gcc_eva_ahb_clk and gcc_eva_xo_clk branch clocks should not be
registered as standalone GCC branch clocks. Drop these clocks from
the GCC clock list and instead add their CBCR registers to the GCC
critical clocks list to ensure they remain enabled during early boot.

If these clocks are registered as normal branch clocks, they may be
gated, which breaks access to the EVA clock controller during clock
controller probe, thus leave them as critical clocks similar to other
subsystem AHB and XO clocks.

Fixes: efe504300a ("clk: qcom: gcc: Add support for Global Clock Controller")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://patch.msgid.link/20260617-evacc_glymur-v2-1-905108dacaaa@oss.qualcomm.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
 2026-08-05 15:36:01 +03:00
Jagadeesh KonaandAbel Vesa 23b90b8e8d clk: qcom: camcc-glymur: Add camera clock controller driver 
Add support for the camera clock controller for camera clients
to be able to request for camcc clocks on Glymur platform.

Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Link: https://patch.msgid.link/20260624-glymur_camcc-v5-2-a321df74b1a1@oss.qualcomm.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
 2026-08-05 15:36:01 +03:00
Qiang YuandAbel Vesa 6d662749b3 clk: qcom: tcsrcc-glymur: Add Mahua QREF regulator support 
Mahua is based on Glymur but uses a different QREF topology, requiring
distinct regulator lists and clock descriptors for its PCIe clock
references.

Add mahua-specific regulator arrays and clk descriptor table, and use
match_data to select the correct descriptor table per compatible string at
probe time.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
 2026-08-05 15:36:00 +03:00
Qiang YuandAbel Vesa 95743e7c44 clk: qcom: tcsrcc-glymur: Add regulator supplies and migrate to clk_ref helper 
Replace local clk_branch-based clkref definitions with descriptor-based
registration via qcom_clk_ref_probe().

This keeps the glymur driver focused on clock metadata and reuses common
runtime logic for regulator handling, enable/disable sequencing, and OF
provider wiring.

Co-developed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
 2026-08-05 15:36:00 +03:00
Qiang YuandAbel Vesa 03e2d49246 clk: qcom: Add generic clkref_en support 
Before XO refclk is distributed to PCIe/USB/eDP PHYs, it passes through
a QREF block. QREF is powered by dedicated LDO rails, and the clkref_en
register controls whether refclk is gated through to the PHY side.

These clkref controls are different from typical GCC branch clocks:
- only a single enable bit is present, without branch-style config bits
- regulators must be voted before enable and unvoted after disable

Model this as a dedicated clk_ref clock type with custom clk_ops instead
of reusing struct clk_branch semantics.

Also provide a common registration/probe API so the same clkref model
can be reused regardless of where clkref_en registers are placed, e.g.
TCSR on glymur and TLMM on SM8750.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com>
 2026-08-05 15:36:00 +03:00
Abel Vesa 6615986e48 clk: qcom: gcc-glymur: Enable runtime PM 
Enable runtime PM for the controller so the common GCC probe path resumes
the attached domain while registering clocks, resets and GDSCs.

This lets GDSC consumers propagate their votes through the GCC provider to
the CX parent domain.

Fixes: efe504300a ("clk: qcom: gcc: Add support for Global Clock Controller")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://patch.msgid.link/20260715-glymur-fix-gcc-cx-scaling-v3-2-72eb5adad156@oss.qualcomm.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
 2026-08-05 15:36:00 +03:00
Uwe Kleine-König (The Capable Hub) 995832b2ce Replace <linux/mod_devicetable.h> by more specific <linux/device-id/*.h> (c files) 
Replace the #include of <linux/mod_devicetable.h> by the more specific
<linux/device-id/*.h> where applicable. For most cases the include
can be dropped completely, only a few drivers need one or two headers
added.

Acked-by: Danilo Krummrich <dakr@kernel.org>
Acked-by: Takashi Sakamoto <o-takashi@sakamocchi.jp>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Link: https://patch.msgid.link/1a3f2007c5c5dcf555c09a4035ce3ae8ef1b6c49.1782808461.git.u.kleine-koenig@baylibre.com
Signed-off-by: Uwe Kleine-König (The Capable Hub) <u.kleine-koenig@baylibre.com>
 2026-07-03 07:38:17 +02:00
Linus Torvalds 8c04c1292d Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux 
Pull clk updates from Stephen Boyd:
 "This is all clk driver updates. Mostly new SoC support for various
  Qualcomm chips and Canaan K230. Otherwise there's non-critical fixes
  and updates to clk data such as adding missing clks to existing
  drivers or marking clks critical. Nothing looks especially exciting"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (106 commits)
  clk: qcom: regmap-phy-mux: Rework the implementation
  clk: qcom: a53: Corrected frequency multiplier for 1152MHz
  clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC
  clk: qcom: gdsc: Support enabling interconnect path for power domain
  dt-bindings: clock: qcom,milos-camcc: Document interconnect path
  interconnect: Add devm_of_icc_get_by_index() as exported API for users
  clk: qcom: camcc-x1p42100: Add support for camera clock controller
  clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks
  clk: qcom: videocc-x1p42100: Add support for video clock controller
  dt-bindings: clock: qcom: Add X1P42100 camera clock controller
  dt-bindings: clock: qcom: Add X1P42100 video clock controller
  clk: keystone: sci-clk: fix application of sizeof to pointer
  clk: keystone: don't cache clock rate
  clk: spacemit: k3: Add PCIe DBI clock
  dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
  clk: spacemit: k3: Fix PCIe clock register offset
  clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
  clk: at91: keep securam node alive while mapping it
  clk: samsung: exynos990: Fix PERIC0/1 USI clock types
  clk: renesas: r9a08g045: Drop unused pm_domain header file
  ...
 2026-06-25 12:48:57 -07:00
Stephen Boyd 92010229c4 Merge branches 'clk-microchip' and 'clk-qcom' into clk-next 
* clk-microchip:
  clk: at91: keep securam node alive while mapping it
  clk: at91: sama7d65: add peripheral clock for I3C
  clk: microchip: mpfs-ccc: fix peripheral driver registration failures after oob fix
  clk: at91: sam9x7: Fix gmac_gclk clock definition
  clk: at91: sam9x7: Rename macb0_clk to gmac_clk
  clk: at91: sam9x7: Remove gmac peripheral clock with ID 67
  clk: microchip: rename clk-core to clk-pic32

* clk-qcom: (32 commits)
  clk: qcom: regmap-phy-mux: Rework the implementation
  clk: qcom: a53: Corrected frequency multiplier for 1152MHz
  clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC
  clk: qcom: gdsc: Support enabling interconnect path for power domain
  dt-bindings: clock: qcom,milos-camcc: Document interconnect path
  interconnect: Add devm_of_icc_get_by_index() as exported API for users
  clk: qcom: camcc-x1p42100: Add support for camera clock controller
  clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks
  clk: qcom: videocc-x1p42100: Add support for video clock controller
  dt-bindings: clock: qcom: Add X1P42100 camera clock controller
  dt-bindings: clock: qcom: Add X1P42100 video clock controller
  clk: qcom: nord: negcc: add support for the USB2 PHY reset
  dt-bindings: clock: qcom: add the definition for the USB2 PHY reset
  clk: qcom: clk-rpmh: Make all VRMs optional
  clk: qcom: Add support for global clock controller on Hawi
  clk: qcom: clk-alpha-pll: Add support for Taycan EHA_T PLL
  clk: qcom: Add Hawi TCSR clock controller driver
  clk: qcom: rpmh: Add support for Hawi RPMH clocks
  dt-bindings: clock: qcom: Add Hawi global clock controller
  dt-bindings: clock: qcom: Add Hawi TCSR clock controller
  ...
 2026-06-25 07:55:47 -07:00
Stephen Boyd db810874e5 Merge branches 'clk-ti', 'clk-samsung', 'clk-rockchip' and 'clk-spacemit' into clk-next 
* clk-ti:
  clk: keystone: sci-clk: fix application of sizeof to pointer
  clk: keystone: don't cache clock rate

* clk-samsung:
  clk: samsung: exynos990: Fix PERIC0/1 USI clock types
  clk: samsung: exynos850: mark APM I3C clocks as critical

* clk-rockchip:
  clk: rockchip: allow COMPILE_TEST builds
  clk: rockchip: rk3588: add GATE_GRF clocks for I2S MCLK output to IO
  soc: rockchip: rk3588: add SYS_GRF SOC_CON6 register offset
  clk: rockchip: add helper to register auxiliary GRFs
  clk: rockchip: allow grf_type_sys lookup in aux_grf_table
  dt-bindings: clock: rockchip,rk3588-cru: add I2S MCLK output to IO clock IDs

* clk-spacemit:
  clk: spacemit: k3: Add PCIe DBI clock
  dt-bindings: soc: spacemit: k3: Add PCIe DBI clock IDs
  clk: spacemit: k3: Fix PCIe clock register offset
  clk: spacemit: k3: Switch to pll2_d6 as parent for PCIe clock
 2026-06-25 07:55:38 -07:00
Stephen Boyd e08f2083dd Merge branches 'clk-renesas', 'clk-socfpga', 'clk-amlogic' and 'clk-canaan' into clk-next 
* clk-renesas: (36 commits)
  clk: renesas: r9a08g045: Drop unused pm_domain header file
  clk: renesas: r8a779g0: Add DSC clock
  clk: renesas: rzg2l: Rename iterator in for_each_mod_clock() to avoid shadowing
  clk: renesas: r9a08g045: Drop unused DEF_G3S_MUX macro
  clk: renesas: rzg2l: Rename RZG3L-prefixed PLL macros to CPG-prefixed ones
  clk: renesas: rzg3s/rzg3l: Simplify PLL configuration macro
  clk: renesas: rzg2l: Simplify SAM PLL configuration macro
  clk: renesas: r8a73a4: Add ZT/ZTR trace clocks
  dt-bindings: clock: renesas,cpg-clocks: Document ZT/ZTR trace clock on R-Mobile APE6
  clk: renesas: r9a08g046: Add RSPI clocks and resets
  clk: renesas: r9a08g046: Add SSIF-2 clocks and resets
  clk: renesas: r9a08g046: Add RSCI clocks and resets
  clk: renesas: cpg-mssr: Add number of clock cells check
  clk: renesas: rzg2l: Refactor rzg3l_cpg_pll_clk_endisable()
  clk: renesas: rzg2l: Consolidate DEF_MUX() and DEF_MUX_FLAGS()
  clk: renesas: r9a08g046: Add IA55_PCLK to critical module clocks
  clk: renesas: r9a09g047: Add support for LCDC{0,1} clocks and resets
  clk: renesas: r9a09g047: Add support for DSI clocks and resets
  clk: renesas: r9a09g047: Add support for SMUX2_DSI{0,1}_CLK
  clk: renesas: r9a09g047: Add CLK_PLLDSI{0,1}_CSDIV clocks
  ...

* clk-socfpga:
  clk: socfpga: agilex: implement l3_main_free_clk

* clk-amlogic:
  dt-bindings: clock: amlogic: t7: Add missing mpll3 parent clock
  dt-bindings: clock: amlogic: Fix redundant hyphen in "amlogic,t7-gp1--pll" string.

* clk-canaan:
  clk: canaan: Add clock driver for Canaan K230
  dt-bindings: clock: Add Canaan K230 clock controller
 2026-06-25 07:55:26 -07:00
Stephen Boyd 124e5c5ec9 Merge branches 'clk-cleanup', 'clk-mediatek', 'clk-marvell' and 'clk-versal' into clk-next 
* clk-cleanup:
  clk: hisilicon: Improve deallocation in error path
  clk-lpc18xx-ccu: kzalloc + kcalloc to kzalloc_flex
  clk: bulk: Use dev_err_probe() helper in of_clk_bulk_get()
  clk: bcm: iproc-asiu: simplify allocation
  clk: clk-max77686: kzalloc + kcalloc to kzalloc
  clk: visconti: pll: use kzalloc_flex
  clk: hisilicon: clkdivider-hi6220: use kzalloc_flex
  clk: mvebu: use kzalloc_flex

* clk-mediatek:
  clk: mediatek: mt7988: use MUX_CLR_SET for gate-less muxes
  clk: mediatek: mt8192: use MUX_CLR_SET
  clk: mediatek: add MUX_CLR_SET macro

* clk-marvell:
  clk: mmp: pxa1908-apbcp: Add reset cells
  clk: mmp: pxa1908-apbc: Add reset cells
  dt-bindings: clock: marvell,pxa1908: Add #reset-cells

* clk-versal:
  clk: clk-axi-clkgen: Add support versal timings
 2026-06-25 07:55:16 -07:00
Linus Torvalds 70cb95c736 Merge tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc 
Pull SoC driver updates from Arnd Bergmann:
 "There are a few added drivers, but mostly the normal maintenance to
  drivers for firmware, memory controller and other soc specific
  hardware:

   - The NXP QuickEngine gets modern MSI support, which allows some
     cleanups to the GICv3 irqchip chip driver

   - A new SoC specific driver for the Renesas R-Car MFIS unit is added,
     encapsulating support for the on-chip mailbox and hwspinlock
     implementations that are not easily separated into individual
     drivers

   - The Qualcomm SoC drivers add support for additional SoC
     implementations, and flexibility around power management for the
     serial-engine driver as well as probing the LLCC driver using
     custom hardware descriptions inside of the device itself.

   - Added support for the Samsung thermal management unit

   - A cleanup to the Tegra 'PMC' driver interfaces to remove legacy
     APIs and allow multiple PMC instances everywhere.

   - Updates to the TI SCI and KNAS drivers to improve suspend/resume
     support.

   - Minor driver changes for mediatek, xilinx, allwinner, aspeed,
     tegra, broadcom, amd, microchip and starfive specific drivers

   - Memory controller updates for Tegra and Renesas for additional SoC
     types and other improvements.

   - Firmware driver updates for Arm FF-A, SMCCC and SCMI interfaces, to
     update driver probing, object lifetimes and address minor bugs"

* tag 'soc-drivers-7.2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (189 commits)
  Revert "firmware: zynqmp: Add dynamic CSU register discovery and sysfs interface"
  Revert "Documentation: ABI: add sysfs interface for ZynqMP CSU registers"
  memory: tegra234: drop dead NULL check in tegra234_mc_icc_aggregate()
  memory: tegra264: drop redundant tegra264_mc_icc_aggregate()
  memory: tegra186-emc: stop borrowing MC aggregate hook for EMC
  soc: aspeed: cleanup dead default for ASPEED_SOCINFO
  firmware: tegra: bpmp: Add support for multi-socket platforms
  firmware: tegra: bpmp: Propagate debugfs errors
  soc/tegra: pmc: Add Tegra238 support
  soc/tegra: pmc: Restrict power-off handler to Nexus 7
  soc/tegra: pmc: Populate powergate debugfs only when needed
  soc/tegra: pmc: Move legacy code behind CONFIG_ARM guard
  soc/tegra: pmc: Remove unused legacy functions
  soc/tegra: pmc: Create PMC context dynamically
  firmware: samsung: acpm: remove compile-testing stubs
  firmware: samsung: acpm: Add devm_acpm_get_by_phandle helper
  firmware: samsung: acpm: Add TMU protocol support
  firmware: samsung: acpm: Make acpm_ops const and access via pointer
  firmware: samsung: acpm: Drop redundant _ops suffix in acpm_ops members
  firmware: samsung: acpm: Annotate rx_data->cmd with __counted_by_ptr
  ...
 2026-06-17 11:21:40 -07:00
Stephen Boyd 19ec63c4ef Merge tag 'clk-microchip-fixes-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into clk-microchip 
Pull Microchip clock fixes from Claudiu Beznea:

 - Fix the GMAC GCLK clock ID for the SAM9X7 SoC
 - Properly decrement the reference count of a struct device_node
   in pmc_register_ops() after it is no longer needed
 - Fix the MPFS peripheral driver registration failures by using the proper
   size and mapping for the output clocks array

[sboyd@kernel.org: These all look non-critical so not taking for
clk-fixes]

* tag 'clk-microchip-fixes-7.1' of https://git.kernel.org/pub/scm/linux/kernel/git/at91/linux:
  clk: at91: keep securam node alive while mapping it
  clk: microchip: mpfs-ccc: fix peripheral driver registration failures after oob fix
  clk: at91: sam9x7: Fix gmac_gclk clock definition
 2026-06-13 14:10:42 -07:00
Arnd Bergmann 10c24a2a37 Merge tag 'ti-driver-soc-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux into soc/drivers 
TI SoC driver updates for v7.2

TI K3 TISCI:
- ti_sci: Add BOARDCFG_MANAGED mode for support system suspend/resume cycles
- ti_sci: Add support for restoring IRQ and clock contexts during resume.
- clk: keystone: sci-clk: Add clock restoration support.

SoC Drivers:
- k3-socinfo: Add support for identifying AM62P silicon variants via NVMEM,
  along with corresponding dt-bindings update for nvmem-cells support
- k3-ringacc: Fix incorrect access mode for ring pop tail IO/proxy operations

Keystone Navigator (knav) Cleanup and Fixes:
- knav_qmss: Multiple code quality improvements
- knav_qmss_queue: Implement proper resource cleanup in the remove() path

General Cleanups:
- k3-ringacc: Use str_enabled_disabled() helper for consistency
- knav_qmss: Use %pe format specifier for PTR_ERR() printing

* tag 'ti-driver-soc-for-v7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/ti/linux:
  firmware: ti_sci: Add support for restoring clock context during resume
  clk: keystone: sci-clk: Add restore_context() operation
  firmware: ti_sci: Add support for restoring IRQs during resume
  firmware: ti_sci: Add BOARDCFG_MANAGED mode support
  soc: ti: k3-ringacc: Use str_enabled_disabled() helper
  soc: ti: knav_dma: Use IOMEM_ERR_PTR() in pktdma_get_regs()
  soc: ti: knav_dma: Remove dead check on unsigned args.args[0]
  soc: ti: knav_dma: Remove unused DMA_PRIO_MASK macro
  soc: ti: knav_qmss_acc: Fix kernel-doc Return: tag
  soc: ti: knav_qmss: Fix __iomem annotations and __be32 type
  soc: ti: knav_qmss: Use %pe to print PTR_ERR()
  soc: ti: knav_qmss: Fix kernel-doc Return: tags
  soc: ti: knav_qmss: Inline lockdep condition in for_each_handle_rcu
  soc: ti: knav_qmss: Rename global kdev to knav_qdev to fix -Wshadow
  soc: ti: knav_qmss: Remove remaining redundant ENOMEM printks
  soc: ti: knav_qmss_queue: Implement resource cleanup in remove()
  soc: ti: k3-ringacc: Fix access mode for k3_ringacc_ring_pop_tail_io/proxy
  soc: ti: knav_dma: fix all kernel-doc warnings in knav_dma.h
  soc: ti: k3-socinfo: Add support for AM62P variants via NVMEM
  dt-bindings: hwinfo: ti,k3-socinfo: Add nvmem-cells support

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2026-06-09 16:59:20 +02:00
Arnd Bergmann c711f432e2 Merge tag 'samsung-drivers-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/drivers 
Samsung SoC drivers for v7.2

Improve Samsung Exynos (and Google GS101) ACPM (Alive Clock and Power
Manager) firmware driver:
1. Few code improvements.
2. Add support for protocol used to communicate with Thermal Management
   Unit (TMU).  This will allow to implement the thermal driver working
   for newer Samsung Exynos and Google GS101 SoCs.

* tag 'samsung-drivers-7.2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  firmware: samsung: acpm: remove compile-testing stubs
  firmware: samsung: acpm: Add devm_acpm_get_by_phandle helper
  firmware: samsung: acpm: Add TMU protocol support
  firmware: samsung: acpm: Make acpm_ops const and access via pointer
  firmware: samsung: acpm: Drop redundant _ops suffix in acpm_ops members
  firmware: samsung: acpm: Annotate rx_data->cmd with __counted_by_ptr
  firmware: samsung: acpm: Consolidate transfer initialization helper
  firmware: samsung: acpm: Fix infinite loop on sequence number exhaustion
  firmware: samsung: acpm: Fix missing LKMM barriers in sequence allocator
  firmware: samsung: acpm: Fix false timeouts and Use-After-Free in polling
  firmware: samsung: acpm: Fix mailbox channel leak on probe error
  firmware: samsung: acpm: Fix cross-thread RX length corruption

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
 2026-06-09 16:51:26 +02:00
Konrad DybcioandBjorn Andersson e108373c54 clk: qcom: regmap-phy-mux: Rework the implementation 
The sole reason this hw exists is to let the branch clock downstream of
it keep running, with the PHY disengaged. This is not possible with the
current implementation, as the enabled status is hijacked to mean
"enabled" = "use fast/PHY source" and "disabled" = "use XO source".

This is an issue, since the mux enable state follows that of the child
branch, making the desired "child enabled, MUX @ XO" combination
impossible.

Solve that by implementing ratesetting. Because PHY clock rates may
change at runtime and aren't really deterministic from Linux, assume
ULONG_MAX as "fast clock" and 19.2 MHz as XO. All the branches in
question already set CLK_SET_RATE_PARENT, so everything works out.

Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260409-topic-phy_fastclk-v1-1-6b4aaee56b90@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-06-08 09:17:24 -05:00
Phillip VarneyandBjorn Andersson bb56147ea9 clk: qcom: a53: Corrected frequency multiplier for 1152MHz 
The 1152MHz frequency entry for the a53 currently selects a multiplier of 62, giving 1190MHz. This changes the mulitiplier to 60 giving the intended 1152MHz.

Signed-off-by: Phillip Varney <pbvarney@protonmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Fixes: 0c6ab1b8f8 ("clk: qcom: Add A53 PLL support")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260605005502.313928-1-pbvarney@protonmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-06-08 09:08:55 -05:00
Luca WeissandBjorn Andersson 205aefa0db clk: qcom: camcc-milos: Declare icc path dependency for CAMSS_TOP_GDSC 
This GDSC requires an interconnect path to be enabled, otherwise the
GDSC will be stuck on 'off' and can't be enabled.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20260501-milos-camcc-icc-v2-4-bb83c1256cc3@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-06-06 19:51:15 -05:00
Luca WeissandBjorn Andersson bd09d87c55 clk: qcom: gdsc: Support enabling interconnect path for power domain 
On newer SoCs like Milos the CAMSS_TOP_GDSC power domains requires the
enablement of the multimedia NoC, otherwise the GDSC will be stuck on
'off'.

Add support for getting an interconnect path as specified in the SoC
clock driver, and enabling/disabling that interconnect path when the
GDSC is being enabled/disabled.

Signed-off-by: Luca Weiss <luca.weiss@fairphone.com>
Link: https://lore.kernel.org/r/20260501-milos-camcc-icc-v2-3-bb83c1256cc3@fairphone.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-06-06 19:51:15 -05:00
Jagadeesh KonaandBjorn Andersson 10524682d1 clk: qcom: camcc-x1p42100: Add support for camera clock controller 
Add support for the camera clock controller for camera clients to
be able to request for camcc clocks on X1P42100 platform. Although
X1P42100 is derived from X1E80100, the camera clock controller driver
differs significantly. Few PLLs, clocks and GDSC's are removed, there
is delta in frequency tables for most RCG's and parent data structures
also changed for few RCG's. Hence introduce a separate camcc driver
for X1P42100 platform.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-5-fc3af4130282@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-06-06 19:50:16 -05:00
Jagadeesh KonaandBjorn Andersson 1e6ae74ac6 clk: qcom: camcc-x1e80100: Add support for camera QDSS debug clocks 
Add support for camera QDSS debug clocks on X1E80100 platform which
are required to be voted for camera icp and cpas usecases. This change
aligns the camcc driver to the new ABI exposed from X1E80100 camcc
bindings that supports these camcc QDSS debug clocks.

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Fixes: 76126a5129 ("clk: qcom: Add camcc clock driver for x1e80100")
Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-4-fc3af4130282@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-06-06 19:50:16 -05:00
Jagadeesh KonaandBjorn Andersson cfc3490676 clk: qcom: videocc-x1p42100: Add support for video clock controller 
Add support for the video clock controller for video clients to be
able to request for videocc clocks on X1P42100 platform. Although
X1P42100 is derived from X1E80100, the video clock controller differs
significantly. The BSE clocks are newly added, several cdiv clocks have
been removed, and most RCG frequency tables have been updated. Initial
PLL configurations also require changes, hence introduce a separate
videocc driver for X1P42100 platform.

Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260507-purwa-videocc-camcc-v5-3-fc3af4130282@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
 2026-06-06 19:50:16 -05:00