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clk: qcom: Add EVA clock controller driver for Glymur SoC
Add the Enhanced Video Analytics (EVA) clock controller driver for the Glymur SoC. The EVACC manages the PLL, RCGs, branch clocks, GDSCs and resets for the EVA subsystem which handles vision processing workloads. Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://patch.msgid.link/20260617-evacc_glymur-v2-3-905108dacaaa@oss.qualcomm.com Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
This commit is contained in:
Taniya Das
Abel Vesa
@@ -66,6 +66,17 @@ config CLK_GLYMUR_DISPCC
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Say Y if you want to support display devices and functionality such as
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splash screen.
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config CLK_GLYMUR_EVACC
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tristate "Glymur EVA Clock Controller"
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depends on ARM64 || COMPILE_TEST
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default m if ARCH_QCOM
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select CLK_GLYMUR_GCC
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help
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Support for the Enhanced Video Analytics (EVA) clock controller on
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Qualcomm Technologies, Inc. Glymur devices.
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Say Y if you want to support EVA devices and functionality such as
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vision processing.
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config CLK_GLYMUR_GCC
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tristate "Glymur Global Clock Controller"
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depends on ARM64 || COMPILE_TEST
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@@ -27,6 +27,7 @@ obj-$(CONFIG_CLK_ELIZA_TCSRCC) += tcsrcc-eliza.o
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obj-$(CONFIG_CLK_GFM_LPASS_SM8250) += lpass-gfm-sm8250.o
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obj-$(CONFIG_CLK_GLYMUR_CAMCC) += camcc-glymur.o
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obj-$(CONFIG_CLK_GLYMUR_DISPCC) += dispcc-glymur.o
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obj-$(CONFIG_CLK_GLYMUR_EVACC) += evacc-glymur.o
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obj-$(CONFIG_CLK_GLYMUR_GCC) += gcc-glymur.o
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obj-$(CONFIG_CLK_GLYMUR_GPUCC) += gpucc-glymur.o gxclkctl-kaanapali.o
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obj-$(CONFIG_CLK_GLYMUR_TCSRCC) += tcsrcc-glymur.o
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@@ -0,0 +1,455 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
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*/
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#include <linux/clk-provider.h>
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#include <linux/mod_devicetable.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/regmap.h>
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#include <dt-bindings/clock/qcom,glymur-evacc.h>
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#include "clk-alpha-pll.h"
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#include "clk-branch.h"
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#include "clk-pll.h"
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#include "clk-rcg.h"
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#include "clk-regmap.h"
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#include "clk-regmap-divider.h"
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#include "clk-regmap-mux.h"
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#include "common.h"
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#include "gdsc.h"
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#include "reset.h"
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enum {
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DT_AHB_CLK,
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DT_BI_TCXO,
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DT_SLEEP_CLK,
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};
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enum {
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P_BI_TCXO,
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P_EVA_CC_PLL0_OUT_MAIN,
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P_SLEEP_CLK,
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};
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static const struct pll_vco taycan_eko_t_vco[] = {
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{ 249600000, 2500000000, 0 },
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};
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/* 840.0 MHz Configuration */
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static const struct alpha_pll_config eva_cc_pll0_config = {
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.l = 0x2b,
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.alpha = 0xc000,
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.config_ctl_val = 0x25c400e7,
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.config_ctl_hi_val = 0x0a8060e0,
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.config_ctl_hi1_val = 0xf51dea20,
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.user_ctl_val = 0x00000008,
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.user_ctl_hi_val = 0x00000002,
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};
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static struct clk_alpha_pll eva_cc_pll0 = {
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.offset = 0x0,
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.config = &eva_cc_pll0_config,
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.vco_table = taycan_eko_t_vco,
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.num_vco = ARRAY_SIZE(taycan_eko_t_vco),
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.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_TAYCAN_EKO_T],
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_pll0",
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.parent_data = &(const struct clk_parent_data) {
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.index = DT_BI_TCXO,
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},
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.num_parents = 1,
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.ops = &clk_alpha_pll_taycan_eko_t_ops,
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},
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},
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};
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static const struct parent_map eva_cc_parent_map_0[] = {
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{ P_BI_TCXO, 0 },
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};
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static const struct clk_parent_data eva_cc_parent_data_0[] = {
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{ .index = DT_BI_TCXO },
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};
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static const struct parent_map eva_cc_parent_map_1[] = {
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{ P_BI_TCXO, 0 },
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{ P_EVA_CC_PLL0_OUT_MAIN, 1 },
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};
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static const struct clk_parent_data eva_cc_parent_data_1[] = {
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{ .index = DT_BI_TCXO },
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{ .hw = &eva_cc_pll0.clkr.hw },
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};
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static const struct parent_map eva_cc_parent_map_2[] = {
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{ P_SLEEP_CLK, 0 },
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};
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static const struct clk_parent_data eva_cc_parent_data_2[] = {
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{ .index = DT_SLEEP_CLK },
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};
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static const struct freq_tbl ftbl_eva_cc_ahb_clk_src[] = {
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F(19200000, P_BI_TCXO, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 eva_cc_ahb_clk_src = {
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.cmd_rcgr = 0x8018,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = eva_cc_parent_map_0,
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.freq_tbl = ftbl_eva_cc_ahb_clk_src,
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.hw_clk_ctrl = true,
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_ahb_clk_src",
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.parent_data = eva_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(eva_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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},
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};
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static const struct freq_tbl ftbl_eva_cc_mvs0_clk_src[] = {
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F(840000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1050000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1350000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1500000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0),
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F(1650000000, P_EVA_CC_PLL0_OUT_MAIN, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 eva_cc_mvs0_clk_src = {
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.cmd_rcgr = 0x8000,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = eva_cc_parent_map_1,
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.freq_tbl = ftbl_eva_cc_mvs0_clk_src,
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.hw_clk_ctrl = true,
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_mvs0_clk_src",
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.parent_data = eva_cc_parent_data_1,
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.num_parents = ARRAY_SIZE(eva_cc_parent_data_1),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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},
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};
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static const struct freq_tbl ftbl_eva_cc_sleep_clk_src[] = {
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F(32000, P_SLEEP_CLK, 1, 0, 0),
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{ }
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};
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static struct clk_rcg2 eva_cc_sleep_clk_src = {
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.cmd_rcgr = 0x80e0,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = eva_cc_parent_map_2,
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.freq_tbl = ftbl_eva_cc_sleep_clk_src,
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.hw_clk_ctrl = true,
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_sleep_clk_src",
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.parent_data = eva_cc_parent_data_2,
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.num_parents = ARRAY_SIZE(eva_cc_parent_data_2),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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},
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};
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static struct clk_rcg2 eva_cc_xo_clk_src = {
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.cmd_rcgr = 0x80bc,
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.mnd_width = 0,
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.hid_width = 5,
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.parent_map = eva_cc_parent_map_0,
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.freq_tbl = ftbl_eva_cc_ahb_clk_src,
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.hw_clk_ctrl = true,
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.clkr = {
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_xo_clk_src",
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.parent_data = eva_cc_parent_data_0,
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.num_parents = ARRAY_SIZE(eva_cc_parent_data_0),
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_rcg2_shared_ops,
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},
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},
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};
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static struct clk_regmap_div eva_cc_mvs0_div_clk_src = {
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.reg = 0x809c,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_mvs0_div_clk_src",
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.parent_hws = (const struct clk_hw*[]) {
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&eva_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_regmap_div eva_cc_mvs0c_div2_div_clk_src = {
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.reg = 0x8060,
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.shift = 0,
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.width = 4,
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.clkr.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_mvs0c_div2_div_clk_src",
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.parent_hws = (const struct clk_hw*[]) {
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&eva_cc_mvs0_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_regmap_div_ro_ops,
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},
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};
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static struct clk_branch eva_cc_mvs0_clk = {
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.halt_reg = 0x807c,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x807c,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x807c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_mvs0_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&eva_cc_mvs0_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch eva_cc_mvs0_freerun_clk = {
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.halt_reg = 0x808c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x808c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_mvs0_freerun_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&eva_cc_mvs0_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch eva_cc_mvs0_shift_clk = {
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.halt_reg = 0x80d8,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x80d8,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x80d8,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_mvs0_shift_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&eva_cc_xo_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch eva_cc_mvs0c_clk = {
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.halt_reg = 0x804c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x804c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_mvs0c_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&eva_cc_mvs0c_div2_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch eva_cc_mvs0c_freerun_clk = {
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.halt_reg = 0x805c,
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.halt_check = BRANCH_HALT,
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.clkr = {
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.enable_reg = 0x805c,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_mvs0c_freerun_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&eva_cc_mvs0c_div2_div_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct clk_branch eva_cc_mvs0c_shift_clk = {
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.halt_reg = 0x80dc,
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.halt_check = BRANCH_HALT_VOTED,
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.hwcg_reg = 0x80dc,
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.hwcg_bit = 1,
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.clkr = {
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.enable_reg = 0x80dc,
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.enable_mask = BIT(0),
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.hw.init = &(const struct clk_init_data) {
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.name = "eva_cc_mvs0c_shift_clk",
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.parent_hws = (const struct clk_hw*[]) {
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&eva_cc_xo_clk_src.clkr.hw,
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},
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.num_parents = 1,
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.flags = CLK_SET_RATE_PARENT,
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.ops = &clk_branch2_ops,
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},
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},
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};
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static struct gdsc eva_cc_mvs0c_gdsc = {
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.gdscr = 0x8034,
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.en_rest_wait_val = 0x2,
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.en_few_wait_val = 0x2,
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.clk_dis_wait_val = 0x6,
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.pd = {
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.name = "eva_cc_mvs0c_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
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};
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static struct gdsc eva_cc_mvs0_gdsc = {
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.gdscr = 0x8068,
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.en_rest_wait_val = 0x2,
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.en_few_wait_val = 0x2,
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.clk_dis_wait_val = 0x6,
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.pd = {
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.name = "eva_cc_mvs0_gdsc",
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},
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.pwrsts = PWRSTS_OFF_ON,
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.flags = HW_CTRL_TRIGGER | POLL_CFG_GDSCR | RETAIN_FF_ENABLE,
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.parent = &eva_cc_mvs0c_gdsc.pd,
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};
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static struct clk_regmap *eva_cc_glymur_clocks[] = {
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[EVA_CC_AHB_CLK_SRC] = &eva_cc_ahb_clk_src.clkr,
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[EVA_CC_MVS0_CLK] = &eva_cc_mvs0_clk.clkr,
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[EVA_CC_MVS0_CLK_SRC] = &eva_cc_mvs0_clk_src.clkr,
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[EVA_CC_MVS0_DIV_CLK_SRC] = &eva_cc_mvs0_div_clk_src.clkr,
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[EVA_CC_MVS0_FREERUN_CLK] = &eva_cc_mvs0_freerun_clk.clkr,
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[EVA_CC_MVS0_SHIFT_CLK] = &eva_cc_mvs0_shift_clk.clkr,
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[EVA_CC_MVS0C_CLK] = &eva_cc_mvs0c_clk.clkr,
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[EVA_CC_MVS0C_DIV2_DIV_CLK_SRC] = &eva_cc_mvs0c_div2_div_clk_src.clkr,
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[EVA_CC_MVS0C_FREERUN_CLK] = &eva_cc_mvs0c_freerun_clk.clkr,
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[EVA_CC_MVS0C_SHIFT_CLK] = &eva_cc_mvs0c_shift_clk.clkr,
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[EVA_CC_PLL0] = &eva_cc_pll0.clkr,
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[EVA_CC_SLEEP_CLK_SRC] = &eva_cc_sleep_clk_src.clkr,
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[EVA_CC_XO_CLK_SRC] = &eva_cc_xo_clk_src.clkr,
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};
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static struct gdsc *eva_cc_glymur_gdscs[] = {
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[EVA_CC_MVS0_GDSC] = &eva_cc_mvs0_gdsc,
|
||||
[EVA_CC_MVS0C_GDSC] = &eva_cc_mvs0c_gdsc,
|
||||
};
|
||||
|
||||
static const struct qcom_reset_map eva_cc_glymur_resets[] = {
|
||||
[EVA_CC_INTERFACE_BCR] = { 0x80a0 },
|
||||
[EVA_CC_MVS0_BCR] = { 0x8064 },
|
||||
[EVA_CC_MVS0C_CLK_ARES] = { 0x804c, 2 },
|
||||
[EVA_CC_MVS0C_BCR] = { 0x8030 },
|
||||
[EVA_CC_MVS0C_FREERUN_CLK_ARES] = { 0x805c, 2 },
|
||||
};
|
||||
|
||||
static struct clk_alpha_pll *eva_cc_glymur_plls[] = {
|
||||
&eva_cc_pll0,
|
||||
};
|
||||
|
||||
static const u32 eva_cc_glymur_critical_cbcrs[] = {
|
||||
0x80a4, /* EVA_CC_AHB_CLK */
|
||||
0x80f8, /* EVA_CC_SLEEP_CLK */
|
||||
0x80d4, /* EVA_CC_XO_CLK */
|
||||
};
|
||||
|
||||
static const struct regmap_config eva_cc_glymur_regmap_config = {
|
||||
.reg_bits = 32,
|
||||
.reg_stride = 4,
|
||||
.val_bits = 32,
|
||||
.max_register = 0x9f50,
|
||||
.fast_io = true,
|
||||
};
|
||||
|
||||
static void clk_glymur_regs_configure(struct device *dev, struct regmap *regmap)
|
||||
{
|
||||
/*
|
||||
* Update CTRL_IN register as per HW recommendation to ensure clocks
|
||||
* stay cycle‑aligned when the EVA core is ON.
|
||||
*/
|
||||
regmap_set_bits(regmap, 0x9f24, BIT(0));
|
||||
}
|
||||
|
||||
static const struct qcom_cc_driver_data eva_cc_glymur_driver_data = {
|
||||
.alpha_plls = eva_cc_glymur_plls,
|
||||
.num_alpha_plls = ARRAY_SIZE(eva_cc_glymur_plls),
|
||||
.clk_cbcrs = eva_cc_glymur_critical_cbcrs,
|
||||
.num_clk_cbcrs = ARRAY_SIZE(eva_cc_glymur_critical_cbcrs),
|
||||
.clk_regs_configure = clk_glymur_regs_configure,
|
||||
};
|
||||
|
||||
static const struct qcom_cc_desc eva_cc_glymur_desc = {
|
||||
.config = &eva_cc_glymur_regmap_config,
|
||||
.clks = eva_cc_glymur_clocks,
|
||||
.num_clks = ARRAY_SIZE(eva_cc_glymur_clocks),
|
||||
.resets = eva_cc_glymur_resets,
|
||||
.num_resets = ARRAY_SIZE(eva_cc_glymur_resets),
|
||||
.gdscs = eva_cc_glymur_gdscs,
|
||||
.num_gdscs = ARRAY_SIZE(eva_cc_glymur_gdscs),
|
||||
.use_rpm = true,
|
||||
.driver_data = &eva_cc_glymur_driver_data,
|
||||
};
|
||||
|
||||
static const struct of_device_id eva_cc_glymur_match_table[] = {
|
||||
{ .compatible = "qcom,glymur-evacc" },
|
||||
{ }
|
||||
};
|
||||
MODULE_DEVICE_TABLE(of, eva_cc_glymur_match_table);
|
||||
|
||||
static int eva_cc_glymur_probe(struct platform_device *pdev)
|
||||
{
|
||||
return qcom_cc_probe(pdev, &eva_cc_glymur_desc);
|
||||
}
|
||||
|
||||
static struct platform_driver eva_cc_glymur_driver = {
|
||||
.probe = eva_cc_glymur_probe,
|
||||
.driver = {
|
||||
.name = "evacc-glymur",
|
||||
.of_match_table = eva_cc_glymur_match_table,
|
||||
},
|
||||
};
|
||||
|
||||
module_platform_driver(eva_cc_glymur_driver);
|
||||
|
||||
MODULE_DESCRIPTION("QTI EVACC Glymur Driver");
|
||||
MODULE_LICENSE("GPL");
|
||||
Reference in New Issue
Block a user