mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'loongarch-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson
Pull LoongArch updates from Huacai Chen:
- Adjust build infrastructure for 32BIT/64BIT
- Add HIGHMEM (PKMAP and FIX_KMAP) support
- Show and handle CPU vulnerabilites correctly
- Batch the icache maintenance for jump_label
- Add more atomic instructions support for BPF JIT
- Add more features (e.g. fsession) support for BPF trampoline
- Some bug fixes and other small changes
* tag 'loongarch-7.1' of git://git.kernel.org/pub/scm/linux/kernel/git/chenhuacai/linux-loongson: (21 commits)
selftests/bpf: Enable CAN_USE_LOAD_ACQ_STORE_REL for LoongArch
LoongArch: BPF: Add fsession support for trampolines
LoongArch: BPF: Introduce emit_store_stack_imm64() helper
LoongArch: BPF: Support up to 12 function arguments for trampoline
LoongArch: BPF: Support small struct arguments for trampoline
LoongArch: BPF: Open code and remove invoke_bpf_mod_ret()
LoongArch: BPF: Support load-acquire and store-release instructions
LoongArch: BPF: Support 8 and 16 bit read-modify-write instructions
LoongArch: BPF: Add the default case in emit_atomic() and rename it
LoongArch: Define instruction formats for AM{SWAP/ADD}.{B/H} and DBAR
LoongArch: Batch the icache maintenance for jump_label
LoongArch: Add flush_icache_all()/local_flush_icache_all()
LoongArch: Add spectre boundry for syscall dispatch table
LoongArch: Show CPU vulnerabilites correctly
LoongArch: Make arch_irq_work_has_interrupt() true only if IPI HW exist
LoongArch: Use get_random_canary() for stack canary init
LoongArch: Improve the logging of disabling KASLR
LoongArch: Align FPU register state to 32 bytes
LoongArch: Handle CONFIG_32BIT in syscall_get_arch()
LoongArch: Add HIGHMEM (PKMAP and FIX_KMAP) support
...
This commit is contained in:
Linus Torvalds
+86
-34
@@ -20,11 +20,11 @@ config LOONGARCH
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select ARCH_HAS_FAST_MULTIPLIER
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select ARCH_HAS_FORTIFY_SOURCE
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select ARCH_HAS_KCOV
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select ARCH_HAS_KERNEL_FPU_SUPPORT if CPU_HAS_FPU
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select ARCH_HAS_KERNEL_FPU_SUPPORT if 64BIT && CPU_HAS_FPU
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select ARCH_HAS_NMI_SAFE_THIS_CPU_OPS
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select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
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select ARCH_HAS_PREEMPT_LAZY
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select ARCH_HAS_PTE_SPECIAL
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select ARCH_HAS_PTE_SPECIAL if 64BIT
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select ARCH_HAS_SET_MEMORY
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select ARCH_HAS_SET_DIRECT_MAP
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select ARCH_HAS_TICK_BROADCAST if GENERIC_CLOCKEVENTS_BROADCAST
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@@ -59,16 +59,15 @@ config LOONGARCH
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select ARCH_KEEP_MEMBLOCK
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select ARCH_MIGHT_HAVE_PC_PARPORT
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select ARCH_MIGHT_HAVE_PC_SERIO
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select ARCH_SPARSEMEM_ENABLE
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select ARCH_STACKWALK
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select ARCH_SUPPORTS_ACPI
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select ARCH_SUPPORTS_ATOMIC_RMW
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select ARCH_SUPPORTS_HUGETLBFS
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select ARCH_SUPPORTS_HUGETLBFS if 64BIT
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select ARCH_SUPPORTS_INT128 if CC_HAS_INT128
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select ARCH_SUPPORTS_LTO_CLANG
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select ARCH_SUPPORTS_LTO_CLANG_THIN
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select ARCH_SUPPORTS_MSEAL_SYSTEM_MAPPINGS
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select ARCH_SUPPORTS_NUMA_BALANCING
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select ARCH_SUPPORTS_NUMA_BALANCING if NUMA
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select ARCH_SUPPORTS_PER_VMA_LOCK
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select ARCH_SUPPORTS_RT
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select ARCH_SUPPORTS_SCHED_SMT if SMP
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@@ -78,10 +77,10 @@ config LOONGARCH
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select ARCH_USE_MEMTEST
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select ARCH_USE_QUEUED_RWLOCKS
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select ARCH_USE_QUEUED_SPINLOCKS
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select ARCH_WANT_DEFAULT_BPF_JIT
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select ARCH_WANT_DEFAULT_BPF_JIT if HAVE_EBPF_JIT
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select ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
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select ARCH_WANT_LD_ORPHAN_WARN
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select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP
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select ARCH_WANT_OPTIMIZE_HUGETLB_VMEMMAP if 64BIT
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select ARCH_WANTS_NO_INSTR
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select ARCH_WANTS_THP_SWAP if HAVE_ARCH_TRANSPARENT_HUGEPAGE
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select BUILDTIME_TABLE_SORT
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@@ -89,13 +88,14 @@ config LOONGARCH
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select CPU_PM
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select EDAC_SUPPORT
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select EFI
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select GENERIC_ATOMIC64 if 32BIT
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select GENERIC_CLOCKEVENTS
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select GENERIC_CMOS_UPDATE
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select GENERIC_CPU_AUTOPROBE
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select GENERIC_CPU_DEVICES
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select GENERIC_CPU_VULNERABILITIES
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select GENERIC_ENTRY
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select GENERIC_GETTIMEOFDAY
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select GENERIC_GETTIMEOFDAY if 64BIT
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select GENERIC_IOREMAP if !ARCH_IOREMAP
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select GENERIC_IRQ_MATRIX_ALLOCATOR
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select GENERIC_IRQ_MULTI_HANDLER
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@@ -110,16 +110,16 @@ config LOONGARCH
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select GENERIC_PCI_IOMAP
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select GENERIC_SCHED_CLOCK
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select GENERIC_SMP_IDLE_THREAD
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select GENERIC_TIME_VSYSCALL
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select GENERIC_TIME_VSYSCALL if GENERIC_GETTIMEOFDAY
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select GPIOLIB
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select HAS_IOPORT
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select HAVE_ALIGNED_STRUCT_PAGE
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select HAVE_ALIGNED_STRUCT_PAGE if 64BIT
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select HAVE_ARCH_AUDITSYSCALL
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select HAVE_ARCH_BITREVERSE
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select HAVE_ARCH_BITREVERSE if 64BIT
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select HAVE_ARCH_JUMP_LABEL
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select HAVE_ARCH_JUMP_LABEL_RELATIVE
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select HAVE_ARCH_KASAN
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select HAVE_ARCH_KFENCE
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select HAVE_ARCH_KASAN if 64BIT
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select HAVE_ARCH_KFENCE if 64BIT
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select HAVE_ARCH_KGDB if PERF_EVENTS
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select HAVE_ARCH_KSTACK_ERASE
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select HAVE_ARCH_MMAP_RND_BITS if MMU
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@@ -127,8 +127,8 @@ config LOONGARCH
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select HAVE_ARCH_SECCOMP
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select HAVE_ARCH_SECCOMP_FILTER
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select HAVE_ARCH_TRACEHOOK
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select HAVE_ARCH_TRANSPARENT_HUGEPAGE
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select HAVE_ARCH_USERFAULTFD_MINOR if USERFAULTFD
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select HAVE_ARCH_TRANSPARENT_HUGEPAGE if 64BIT
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select HAVE_ARCH_USERFAULTFD_MINOR if 64BIT && USERFAULTFD
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select HAVE_ASM_MODVERSIONS
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select HAVE_CMPXCHG_DOUBLE
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select HAVE_CMPXCHG_LOCAL
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@@ -142,7 +142,7 @@ config LOONGARCH
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select HAVE_FTRACE_REGS_HAVING_PT_REGS
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select HAVE_DYNAMIC_FTRACE_WITH_DIRECT_CALLS
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select HAVE_DYNAMIC_FTRACE_WITH_REGS
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select HAVE_EBPF_JIT
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select HAVE_EBPF_JIT if 64BIT
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select HAVE_EFFICIENT_UNALIGNED_ACCESS if !ARCH_STRICT_ALIGN
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select HAVE_EXIT_THREAD
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select HAVE_GENERIC_TIF_BITS
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@@ -165,9 +165,9 @@ config LOONGARCH
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select HAVE_LIVEPATCH
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select HAVE_MOD_ARCH_SPECIFIC
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select HAVE_NMI
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select HAVE_OBJTOOL if AS_HAS_EXPLICIT_RELOCS && AS_HAS_THIN_ADD_SUB
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select HAVE_OBJTOOL if AS_HAS_EXPLICIT_RELOCS && AS_HAS_THIN_ADD_SUB && 64BIT
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select HAVE_PCI
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select HAVE_PERF_EVENTS
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select HAVE_PERF_EVENTS if 64BIT
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select HAVE_PERF_REGS
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select HAVE_PERF_USER_STACK_DUMP
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select HAVE_POSIX_CPU_TIMERS_TASK_WORK
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@@ -209,18 +209,50 @@ config LOONGARCH
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select SYSCTL_ARCH_UNALIGN_ALLOW
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select SYSCTL_ARCH_UNALIGN_NO_WARN
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select SYSCTL_EXCEPTION_TRACE
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select SWIOTLB
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select SWIOTLB if 64BIT
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select TRACE_IRQFLAGS_SUPPORT
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select USE_PERCPU_NUMA_NODE_ID
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select USER_STACKTRACE_SUPPORT
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select VDSO_GETRANDOM
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select ZONE_DMA32
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select ZONE_DMA32 if 64BIT
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menu "Kernel type and options"
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choice
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prompt "Kernel type"
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config 32BIT
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bool
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bool "32-bit kernel"
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help
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Select this option if you want to build a 32-bit kernel.
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config 64BIT
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def_bool y
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bool "64-bit kernel"
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help
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Select this option if you want to build a 64-bit kernel.
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endchoice
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if 32BIT
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choice
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prompt "32-bit kernel sub-type"
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config 32BIT_REDUCED
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bool "32-bit kernel for LA32R"
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help
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Select this option if you want to build a 32-bit kernel for
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LoongArch32 Reduced (LA32R).
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config 32BIT_STANDARD
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bool "32-bit kernel for LA32S"
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help
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Select this option if you want to build a 32-bit kernel for
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LoongArch32 Standard (LA32S).
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endchoice
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endif
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config GENERIC_BUG
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def_bool y
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@@ -313,10 +345,13 @@ config RUSTC_HAS_ANNOTATE_TABLEJUMP
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depends on RUST
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def_bool $(rustc-option,-Cllvm-args=--loongarch-annotate-tablejump)
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menu "Kernel type and options"
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source "kernel/Kconfig.hz"
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config HIGHMEM
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bool "High Memory Support"
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depends on 32BIT
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select KMAP_LOCAL
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choice
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prompt "Page Table Layout"
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default 16KB_2LEVEL if 32BIT
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@@ -326,8 +361,17 @@ choice
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of page size and page table levels. The size of virtual memory
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address space are determined by the page table layout.
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config 4KB_2LEVEL
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bool "4KB with 2 levels"
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select HAVE_PAGE_SIZE_4KB
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select PGTABLE_2LEVEL
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help
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This option selects 4KB page size with 2 level page tables, which
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support a maximum of 32 bits of application virtual memory.
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config 4KB_3LEVEL
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bool "4KB with 3 levels"
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depends on 64BIT
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select HAVE_PAGE_SIZE_4KB
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select PGTABLE_3LEVEL
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help
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@@ -336,6 +380,7 @@ config 4KB_3LEVEL
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config 4KB_4LEVEL
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bool "4KB with 4 levels"
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depends on 64BIT
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select HAVE_PAGE_SIZE_4KB
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select PGTABLE_4LEVEL
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help
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@@ -352,6 +397,7 @@ config 16KB_2LEVEL
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config 16KB_3LEVEL
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bool "16KB with 3 levels"
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depends on 64BIT
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select HAVE_PAGE_SIZE_16KB
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select PGTABLE_3LEVEL
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help
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@@ -368,6 +414,7 @@ config 64KB_2LEVEL
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config 64KB_3LEVEL
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bool "64KB with 3 levels"
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depends on 64BIT
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select HAVE_PAGE_SIZE_64KB
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select PGTABLE_3LEVEL
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help
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@@ -465,6 +512,7 @@ config EFI_STUB
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config SMP
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bool "Multi-Processing support"
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depends on 64BIT
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help
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This enables support for systems with more than one CPU. If you have
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a system with only one CPU, say N. If you have a system with more
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@@ -503,6 +551,7 @@ config NR_CPUS
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config NUMA
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bool "NUMA Support"
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select SMP
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depends on 64BIT
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help
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Say Y to compile the kernel with NUMA (Non-Uniform Memory Access)
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support. This option improves performance on systems with more
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@@ -585,7 +634,7 @@ config CPU_HAS_FPU
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config CPU_HAS_LSX
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bool "Support for the Loongson SIMD Extension"
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depends on AS_HAS_LSX_EXTENSION
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depends on AS_HAS_LSX_EXTENSION && 64BIT
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help
|
||||
Loongson SIMD Extension (LSX) introduces 128 bit wide vector registers
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and a set of SIMD instructions to operate on them. When this option
|
||||
@@ -600,7 +649,7 @@ config CPU_HAS_LSX
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config CPU_HAS_LASX
|
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bool "Support for the Loongson Advanced SIMD Extension"
|
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depends on CPU_HAS_LSX
|
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depends on AS_HAS_LASX_EXTENSION
|
||||
depends on AS_HAS_LASX_EXTENSION && 64BIT
|
||||
help
|
||||
Loongson Advanced SIMD Extension (LASX) introduces 256 bit wide vector
|
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registers and a set of SIMD instructions to operate on them. When this
|
||||
@@ -614,7 +663,7 @@ config CPU_HAS_LASX
|
||||
|
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config CPU_HAS_LBT
|
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bool "Support for the Loongson Binary Translation Extension"
|
||||
depends on AS_HAS_LBT_EXTENSION
|
||||
depends on AS_HAS_LBT_EXTENSION && 64BIT
|
||||
help
|
||||
Loongson Binary Translation (LBT) introduces 4 scratch registers (SCR0
|
||||
to SCR3), x86/ARM eflags (eflags) and x87 fpu stack pointer (ftop).
|
||||
@@ -642,13 +691,13 @@ config ARCH_SELECTS_KEXEC_FILE
|
||||
select HAVE_IMA_KEXEC if IMA
|
||||
|
||||
config ARCH_SUPPORTS_CRASH_DUMP
|
||||
def_bool y
|
||||
def_bool 64BIT
|
||||
|
||||
config ARCH_DEFAULT_CRASH_DUMP
|
||||
def_bool y
|
||||
def_bool 64BIT
|
||||
|
||||
config ARCH_SELECTS_CRASH_DUMP
|
||||
def_bool y
|
||||
def_bool 64BIT
|
||||
depends on CRASH_DUMP
|
||||
select RELOCATABLE
|
||||
|
||||
@@ -657,6 +706,7 @@ config ARCH_HAS_GENERIC_CRASHKERNEL_RESERVATION
|
||||
|
||||
config RELOCATABLE
|
||||
bool "Relocatable kernel"
|
||||
depends on 64BIT
|
||||
select ARCH_HAS_RELR
|
||||
help
|
||||
This builds the kernel as a Position Independent Executable (PIE),
|
||||
@@ -693,7 +743,7 @@ source "kernel/livepatch/Kconfig"
|
||||
|
||||
config PARAVIRT
|
||||
bool "Enable paravirtualization code"
|
||||
depends on AS_HAS_LVZ_EXTENSION
|
||||
depends on AS_HAS_LVZ_EXTENSION && 64BIT
|
||||
select HAVE_PV_STEAL_CLOCK_GEN
|
||||
help
|
||||
This changes the kernel so it can modify itself when it is run
|
||||
@@ -722,7 +772,7 @@ config ARCH_FLATMEM_ENABLE
|
||||
depends on !NUMA
|
||||
|
||||
config ARCH_SPARSEMEM_ENABLE
|
||||
def_bool y
|
||||
def_bool 64BIT
|
||||
select SPARSEMEM_VMEMMAP_ENABLE
|
||||
help
|
||||
Say Y to support efficient handling of sparse physical memory,
|
||||
@@ -739,10 +789,12 @@ config MMU
|
||||
default y
|
||||
|
||||
config ARCH_MMAP_RND_BITS_MIN
|
||||
default 12
|
||||
default 10 if 32BIT
|
||||
default 12 if 64BIT
|
||||
|
||||
config ARCH_MMAP_RND_BITS_MAX
|
||||
default 18
|
||||
default 15 if 32BIT
|
||||
default 20 if 64BIT
|
||||
|
||||
config ARCH_SUPPORTS_UPROBES
|
||||
def_bool y
|
||||
|
||||
+21
-2
@@ -25,6 +25,7 @@ endif
|
||||
#
|
||||
# Select the object file format to substitute into the linker script.
|
||||
#
|
||||
32bit-tool-archpref = loongarch32
|
||||
64bit-tool-archpref = loongarch64
|
||||
32bit-bfd = elf32-loongarch
|
||||
64bit-bfd = elf64-loongarch
|
||||
@@ -51,7 +52,10 @@ KBUILD_CPPFLAGS += -DCC_USING_PATCHABLE_FUNCTION_ENTRY
|
||||
CC_FLAGS_FTRACE := -fpatchable-function-entry=2
|
||||
endif
|
||||
|
||||
ifdef CONFIG_64BIT
|
||||
ifdef CONFIG_32BIT
|
||||
tool-archpref = $(32bit-tool-archpref)
|
||||
UTS_MACHINE := loongarch32
|
||||
else
|
||||
tool-archpref = $(64bit-tool-archpref)
|
||||
UTS_MACHINE := loongarch64
|
||||
endif
|
||||
@@ -62,9 +66,19 @@ ifneq ($(SUBARCH),$(ARCH))
|
||||
endif
|
||||
endif
|
||||
|
||||
ifdef CONFIG_32BIT
|
||||
ifdef CONFIG_32BIT_STANDARD
|
||||
ld-emul = $(32bit-emul)
|
||||
cflags-y += -march=la32v1.0 -mabi=ilp32s -mcmodel=normal
|
||||
else # CONFIG_32BIT_REDUCED
|
||||
ld-emul = $(32bit-emul)
|
||||
cflags-y += -march=la32rv1.0 -mabi=ilp32s -mcmodel=normal
|
||||
endif
|
||||
endif
|
||||
|
||||
ifdef CONFIG_64BIT
|
||||
ld-emul = $(64bit-emul)
|
||||
cflags-y += -mabi=lp64s -mcmodel=normal
|
||||
cflags-y += -march=loongarch64 -mabi=lp64s -mcmodel=normal
|
||||
endif
|
||||
|
||||
cflags-y += -pipe $(CC_FLAGS_NO_FPU)
|
||||
@@ -140,7 +154,12 @@ ifndef CONFIG_KASAN
|
||||
cflags-y += -fno-builtin-memcpy -fno-builtin-memmove -fno-builtin-memset
|
||||
endif
|
||||
|
||||
ifdef CONFIG_32BIT
|
||||
load-y = 0xa0200000
|
||||
else
|
||||
load-y = 0x9000000000200000
|
||||
endif
|
||||
|
||||
bootvars-y = VMLINUX_LOAD_ADDRESS=$(load-y)
|
||||
|
||||
drivers-$(CONFIG_PCI) += arch/loongarch/pci/
|
||||
|
||||
@@ -20,7 +20,13 @@ $(obj)/vmlinux.efi: vmlinux FORCE
|
||||
$(call if_changed,objcopy)
|
||||
|
||||
EFI_ZBOOT_PAYLOAD := vmlinux.efi
|
||||
|
||||
ifdef CONFIG_32BIT
|
||||
EFI_ZBOOT_BFD_TARGET := elf32-loongarch
|
||||
EFI_ZBOOT_MACH_TYPE := LOONGARCH32
|
||||
else
|
||||
EFI_ZBOOT_BFD_TARGET := elf64-loongarch
|
||||
EFI_ZBOOT_MACH_TYPE := LOONGARCH64
|
||||
endif
|
||||
|
||||
include $(srctree)/drivers/firmware/efi/libstub/Makefile.zboot
|
||||
|
||||
@@ -32,8 +32,22 @@ static inline unsigned int cpu_last_level_cache_line_size(void)
|
||||
}
|
||||
|
||||
asmlinkage void __flush_cache_all(void);
|
||||
void local_flush_icache_range(unsigned long start, unsigned long end);
|
||||
|
||||
/*
|
||||
* LoongArch maintains ICache/DCache coherency by hardware,
|
||||
* we just need "ibar" to avoid instruction hazard here.
|
||||
*/
|
||||
static inline void local_flush_icache_all(void)
|
||||
{
|
||||
asm volatile ("ibar\t0\n"::);
|
||||
}
|
||||
|
||||
static inline void local_flush_icache_range(unsigned long start, unsigned long end)
|
||||
{
|
||||
asm volatile ("ibar\t0\n"::);
|
||||
}
|
||||
|
||||
#define flush_icache_all local_flush_icache_all
|
||||
#define flush_icache_range local_flush_icache_range
|
||||
#define flush_icache_user_range local_flush_icache_range
|
||||
|
||||
|
||||
@@ -35,6 +35,7 @@
|
||||
*/
|
||||
#define cpu_has_cpucfg cpu_opt(LOONGARCH_CPU_CPUCFG)
|
||||
#define cpu_has_lam cpu_opt(LOONGARCH_CPU_LAM)
|
||||
#define cpu_has_lam_bh cpu_opt(LOONGARCH_CPU_LAM_BH)
|
||||
#define cpu_has_scq cpu_opt(LOONGARCH_CPU_SCQ)
|
||||
#define cpu_has_ual cpu_opt(LOONGARCH_CPU_UAL)
|
||||
#define cpu_has_fpu cpu_opt(LOONGARCH_CPU_FPU)
|
||||
|
||||
@@ -95,40 +95,42 @@ static inline char *id_to_core_name(unsigned int id)
|
||||
*/
|
||||
#define CPU_FEATURE_CPUCFG 0 /* CPU has CPUCFG */
|
||||
#define CPU_FEATURE_LAM 1 /* CPU has Atomic instructions */
|
||||
#define CPU_FEATURE_SCQ 2 /* CPU has SC.Q instruction */
|
||||
#define CPU_FEATURE_UAL 3 /* CPU supports unaligned access */
|
||||
#define CPU_FEATURE_FPU 4 /* CPU has FPU */
|
||||
#define CPU_FEATURE_LSX 5 /* CPU has LSX (128-bit SIMD) */
|
||||
#define CPU_FEATURE_LASX 6 /* CPU has LASX (256-bit SIMD) */
|
||||
#define CPU_FEATURE_CRC32 7 /* CPU has CRC32 instructions */
|
||||
#define CPU_FEATURE_COMPLEX 8 /* CPU has Complex instructions */
|
||||
#define CPU_FEATURE_CRYPTO 9 /* CPU has Crypto instructions */
|
||||
#define CPU_FEATURE_LVZ 10 /* CPU has Virtualization extension */
|
||||
#define CPU_FEATURE_LBT_X86 11 /* CPU has X86 Binary Translation */
|
||||
#define CPU_FEATURE_LBT_ARM 12 /* CPU has ARM Binary Translation */
|
||||
#define CPU_FEATURE_LBT_MIPS 13 /* CPU has MIPS Binary Translation */
|
||||
#define CPU_FEATURE_TLB 14 /* CPU has TLB */
|
||||
#define CPU_FEATURE_CSR 15 /* CPU has CSR */
|
||||
#define CPU_FEATURE_IOCSR 16 /* CPU has IOCSR */
|
||||
#define CPU_FEATURE_WATCH 17 /* CPU has watchpoint registers */
|
||||
#define CPU_FEATURE_VINT 18 /* CPU has vectored interrupts */
|
||||
#define CPU_FEATURE_CSRIPI 19 /* CPU has CSR-IPI */
|
||||
#define CPU_FEATURE_EXTIOI 20 /* CPU has EXT-IOI */
|
||||
#define CPU_FEATURE_PREFETCH 21 /* CPU has prefetch instructions */
|
||||
#define CPU_FEATURE_PMP 22 /* CPU has perfermance counter */
|
||||
#define CPU_FEATURE_SCALEFREQ 23 /* CPU supports cpufreq scaling */
|
||||
#define CPU_FEATURE_FLATMODE 24 /* CPU has flat mode */
|
||||
#define CPU_FEATURE_EIODECODE 25 /* CPU has EXTIOI interrupt pin decode mode */
|
||||
#define CPU_FEATURE_GUESTID 26 /* CPU has GuestID feature */
|
||||
#define CPU_FEATURE_HYPERVISOR 27 /* CPU has hypervisor (running in VM) */
|
||||
#define CPU_FEATURE_PTW 28 /* CPU has hardware page table walker */
|
||||
#define CPU_FEATURE_LSPW 29 /* CPU has LSPW (lddir/ldpte instructions) */
|
||||
#define CPU_FEATURE_MSGINT 30 /* CPU has MSG interrupt */
|
||||
#define CPU_FEATURE_AVECINT 31 /* CPU has AVEC interrupt */
|
||||
#define CPU_FEATURE_REDIRECTINT 32 /* CPU has interrupt remapping */
|
||||
#define CPU_FEATURE_LAM_BH 2 /* CPU has AM{SWAP/ADD}[_DB].{B/H} instructions */
|
||||
#define CPU_FEATURE_SCQ 3 /* CPU has SC.Q instruction */
|
||||
#define CPU_FEATURE_UAL 4 /* CPU supports unaligned access */
|
||||
#define CPU_FEATURE_FPU 5 /* CPU has FPU */
|
||||
#define CPU_FEATURE_LSX 6 /* CPU has LSX (128-bit SIMD) */
|
||||
#define CPU_FEATURE_LASX 7 /* CPU has LASX (256-bit SIMD) */
|
||||
#define CPU_FEATURE_CRC32 8 /* CPU has CRC32 instructions */
|
||||
#define CPU_FEATURE_COMPLEX 9 /* CPU has Complex instructions */
|
||||
#define CPU_FEATURE_CRYPTO 10 /* CPU has Crypto instructions */
|
||||
#define CPU_FEATURE_LVZ 11 /* CPU has Virtualization extension */
|
||||
#define CPU_FEATURE_LBT_X86 12 /* CPU has X86 Binary Translation */
|
||||
#define CPU_FEATURE_LBT_ARM 13 /* CPU has ARM Binary Translation */
|
||||
#define CPU_FEATURE_LBT_MIPS 14 /* CPU has MIPS Binary Translation */
|
||||
#define CPU_FEATURE_TLB 15 /* CPU has TLB */
|
||||
#define CPU_FEATURE_CSR 16 /* CPU has CSR */
|
||||
#define CPU_FEATURE_IOCSR 17 /* CPU has IOCSR */
|
||||
#define CPU_FEATURE_WATCH 18 /* CPU has watchpoint registers */
|
||||
#define CPU_FEATURE_VINT 19 /* CPU has vectored interrupts */
|
||||
#define CPU_FEATURE_CSRIPI 20 /* CPU has CSR-IPI */
|
||||
#define CPU_FEATURE_EXTIOI 21 /* CPU has EXT-IOI */
|
||||
#define CPU_FEATURE_PREFETCH 22 /* CPU has prefetch instructions */
|
||||
#define CPU_FEATURE_PMP 23 /* CPU has perfermance counter */
|
||||
#define CPU_FEATURE_SCALEFREQ 24 /* CPU supports cpufreq scaling */
|
||||
#define CPU_FEATURE_FLATMODE 25 /* CPU has flat mode */
|
||||
#define CPU_FEATURE_EIODECODE 26 /* CPU has EXTIOI interrupt pin decode mode */
|
||||
#define CPU_FEATURE_GUESTID 27 /* CPU has GuestID feature */
|
||||
#define CPU_FEATURE_HYPERVISOR 28 /* CPU has hypervisor (running in VM) */
|
||||
#define CPU_FEATURE_PTW 29 /* CPU has hardware page table walker */
|
||||
#define CPU_FEATURE_LSPW 30 /* CPU has LSPW (lddir/ldpte instructions) */
|
||||
#define CPU_FEATURE_MSGINT 31 /* CPU has MSG interrupt */
|
||||
#define CPU_FEATURE_AVECINT 32 /* CPU has AVEC interrupt */
|
||||
#define CPU_FEATURE_REDIRECTINT 33 /* CPU has interrupt remapping */
|
||||
|
||||
#define LOONGARCH_CPU_CPUCFG BIT_ULL(CPU_FEATURE_CPUCFG)
|
||||
#define LOONGARCH_CPU_LAM BIT_ULL(CPU_FEATURE_LAM)
|
||||
#define LOONGARCH_CPU_LAM_BH BIT_ULL(CPU_FEATURE_LAM_BH)
|
||||
#define LOONGARCH_CPU_SCQ BIT_ULL(CPU_FEATURE_SCQ)
|
||||
#define LOONGARCH_CPU_UAL BIT_ULL(CPU_FEATURE_UAL)
|
||||
#define LOONGARCH_CPU_FPU BIT_ULL(CPU_FEATURE_FPU)
|
||||
|
||||
@@ -8,10 +8,19 @@
|
||||
#ifndef _ASM_FIXMAP_H
|
||||
#define _ASM_FIXMAP_H
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
#include <linux/threads.h>
|
||||
#include <asm/kmap_size.h>
|
||||
#endif
|
||||
|
||||
#define NR_FIX_BTMAPS 64
|
||||
|
||||
enum fixed_addresses {
|
||||
FIX_HOLE,
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
FIX_KMAP_BEGIN,
|
||||
FIX_KMAP_END = FIX_KMAP_BEGIN + (KM_MAX_IDX * NR_CPUS) - 1,
|
||||
#endif
|
||||
FIX_EARLYCON_MEM_BASE,
|
||||
__end_of_fixed_addresses
|
||||
};
|
||||
@@ -25,4 +34,9 @@ extern void __set_fixmap(enum fixed_addresses idx,
|
||||
|
||||
#include <asm-generic/fixmap.h>
|
||||
|
||||
/*
|
||||
* Called from pagetable_init()
|
||||
*/
|
||||
extern void fixrange_init(unsigned long start, unsigned long end, pgd_t *pgd_base);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -0,0 +1,43 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* highmem.h: virtual kernel memory mappings for high memory
|
||||
*
|
||||
* Used in CONFIG_HIGHMEM systems for memory pages which
|
||||
* are not addressable by direct kernel virtual addresses.
|
||||
*
|
||||
* Copyright (C) 2025 Loongson Technology Corporation Limited
|
||||
*/
|
||||
#ifndef _ASM_HIGHMEM_H
|
||||
#define _ASM_HIGHMEM_H
|
||||
|
||||
#ifdef __KERNEL__
|
||||
|
||||
#include <asm/kmap_size.h>
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
|
||||
extern pte_t *pkmap_page_table;
|
||||
|
||||
#define ARCH_HAS_KMAP_FLUSH_TLB
|
||||
void kmap_flush_tlb(unsigned long addr);
|
||||
|
||||
#endif /* !__ASSEMBLER__ */
|
||||
|
||||
/*
|
||||
* Right now we initialize only a single pte table. It can be extended
|
||||
* easily, subsequent pte tables have to be allocated in one physical
|
||||
* chunk of RAM.
|
||||
*/
|
||||
#define LAST_PKMAP 1024
|
||||
#define LAST_PKMAP_MASK (LAST_PKMAP - 1)
|
||||
#define PKMAP_NR(virt) ((virt - PKMAP_BASE) >> PAGE_SHIFT)
|
||||
#define PKMAP_ADDR(nr) (PKMAP_BASE + ((nr) << PAGE_SHIFT))
|
||||
|
||||
#define flush_cache_kmaps() do {} while (0)
|
||||
|
||||
#define arch_kmap_local_post_map(vaddr, pteval) local_flush_tlb_one(vaddr)
|
||||
#define arch_kmap_local_post_unmap(vaddr) local_flush_tlb_one(vaddr)
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
#endif /* _ASM_HIGHMEM_H */
|
||||
@@ -36,6 +36,7 @@
|
||||
|
||||
enum reg0i15_op {
|
||||
break_op = 0x54,
|
||||
dbar_op = 0x70e4,
|
||||
};
|
||||
|
||||
enum reg0i26_op {
|
||||
@@ -194,6 +195,10 @@ enum reg3_op {
|
||||
fstxs_op = 0x7070,
|
||||
fstxd_op = 0x7078,
|
||||
scq_op = 0x70ae,
|
||||
amswapb_op = 0x70b8,
|
||||
amswaph_op = 0x70b9,
|
||||
amaddb_op = 0x70ba,
|
||||
amaddh_op = 0x70bb,
|
||||
amswapw_op = 0x70c0,
|
||||
amswapd_op = 0x70c1,
|
||||
amaddw_op = 0x70c2,
|
||||
@@ -543,6 +548,7 @@ static inline void emit_##NAME(union loongarch_instruction *insn, \
|
||||
}
|
||||
|
||||
DEF_EMIT_REG0I15_FORMAT(break, break_op)
|
||||
DEF_EMIT_REG0I15_FORMAT(dbar, dbar_op)
|
||||
|
||||
/* like emit_break(imm) but returns a constant expression */
|
||||
#define __emit_break(imm) ((u32)((imm) | (break_op << 15)))
|
||||
@@ -763,6 +769,8 @@ DEF_EMIT_REG3_FORMAT(stxb, stxb_op)
|
||||
DEF_EMIT_REG3_FORMAT(stxh, stxh_op)
|
||||
DEF_EMIT_REG3_FORMAT(stxw, stxw_op)
|
||||
DEF_EMIT_REG3_FORMAT(stxd, stxd_op)
|
||||
DEF_EMIT_REG3_FORMAT(amaddb, amaddb_op)
|
||||
DEF_EMIT_REG3_FORMAT(amaddh, amaddh_op)
|
||||
DEF_EMIT_REG3_FORMAT(amaddw, amaddw_op)
|
||||
DEF_EMIT_REG3_FORMAT(amaddd, amaddd_op)
|
||||
DEF_EMIT_REG3_FORMAT(amandw, amandw_op)
|
||||
@@ -771,6 +779,8 @@ DEF_EMIT_REG3_FORMAT(amorw, amorw_op)
|
||||
DEF_EMIT_REG3_FORMAT(amord, amord_op)
|
||||
DEF_EMIT_REG3_FORMAT(amxorw, amxorw_op)
|
||||
DEF_EMIT_REG3_FORMAT(amxord, amxord_op)
|
||||
DEF_EMIT_REG3_FORMAT(amswapb, amswapb_op)
|
||||
DEF_EMIT_REG3_FORMAT(amswaph, amswaph_op)
|
||||
DEF_EMIT_REG3_FORMAT(amswapw, amswapw_op)
|
||||
DEF_EMIT_REG3_FORMAT(amswapd, amswapd_op)
|
||||
|
||||
|
||||
@@ -4,7 +4,7 @@
|
||||
|
||||
static inline bool arch_irq_work_has_interrupt(void)
|
||||
{
|
||||
return IS_ENABLED(CONFIG_SMP);
|
||||
return IS_ENABLED(CONFIG_SMP) && cpu_opt(LOONGARCH_CPU_CSRIPI);
|
||||
}
|
||||
|
||||
#endif /* _ASM_LOONGARCH_IRQ_WORK_H */
|
||||
|
||||
@@ -13,6 +13,8 @@
|
||||
#include <linux/stringify.h>
|
||||
#include <asm/asm.h>
|
||||
|
||||
#define HAVE_JUMP_LABEL_BATCH
|
||||
|
||||
#define JUMP_LABEL_NOP_SIZE 4
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
|
||||
@@ -36,10 +36,6 @@ extern unsigned long shm_align_mask;
|
||||
|
||||
struct page;
|
||||
struct vm_area_struct;
|
||||
void copy_user_highpage(struct page *to, struct page *from,
|
||||
unsigned long vaddr, struct vm_area_struct *vma);
|
||||
|
||||
#define __HAVE_ARCH_COPY_USER_HIGHPAGE
|
||||
|
||||
typedef struct { unsigned long pte; } pte_t;
|
||||
#define pte_val(x) ((x).pte)
|
||||
|
||||
@@ -23,6 +23,10 @@
|
||||
#include <asm-generic/pgtable-nop4d.h>
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
#include <asm/highmem.h>
|
||||
#endif
|
||||
|
||||
#if CONFIG_PGTABLE_LEVELS == 2
|
||||
#define PGDIR_SHIFT (PAGE_SHIFT + (PAGE_SHIFT - PTRLOG))
|
||||
#elif CONFIG_PGTABLE_LEVELS == 3
|
||||
@@ -77,7 +81,15 @@ struct vm_area_struct;
|
||||
#ifdef CONFIG_32BIT
|
||||
|
||||
#define VMALLOC_START (vm_map_base + PCI_IOSIZE + (2 * PAGE_SIZE))
|
||||
|
||||
#ifdef CONFIG_HIGHMEM
|
||||
#define VMALLOC_END (PKMAP_BASE - (2 * PAGE_SIZE))
|
||||
#else
|
||||
#define VMALLOC_END (FIXADDR_START - (2 * PAGE_SIZE))
|
||||
#endif
|
||||
|
||||
#define PKMAP_BASE (PKMAP_END - (PAGE_SIZE * LAST_PKMAP))
|
||||
#define PKMAP_END ((FIXADDR_START) & ~((LAST_PKMAP << PAGE_SHIFT)-1))
|
||||
|
||||
#endif
|
||||
|
||||
|
||||
@@ -80,10 +80,10 @@ BUILD_FPR_ACCESS(32)
|
||||
BUILD_FPR_ACCESS(64)
|
||||
|
||||
struct loongarch_fpu {
|
||||
union fpureg fpr[NUM_FPU_REGS];
|
||||
uint64_t fcc; /* 8x8 */
|
||||
uint32_t fcsr;
|
||||
uint32_t ftop;
|
||||
union fpureg fpr[NUM_FPU_REGS];
|
||||
};
|
||||
|
||||
struct loongarch_lbt {
|
||||
|
||||
@@ -12,9 +12,6 @@
|
||||
#ifndef _ASM_STACKPROTECTOR_H
|
||||
#define _ASM_STACKPROTECTOR_H
|
||||
|
||||
#include <linux/random.h>
|
||||
#include <linux/version.h>
|
||||
|
||||
extern unsigned long __stack_chk_guard;
|
||||
|
||||
/*
|
||||
@@ -25,11 +22,7 @@ extern unsigned long __stack_chk_guard;
|
||||
*/
|
||||
static __always_inline void boot_init_stack_canary(void)
|
||||
{
|
||||
unsigned long canary;
|
||||
|
||||
/* Try to get a semi random initial value. */
|
||||
get_random_bytes(&canary, sizeof(canary));
|
||||
canary ^= LINUX_VERSION_CODE;
|
||||
unsigned long canary = get_random_canary();
|
||||
|
||||
current->stack_canary = canary;
|
||||
__stack_chk_guard = current->stack_canary;
|
||||
|
||||
@@ -78,7 +78,11 @@ static inline void syscall_set_arguments(struct task_struct *task,
|
||||
|
||||
static inline int syscall_get_arch(struct task_struct *task)
|
||||
{
|
||||
#ifdef CONFIG_32BIT
|
||||
return AUDIT_ARCH_LOONGARCH32;
|
||||
#else
|
||||
return AUDIT_ARCH_LOONGARCH64;
|
||||
#endif
|
||||
}
|
||||
|
||||
static inline bool arch_syscall_is_vdso_sigreturn(struct pt_regs *regs)
|
||||
|
||||
@@ -19,5 +19,6 @@
|
||||
#define HWCAP_LOONGARCH_PTW (1 << 13)
|
||||
#define HWCAP_LOONGARCH_LSPW (1 << 14)
|
||||
#define HWCAP_LOONGARCH_SCQ (1 << 15)
|
||||
#define HWCAP_LOONGARCH_LAM_BH (1 << 16)
|
||||
|
||||
#endif /* _UAPI_ASM_HWCAP_H */
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/ptrace.h>
|
||||
#include <linux/cpu.h>
|
||||
#include <linux/smp.h>
|
||||
#include <linux/stddef.h>
|
||||
#include <linux/export.h>
|
||||
@@ -177,6 +178,10 @@ static void cpu_probe_common(struct cpuinfo_loongarch *c)
|
||||
c->options |= LOONGARCH_CPU_LAM;
|
||||
elf_hwcap |= HWCAP_LOONGARCH_LAM;
|
||||
}
|
||||
if (config & CPUCFG2_LAM_BH) {
|
||||
c->options |= LOONGARCH_CPU_LAM_BH;
|
||||
elf_hwcap |= HWCAP_LOONGARCH_LAM_BH;
|
||||
}
|
||||
if (config & CPUCFG2_SCQ) {
|
||||
c->options |= LOONGARCH_CPU_SCQ;
|
||||
elf_hwcap |= HWCAP_LOONGARCH_SCQ;
|
||||
@@ -402,3 +407,9 @@ void cpu_probe(void)
|
||||
|
||||
cpu_report();
|
||||
}
|
||||
|
||||
ssize_t cpu_show_spectre_v1(struct device *dev,
|
||||
struct device_attribute *attr, char *buf)
|
||||
{
|
||||
return sysfs_emit(buf, "Mitigation: __user pointer sanitization\n");
|
||||
}
|
||||
|
||||
@@ -97,7 +97,7 @@
|
||||
.endm
|
||||
|
||||
#ifdef CONFIG_32BIT
|
||||
.macro sc_save_fcc thread tmp0 tmp1
|
||||
.macro sc_save_fcc base tmp0 tmp1
|
||||
movcf2gr \tmp0, $fcc0
|
||||
move \tmp1, \tmp0
|
||||
movcf2gr \tmp0, $fcc1
|
||||
@@ -106,7 +106,7 @@
|
||||
bstrins.w \tmp1, \tmp0, 23, 16
|
||||
movcf2gr \tmp0, $fcc3
|
||||
bstrins.w \tmp1, \tmp0, 31, 24
|
||||
EX st.w \tmp1, \thread, THREAD_FCC
|
||||
EX st.w \tmp1, \base, 0
|
||||
movcf2gr \tmp0, $fcc4
|
||||
move \tmp1, \tmp0
|
||||
movcf2gr \tmp0, $fcc5
|
||||
@@ -115,11 +115,11 @@
|
||||
bstrins.w \tmp1, \tmp0, 23, 16
|
||||
movcf2gr \tmp0, $fcc7
|
||||
bstrins.w \tmp1, \tmp0, 31, 24
|
||||
EX st.w \tmp1, \thread, (THREAD_FCC + 4)
|
||||
EX st.w \tmp1, \base, 4
|
||||
.endm
|
||||
|
||||
.macro sc_restore_fcc thread tmp0 tmp1
|
||||
EX ld.w \tmp0, \thread, THREAD_FCC
|
||||
.macro sc_restore_fcc base tmp0 tmp1
|
||||
EX ld.w \tmp0, \base, 0
|
||||
bstrpick.w \tmp1, \tmp0, 7, 0
|
||||
movgr2cf $fcc0, \tmp1
|
||||
bstrpick.w \tmp1, \tmp0, 15, 8
|
||||
@@ -128,7 +128,7 @@
|
||||
movgr2cf $fcc2, \tmp1
|
||||
bstrpick.w \tmp1, \tmp0, 31, 24
|
||||
movgr2cf $fcc3, \tmp1
|
||||
EX ld.w \tmp0, \thread, (THREAD_FCC + 4)
|
||||
EX ld.w \tmp0, \base, 4
|
||||
bstrpick.w \tmp1, \tmp0, 7, 0
|
||||
movgr2cf $fcc4, \tmp1
|
||||
bstrpick.w \tmp1, \tmp0, 15, 8
|
||||
|
||||
@@ -209,6 +209,9 @@ int larch_insn_write(void *addr, u32 insn)
|
||||
int ret;
|
||||
unsigned long flags = 0;
|
||||
|
||||
if ((unsigned long)addr & 3)
|
||||
return -EINVAL;
|
||||
|
||||
raw_spin_lock_irqsave(&patch_lock, flags);
|
||||
ret = copy_to_kernel_nofault(addr, &insn, LOONGARCH_INSN_SIZE);
|
||||
raw_spin_unlock_irqrestore(&patch_lock, flags);
|
||||
@@ -221,9 +224,6 @@ int larch_insn_patch_text(void *addr, u32 insn)
|
||||
int ret;
|
||||
u32 *tp = addr;
|
||||
|
||||
if ((unsigned long)tp & 3)
|
||||
return -EINVAL;
|
||||
|
||||
ret = larch_insn_write(tp, insn);
|
||||
if (!ret)
|
||||
flush_icache_range((unsigned long)tp,
|
||||
|
||||
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Reference in New Issue
Block a user