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drm/amd/display: Flattening core_dc to dc

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-Flattening core_dc to dc

Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Harry Wentland <Harry.Wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Bhawanpreet Lakha
2017-09-26 18:16:40 -04:00
committed by Alex Deucher
parent 503a7c6f25
commit fb3466a450
51 changed files with 507 additions and 527 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/display/dc/calcs/dcn_calcs.c
+36 -37
View File
@@ -27,7 +27,6 @@
#include "dcn_calcs.h"
#include "dcn_calc_auto.h"
#include "dc.h"
#include "core_dc.h"
#include "dal_asic_id.h"
#include "resource.h"
@@ -399,7 +398,7 @@ static void pipe_ctx_to_e2e_pipe_params (
}
static void dcn_bw_calc_rq_dlg_ttu(
const struct core_dc *dc,
const struct dc *dc,
const struct dcn_bw_internal_vars *v,
struct pipe_ctx *pipe,
int in_idx)
@@ -674,45 +673,45 @@ static void calc_wm_sets_and_perf_params(
context->bw.dcn.watermarks.d = context->bw.dcn.watermarks.a;
}
static bool dcn_bw_apply_registry_override(struct core_dc *dc)
static bool dcn_bw_apply_registry_override(struct dc *dc)
{
bool updated = false;
kernel_fpu_begin();
if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->public.debug.sr_exit_time_ns
&& dc->public.debug.sr_exit_time_ns) {
if ((int)(dc->dcn_soc->sr_exit_time * 1000) != dc->debug.sr_exit_time_ns
&& dc->debug.sr_exit_time_ns) {
updated = true;
dc->dcn_soc->sr_exit_time = dc->public.debug.sr_exit_time_ns / 1000.0;
dc->dcn_soc->sr_exit_time = dc->debug.sr_exit_time_ns / 1000.0;
}
if ((int)(dc->dcn_soc->sr_enter_plus_exit_time * 1000)
!= dc->public.debug.sr_enter_plus_exit_time_ns
&& dc->public.debug.sr_enter_plus_exit_time_ns) {
!= dc->debug.sr_enter_plus_exit_time_ns
&& dc->debug.sr_enter_plus_exit_time_ns) {
updated = true;
dc->dcn_soc->sr_enter_plus_exit_time =
dc->public.debug.sr_enter_plus_exit_time_ns / 1000.0;
dc->debug.sr_enter_plus_exit_time_ns / 1000.0;
}
if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->public.debug.urgent_latency_ns
&& dc->public.debug.urgent_latency_ns) {
if ((int)(dc->dcn_soc->urgent_latency * 1000) != dc->debug.urgent_latency_ns
&& dc->debug.urgent_latency_ns) {
updated = true;
dc->dcn_soc->urgent_latency = dc->public.debug.urgent_latency_ns / 1000.0;
dc->dcn_soc->urgent_latency = dc->debug.urgent_latency_ns / 1000.0;
}
if ((int)(dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency * 1000)
!= dc->public.debug.percent_of_ideal_drambw
&& dc->public.debug.percent_of_ideal_drambw) {
!= dc->debug.percent_of_ideal_drambw
&& dc->debug.percent_of_ideal_drambw) {
updated = true;
dc->dcn_soc->percent_of_ideal_drambw_received_after_urg_latency =
dc->public.debug.percent_of_ideal_drambw;
dc->debug.percent_of_ideal_drambw;
}
if ((int)(dc->dcn_soc->dram_clock_change_latency * 1000)
!= dc->public.debug.dram_clock_change_latency_ns
&& dc->public.debug.dram_clock_change_latency_ns) {
!= dc->debug.dram_clock_change_latency_ns
&& dc->debug.dram_clock_change_latency_ns) {
updated = true;
dc->dcn_soc->dram_clock_change_latency =
dc->public.debug.dram_clock_change_latency_ns / 1000.0;
dc->debug.dram_clock_change_latency_ns / 1000.0;
}
kernel_fpu_end();
@@ -720,7 +719,7 @@ static bool dcn_bw_apply_registry_override(struct core_dc *dc)
}
bool dcn_validate_bandwidth(
const struct core_dc *dc,
struct dc *dc,
struct validate_context *context)
{
const struct resource_pool *pool = dc->res_pool;
@@ -730,8 +729,8 @@ bool dcn_validate_bandwidth(
bool bw_limit_pass;
float bw_limit;
if (dcn_bw_apply_registry_override(DC_TO_CORE(&dc->public)))
dcn_bw_sync_calcs_and_dml(DC_TO_CORE(&dc->public));
if (dcn_bw_apply_registry_override(dc))
dcn_bw_sync_calcs_and_dml(dc);
memset(v, 0, sizeof(*v));
kernel_fpu_begin();
@@ -850,7 +849,7 @@ bool dcn_validate_bandwidth(
v->phyclk_per_state[1] = v->phyclkv_mid0p72;
v->phyclk_per_state[0] = v->phyclkv_min0p65;
if (dc->public.debug.disable_pipe_split) {
if (dc->debug.disable_pipe_split) {
v->max_dispclk[0] = v->max_dppclk_vmin0p65;
}
@@ -982,15 +981,15 @@ bool dcn_validate_bandwidth(
mode_support_and_system_configuration(v);
if (v->voltage_level == 0 &&
(dc->public.debug.sr_exit_time_dpm0_ns
|| dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)) {
struct core_dc *dc_core = DC_TO_CORE(&dc->public);
(dc->debug.sr_exit_time_dpm0_ns
|| dc->debug.sr_enter_plus_exit_time_dpm0_ns)) {
struct dc *dc_core = dc;
if (dc->public.debug.sr_enter_plus_exit_time_dpm0_ns)
if (dc->debug.sr_enter_plus_exit_time_dpm0_ns)
v->sr_enter_plus_exit_time =
dc->public.debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
if (dc->public.debug.sr_exit_time_dpm0_ns)
v->sr_exit_time = dc->public.debug.sr_exit_time_dpm0_ns / 1000.0f;
dc->debug.sr_enter_plus_exit_time_dpm0_ns / 1000.0f;
if (dc->debug.sr_exit_time_dpm0_ns)
v->sr_exit_time = dc->debug.sr_exit_time_dpm0_ns / 1000.0f;
dc_core->dml.soc.sr_enter_plus_exit_time_us = v->sr_enter_plus_exit_time;
dc_core->dml.soc.sr_exit_time_us = v->sr_exit_time;
mode_support_and_system_configuration(v);
@@ -1020,7 +1019,7 @@ bool dcn_validate_bandwidth(
context->bw.dcn.calc_clk.dcfclk_deep_sleep_khz = (int)(v->dcf_clk_deep_sleep * 1000);
context->bw.dcn.calc_clk.dcfclk_khz = (int)(v->dcfclk * 1000);
context->bw.dcn.calc_clk.dispclk_khz = (int)(v->dispclk * 1000);
if (dc->public.debug.max_disp_clk == true)
if (dc->debug.max_disp_clk == true)
context->bw.dcn.calc_clk.dispclk_khz = (int)(dc->dcn_soc->max_dispclk_vmax0p9 * 1000);
context->bw.dcn.calc_clk.dppclk_div = (int)(v->dispclk_dppclk_ratio) == 2;
@@ -1109,13 +1108,13 @@ bool dcn_validate_bandwidth(
input_idx++;
}
if (dc->public.debug.use_dml_wm)
if (dc->debug.use_dml_wm)
dcn_dml_wm_override(v, (struct display_mode_lib *)
&dc->dml, context, pool);
}
if (v->voltage_level == 0) {
struct core_dc *dc_core = DC_TO_CORE(&dc->public);
struct dc *dc_core = dc;
dc_core->dml.soc.sr_enter_plus_exit_time_us =
dc_core->dcn_soc->sr_enter_plus_exit_time;
@@ -1138,7 +1137,7 @@ bool dcn_validate_bandwidth(
}
unsigned int dcn_find_normalized_clock_vdd_Level(
const struct core_dc *dc,
const struct dc *dc,
enum dm_pp_clock_type clocks_type,
int clocks_in_khz)
{
@@ -1228,7 +1227,7 @@ unsigned int dcn_find_normalized_clock_vdd_Level(
}
unsigned int dcn_find_dcfclk_suits_all(
const struct core_dc *dc,
const struct dc *dc,
struct clocks_value *clocks)
{
unsigned vdd_level, vdd_level_temp;
@@ -1270,7 +1269,7 @@ unsigned int dcn_find_dcfclk_suits_all(
return dcf_clk;
}
void dcn_bw_update_from_pplib(struct core_dc *dc)
void dcn_bw_update_from_pplib(struct dc *dc)
{
struct dc_context *ctx = dc->ctx;
struct dm_pp_clock_levels_with_voltage clks = {0};
@@ -1310,7 +1309,7 @@ void dcn_bw_update_from_pplib(struct core_dc *dc)
kernel_fpu_end();
}
void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc)
void dcn_bw_notify_pplib_of_wm_ranges(struct dc *dc)
{
struct dm_pp_wm_sets_with_clock_ranges_soc15 clk_ranges = {0};
int max_fclk_khz, nom_fclk_khz, min_fclk_khz, max_dcfclk_khz,
@@ -1388,7 +1387,7 @@ void dcn_bw_notify_pplib_of_wm_ranges(struct core_dc *dc)
dm_pp_notify_wm_clock_changes_soc15(dc->ctx, &clk_ranges);
}
void dcn_bw_sync_calcs_and_dml(struct core_dc *dc)
void dcn_bw_sync_calcs_and_dml(struct dc *dc)
{
kernel_fpu_begin();
dm_logger_write(dc->ctx->logger, LOG_BANDWIDTH_CALCS,
drivers/gpu/drm/amd/display/dc/core/dc.c
+81 -81
View File
File diff suppressed because it is too large Load Diff
drivers/gpu/drm/amd/display/dc/core/dc_debug.c
+10 -10
View File
@@ -37,12 +37,12 @@
} while (0)
void pre_surface_trace(
const struct dc *dc,
struct dc *dc,
const struct dc_plane_state *const *plane_states,
int surface_count)
{
int i;
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
for (i = 0; i < surface_count; i++) {
@@ -158,12 +158,12 @@ void pre_surface_trace(
}
void update_surface_trace(
const struct dc *dc,
struct dc *dc,
const struct dc_surface_update *updates,
int surface_count)
{
int i;
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
for (i = 0; i < surface_count; i++) {
@@ -279,9 +279,9 @@ void update_surface_trace(
SURFACE_TRACE("\n");
}
void post_surface_trace(const struct dc *dc)
void post_surface_trace(struct dc *dc)
{
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
SURFACE_TRACE("post surface process.\n");
@@ -289,11 +289,11 @@ void post_surface_trace(const struct dc *dc)
}
void context_timing_trace(
const struct dc *dc,
struct dc *dc,
struct resource_context *res_ctx)
{
int i;
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
int h_pos[MAX_PIPES], v_pos[MAX_PIPES];
struct crtc_position position;
@@ -328,11 +328,11 @@ void context_timing_trace(
}
void context_clock_trace(
const struct dc *dc,
struct dc *dc,
struct validate_context *context)
{
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc *core_dc = dc;
struct dal_logger *logger = core_dc->ctx->logger;
CLOCK_TRACE("Current: dispclk_khz:%d dppclk_div:%d dcfclk_khz:%d\n"
drivers/gpu/drm/amd/display/dc/core/dc_hw_sequencer.c
+1 -2
View File
@@ -25,7 +25,6 @@
#include "dm_services.h"
#include "core_types.h"
#include "core_dc.h"
#include "timing_generator.h"
#include "hw_sequencer.h"
@@ -55,7 +54,7 @@ static const struct tg_color black_color_format[] = {
};
void color_space_to_black_color(
const struct core_dc *dc,
const struct dc *dc,
enum dc_color_space colorspace,
struct tg_color *black_color)
{
drivers/gpu/drm/amd/display/dc/core/dc_link.c
+9 -10
View File
@@ -26,14 +26,13 @@
#include "dm_services.h"
#include "dm_helpers.h"
#include "dc.h"
#include "core_dc.h"
#include "grph_object_id.h"
#include "gpio_service_interface.h"
#include "core_status.h"
#include "dc_link_dp.h"
#include "dc_link_ddc.h"
#include "link_hwss.h"
#include "stream_encoder.h"
#include "link_encoder.h"
#include "hw_sequencer.h"
#include "resource.h"
@@ -1392,7 +1391,7 @@ enum dc_status dc_link_validate_mode_timing(
bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
uint32_t frame_ramp, const struct dc_stream_state *stream)
{
struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
struct dc *core_dc = link->ctx->dc;
struct abm *abm = core_dc->res_pool->abm;
unsigned int controller_id = 0;
int i;
@@ -1431,7 +1430,7 @@ bool dc_link_set_backlight_level(const struct dc_link *link, uint32_t level,
bool dc_link_set_abm_disable(const struct dc_link *link)
{
struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
struct dc *core_dc = link->ctx->dc;
struct abm *abm = core_dc->res_pool->abm;
if ((abm == NULL) || (abm->funcs->set_backlight_level == NULL))
@@ -1445,7 +1444,7 @@ bool dc_link_set_abm_disable(const struct dc_link *link)
bool dc_link_set_psr_enable(const struct dc_link *link, bool enable)
{
struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
struct dc *core_dc = link->ctx->dc;
struct dmcu *dmcu = core_dc->res_pool->dmcu;
if (dmcu != NULL && link->psr_enabled)
@@ -1456,7 +1455,7 @@ bool dc_link_set_psr_enable(const struct dc_link *link, bool enable)
bool dc_link_get_psr_state(const struct dc_link *link, uint32_t *psr_state)
{
struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
struct dc *core_dc = link->ctx->dc;
struct dmcu *dmcu = core_dc->res_pool->dmcu;
if (dmcu != NULL && link->psr_enabled)
@@ -1469,7 +1468,7 @@ bool dc_link_setup_psr(struct dc_link *link,
const struct dc_stream_state *stream, struct psr_config *psr_config,
struct psr_context *psr_context)
{
struct core_dc *core_dc = DC_TO_CORE(link->ctx->dc);
struct dc *core_dc = link->ctx->dc;
struct dmcu *dmcu = core_dc->res_pool->dmcu;
int i;
@@ -1874,7 +1873,7 @@ static enum dc_status deallocate_mst_payload(struct pipe_ctx *pipe_ctx)
void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
{
struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc);
struct dc *core_dc = pipe_ctx->stream->ctx->dc;
enum dc_status status = enable_link(pipe_ctx);
@@ -1907,7 +1906,7 @@ void core_link_enable_stream(struct pipe_ctx *pipe_ctx)
void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
{
struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc);
struct dc *core_dc = pipe_ctx->stream->ctx->dc;
if (pipe_ctx->stream->signal == SIGNAL_TYPE_DISPLAY_PORT_MST)
deallocate_mst_payload(pipe_ctx);
@@ -1919,7 +1918,7 @@ void core_link_disable_stream(struct pipe_ctx *pipe_ctx)
void core_link_set_avmute(struct pipe_ctx *pipe_ctx, bool enable)
{
struct core_dc *core_dc = DC_TO_CORE(pipe_ctx->stream->ctx->dc);
struct dc *core_dc = pipe_ctx->stream->ctx->dc;
if (pipe_ctx->stream->signal != SIGNAL_TYPE_HDMI_TYPE_A)
return;
drivers/gpu/drm/amd/display/dc/core/dc_link_dp.c
-1
View File
@@ -10,7 +10,6 @@
#include "core_status.h"
#include "dpcd_defs.h"
#include "core_dc.h"
#include "resource.h"
/* maximum pre emphasis level allowed for each voltage swing level*/
drivers/gpu/drm/amd/display/dc/core/dc_link_hwss.c
+1 -1
View File
@@ -3,7 +3,7 @@
#include "dm_services.h"
#include "dc.h"
#include "inc/core_dc.h"
#include "inc/core_types.h"
#include "include/ddc_service_types.h"
#include "include/i2caux_interface.h"
#include "link_hwss.h"
drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+11 -11
View File
@@ -92,7 +92,7 @@ enum dce_version resource_parse_asic_id(struct hw_asic_id asic_id)
}
struct resource_pool *dc_create_resource_pool(
struct core_dc *dc,
struct dc *dc,
int num_virtual_links,
enum dce_version dc_version,
struct hw_asic_id asic_id)
@@ -153,7 +153,7 @@ struct resource_pool *dc_create_resource_pool(
return res_pool;
}
void dc_destroy_resource_pool(struct core_dc *dc)
void dc_destroy_resource_pool(struct dc *dc)
{
if (dc) {
if (dc->res_pool)
@@ -193,7 +193,7 @@ static void update_num_audio(
bool resource_construct(
unsigned int num_virtual_links,
struct core_dc *dc,
struct dc *dc,
struct resource_pool *pool,
const struct resource_create_funcs *create_funcs)
{
@@ -892,7 +892,7 @@ bool resource_build_scaling_params(struct pipe_ctx *pipe_ctx)
enum dc_status resource_build_scaling_params_for_context(
const struct core_dc *dc,
const struct dc *dc,
struct validate_context *context)
{
int i;
@@ -1438,7 +1438,7 @@ static void calculate_phy_pix_clks(struct dc_stream_state *stream)
}
enum dc_status resource_map_pool_resources(
const struct core_dc *dc,
const struct dc *dc,
struct validate_context *context,
struct validate_context *old_context)
{
@@ -2316,7 +2316,7 @@ void resource_build_info_frame(struct pipe_ctx *pipe_ctx)
}
enum dc_status resource_map_clock_resources(
const struct core_dc *dc,
const struct dc *dc,
struct validate_context *context,
struct validate_context *old_context)
{
@@ -2343,7 +2343,7 @@ enum dc_status resource_map_clock_resources(
else {
pipe_ctx->clock_source = NULL;
if (!dc->public.config.disable_disp_pll_sharing)
if (!dc->config.disable_disp_pll_sharing)
resource_find_used_clk_src_for_sharing(
&context->res_ctx,
pipe_ctx);
@@ -2515,9 +2515,9 @@ void resource_build_bit_depth_reduction_params(struct dc_stream_state *stream,
fmt_bit_depth->pixel_encoding = pixel_encoding;
}
bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream)
bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream)
{
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc *core_dc = dc;
struct dc_context *dc_ctx = core_dc->ctx;
struct dc_link *link = stream->sink->link;
struct timing_generator *tg = core_dc->res_pool->timing_generators[0];
@@ -2547,9 +2547,9 @@ bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream)
return res == DC_OK;
}
bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state)
bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state)
{
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc *core_dc = dc;
/* TODO For now validates pixel format only */
if (core_dc->res_pool->funcs->validate_plane)
drivers/gpu/drm/amd/display/dc/core/dc_stream.c
+7 -7
View File
@@ -144,7 +144,7 @@ struct dc_stream_status *dc_stream_get_status(
struct dc_stream_state *stream)
{
uint8_t i;
struct core_dc *dc = DC_TO_CORE(stream->ctx->dc);
struct dc *dc = stream->ctx->dc;
for (i = 0; i < dc->current_context->stream_count; i++) {
if (stream == dc->current_context->streams[i]) {
@@ -163,7 +163,7 @@ bool dc_stream_set_cursor_attributes(
const struct dc_cursor_attributes *attributes)
{
int i;
struct core_dc *core_dc;
struct dc *core_dc;
struct resource_context *res_ctx;
if (NULL == stream) {
@@ -175,7 +175,7 @@ bool dc_stream_set_cursor_attributes(
return false;
}
core_dc = DC_TO_CORE(stream->ctx->dc);
core_dc = stream->ctx->dc;
res_ctx = &core_dc->current_context->res_ctx;
for (i = 0; i < MAX_PIPES; i++) {
@@ -198,7 +198,7 @@ bool dc_stream_set_cursor_position(
const struct dc_cursor_position *position)
{
int i;
struct core_dc *core_dc;
struct dc *core_dc;
struct resource_context *res_ctx;
if (NULL == stream) {
@@ -211,7 +211,7 @@ bool dc_stream_set_cursor_position(
return false;
}
core_dc = DC_TO_CORE(stream->ctx->dc);
core_dc = stream->ctx->dc;
res_ctx = &core_dc->current_context->res_ctx;
for (i = 0; i < MAX_PIPES; i++) {
@@ -246,7 +246,7 @@ bool dc_stream_set_cursor_position(
uint32_t dc_stream_get_vblank_counter(const struct dc_stream_state *stream)
{
uint8_t i;
struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc);
struct dc *core_dc = stream->ctx->dc;
struct resource_context *res_ctx =
&core_dc->current_context->res_ctx;
@@ -270,7 +270,7 @@ bool dc_stream_get_scanoutpos(const struct dc_stream_state *stream,
{
uint8_t i;
bool ret = false;
struct core_dc *core_dc = DC_TO_CORE(stream->ctx->dc);
struct dc *core_dc = stream->ctx->dc;
struct resource_context *res_ctx =
&core_dc->current_context->res_ctx;
drivers/gpu/drm/amd/display/dc/core/dc_surface.c
+5 -5
View File
@@ -28,7 +28,7 @@
#include "dc.h"
/* DC core (private) */
#include "core_dc.h"
#include "core_types.h"
#include "transform.h"
/*******************************************************************************
@@ -64,9 +64,9 @@ void enable_surface_flip_reporting(struct dc_plane_state *plane_state,
/*register_flip_interrupt(surface);*/
}
struct dc_plane_state *dc_create_plane_state(const struct dc *dc)
struct dc_plane_state *dc_create_plane_state(struct dc *dc)
{
struct core_dc *core_dc = DC_TO_CORE(dc);
struct dc *core_dc = dc;
struct dc_plane_state *plane_state = dm_alloc(sizeof(*plane_state));
@@ -91,7 +91,7 @@ const struct dc_plane_status *dc_plane_get_status(
const struct dc_plane_state *plane_state)
{
const struct dc_plane_status *plane_status;
struct core_dc *core_dc;
struct dc *core_dc;
int i;
if (!plane_state ||
@@ -102,7 +102,7 @@ const struct dc_plane_status *dc_plane_get_status(
}
plane_status = &plane_state->status;
core_dc = DC_TO_CORE(plane_state->ctx->dc);
core_dc = plane_state->ctx->dc;
if (core_dc->current_context == NULL)
return NULL;
drivers/gpu/drm/amd/display/dc/dc.h
+56 -15
View File
@@ -34,14 +34,19 @@
#include "grph_object_ctrl_defs.h"
#include <inc/hw/opp.h>
#include "inc/hw_sequencer.h"
#include "dml/display_mode_lib.h"
#define MAX_SURFACES 3
#define MAX_STREAMS 6
#define MAX_SINKS_PER_LINK 4
/*******************************************************************************
* Display Core Interfaces
******************************************************************************/
struct dc_caps {
uint32_t max_streams;
uint32_t max_links;
@@ -186,7 +191,9 @@ struct dc_debug {
bool disable_psr;
bool force_abm_enable;
};
struct validate_context;
struct resource_pool;
struct dce_hwseq;
struct dc {
struct dc_caps caps;
struct dc_cap_funcs cap_funcs;
@@ -194,6 +201,40 @@ struct dc {
struct dc_link_funcs link_funcs;
struct dc_config config;
struct dc_debug debug;
struct dc_context *ctx;
uint8_t link_count;
struct dc_link *links[MAX_PIPES * 2];
struct validate_context *current_context;
struct resource_pool *res_pool;
/* Display Engine Clock levels */
struct dm_pp_clock_levels sclk_lvls;
/* Inputs into BW and WM calculations. */
struct bw_calcs_dceip *bw_dceip;
struct bw_calcs_vbios *bw_vbios;
#ifdef CONFIG_DRM_AMD_DC_DCN1_0
struct dcn_soc_bounding_box *dcn_soc;
struct dcn_ip_params *dcn_ip;
struct display_mode_lib dml;
#endif
/* HW functions */
struct hw_sequencer_funcs hwss;
struct dce_hwseq *hwseq;
/* temp store of dm_pp_display_configuration
* to compare to see if display config changed
*/
struct dm_pp_display_configuration prev_display_config;
/* FBC compressor */
#ifdef ENABLE_FBC
struct compressor *fbc_compressor;
#endif
};
enum frame_buffer_mode {
@@ -384,7 +425,7 @@ struct dc_surface_update {
/*
* Create a new surface with default parameters;
*/
struct dc_plane_state *dc_create_plane_state(const struct dc *dc);
struct dc_plane_state *dc_create_plane_state(struct dc *dc);
const struct dc_plane_status *dc_plane_get_status(
const struct dc_plane_state *plane_state);
@@ -558,8 +599,8 @@ void dc_stream_log(
struct dal_logger *dc_logger,
enum dc_log_type log_type);
uint8_t dc_get_current_stream_count(const struct dc *dc);
struct dc_stream_state *dc_get_stream_at_index(const struct dc *dc, uint8_t i);
uint8_t dc_get_current_stream_count(struct dc *dc);
struct dc_stream_state *dc_get_stream_at_index(struct dc *dc, uint8_t i);
/*
* Return the current frame counter.
@@ -585,9 +626,9 @@ struct dc_validation_set {
uint8_t plane_count;
};
bool dc_validate_stream(const struct dc *dc, struct dc_stream_state *stream);
bool dc_validate_stream(struct dc *dc, struct dc_stream_state *stream);
bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_state);
bool dc_validate_plane(struct dc *dc, const struct dc_plane_state *plane_state);
/*
* This function takes a set of resources and checks that they are cofunctional.
*
@@ -595,12 +636,12 @@ bool dc_validate_plane(const struct dc *dc, const struct dc_plane_state *plane_s
* No hardware is programmed for call. Only validation is done.
*/
struct validate_context *dc_get_validate_context(
const struct dc *dc,
struct dc *dc,
const struct dc_validation_set set[],
uint8_t set_count);
bool dc_validate_resources(
const struct dc *dc,
struct dc *dc,
const struct dc_validation_set set[],
uint8_t set_count);
@@ -613,7 +654,7 @@ bool dc_validate_resources(
*/
bool dc_validate_guaranteed(
const struct dc *dc,
struct dc *dc,
struct dc_stream_state *stream);
void dc_resource_validate_ctx_copy_construct(
@@ -764,7 +805,7 @@ struct dc_link {
/* Private to DC core */
const struct core_dc *dc;
const struct dc *dc;
struct dc_context *ctx;
@@ -795,9 +836,9 @@ const struct dc_link_status *dc_link_get_status(const struct dc_link *dc_link);
* boot time. They cannot be created or destroyed.
* Use dc_get_caps() to get number of links.
*/
struct dc_link *dc_get_link_at_index(const struct dc *dc, uint32_t link_index);
struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index);
struct dwbc *dc_get_dwb_at_pipe(const struct dc *dc, uint32_t pipe);
struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe);
/* Return id of physical connector represented by a dc_link at link_index.*/
const struct graphics_object_id dc_get_link_id_at_index(
@@ -948,7 +989,7 @@ enum dc_irq_source dc_interrupt_to_irq_source(
struct dc *dc,
uint32_t src_id,
uint32_t ext_id);
void dc_interrupt_set(const struct dc *dc, enum dc_irq_source src, bool enable);
void dc_interrupt_set(struct dc *dc, enum dc_irq_source src, bool enable);
void dc_interrupt_ack(struct dc *dc, enum dc_irq_source src);
enum dc_irq_source dc_get_hpd_irq_source_at_index(
struct dc *dc, uint32_t link_index);
@@ -960,7 +1001,7 @@ enum dc_irq_source dc_get_hpd_irq_source_at_index(
void dc_set_power_state(
struct dc *dc,
enum dc_acpi_cm_power_state power_state);
void dc_resume(const struct dc *dc);
void dc_resume(struct dc *dc);
/*
* DPCD access interfaces
drivers/gpu/drm/amd/display/dc/dce/dce_clock_source.c
+2 -3
View File
@@ -34,7 +34,6 @@
#include "dce_clock_source.h"
#include "core_dc.h"
#include "reg_helper.h"
#define REG(reg)\
@@ -609,7 +608,7 @@ static uint32_t dce110_get_pll_pixel_rate_in_hz(
struct pll_settings *pll_settings)
{
uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc);
struct dc *dc_core = cs->ctx->dc;
struct validate_context *context = dc_core->current_context;
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];
@@ -624,7 +623,7 @@ static uint32_t dce110_get_dp_pixel_rate_from_combo_phy_pll(
struct pll_settings *pll_settings)
{
uint32_t inst = pix_clk_params->controller_id - CONTROLLER_ID_D0;
struct core_dc *dc_core = DC_TO_CORE(cs->ctx->dc);
struct dc *dc_core = cs->ctx->dc;
struct validate_context *context = dc_core->current_context;
struct pipe_ctx *pipe_ctx = &context->res_ctx.pipe_ctx[inst];
drivers/gpu/drm/amd/display/dc/dce/dce_clocks.c
+4 -6
View File
@@ -29,14 +29,12 @@
#include "fixed32_32.h"
#include "bios_parser_interface.h"
#include "dc.h"
#include "core_dc.h"
#include "dce_abm.h"
#include "dmcu.h"
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
#include "dcn_calcs.h"
#include "core_dc.h"
#endif
#include "core_types.h"
#define TO_DCE_CLOCKS(clocks)\
@@ -368,7 +366,7 @@ static int dce_psr_set_clock(
{
struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
struct dc_context *ctx = clk_dce->base.ctx;
struct core_dc *core_dc = DC_TO_CORE(ctx->dc);
struct dc *core_dc = ctx->dc;
struct dmcu *dmcu = core_dc->res_pool->dmcu;
int actual_clk_khz = requested_clk_khz;
@@ -385,7 +383,7 @@ static int dce112_set_clock(
struct dce_disp_clk *clk_dce = TO_DCE_CLOCKS(clk);
struct bp_set_dce_clock_parameters dce_clk_params;
struct dc_bios *bp = clk->ctx->dc_bios;
struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc);
struct dc *core_dc = clk->ctx->dc;
struct abm *abm = core_dc->res_pool->abm;
struct dmcu *dmcu = core_dc->res_pool->dmcu;
int actual_clock = requested_clk_khz;
@@ -621,7 +619,7 @@ static bool dce_apply_clock_voltage_request(
if (send_request) {
#if defined(CONFIG_DRM_AMD_DC_DCN1_0)
if (clk->ctx->dce_version >= DCN_VERSION_1_0) {
struct core_dc *core_dc = DC_TO_CORE(clk->ctx->dc);
struct dc *core_dc = clk->ctx->dc;
/*use dcfclk request voltage*/
clock_voltage_req.clk_type = DM_PP_CLOCK_TYPE_DCFCLK;
clock_voltage_req.clocks_in_khz =
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.c
+2 -2
View File
@@ -26,7 +26,7 @@
#include "dce_hwseq.h"
#include "reg_helper.h"
#include "hw_sequencer.h"
#include "core_dc.h"
#include "core_types.h"
#define CTX \
hws->ctx
@@ -44,7 +44,7 @@ void dce_enable_fe_clock(struct dce_hwseq *hws,
DCFE_CLOCK_ENABLE, enable);
}
void dce_pipe_control_lock(struct core_dc *dc,
void dce_pipe_control_lock(struct dc *dc,
struct pipe_ctx *pipe,
bool lock)
{
drivers/gpu/drm/amd/display/dc/dce/dce_hwseq.h
+1 -1
View File
@@ -528,7 +528,7 @@ enum blnd_mode {
void dce_enable_fe_clock(struct dce_hwseq *hwss,
unsigned int inst, bool enable);
void dce_pipe_control_lock(struct core_dc *dc,
void dce_pipe_control_lock(struct dc *dc,
struct pipe_ctx *pipe,
bool lock);
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.c
+4 -5
View File
@@ -24,7 +24,6 @@
*/
#include "dm_services.h"
#include "dc.h"
#include "core_dc.h"
#include "core_types.h"
#include "hw_sequencer.h"
#include "dce100_hw_sequencer.h"
@@ -71,7 +70,7 @@ static const struct dce100_hw_seq_reg_offsets reg_offsets[] = {
/***************************PIPE_CONTROL***********************************/
static bool dce100_enable_display_power_gating(
struct core_dc *dc,
struct dc *dc,
uint8_t controller_id,
struct dc_bios *dcb,
enum pipe_gating_control power_gating)
@@ -107,7 +106,7 @@ static bool dce100_enable_display_power_gating(
}
static void dce100_pplib_apply_display_requirements(
struct core_dc *dc,
struct dc *dc,
struct validate_context *context)
{
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
@@ -127,7 +126,7 @@ static void dce100_pplib_apply_display_requirements(
}
void dce100_set_bandwidth(
struct core_dc *dc,
struct dc *dc,
struct validate_context *context,
bool decrease_allowed)
{
@@ -143,7 +142,7 @@ void dce100_set_bandwidth(
/**************************************************************************/
bool dce100_hw_sequencer_construct(struct core_dc *dc)
bool dce100_hw_sequencer_construct(struct dc *dc)
{
dce110_hw_sequencer_construct(dc);
drivers/gpu/drm/amd/display/dc/dce100/dce100_hw_sequencer.h
+3 -3
View File
@@ -28,13 +28,13 @@
#include "core_types.h"
struct core_dc;
struct dc;
struct validate_context;
bool dce100_hw_sequencer_construct(struct core_dc *dc);
bool dce100_hw_sequencer_construct(struct dc *dc);
void dce100_set_bandwidth(
struct core_dc *dc,
struct dc *dc,
struct validate_context *context,
bool decrease_allowed);
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.c
+11 -11
View File
@@ -652,7 +652,7 @@ static void destruct(struct dce110_resource_pool *pool)
}
static enum dc_status build_mapped_resource(
const struct core_dc *dc,
const struct dc *dc,
struct validate_context *context,
struct validate_context *old_context)
{
@@ -688,7 +688,7 @@ static enum dc_status build_mapped_resource(
}
bool dce100_validate_bandwidth(
const struct core_dc *dc,
struct dc *dc,
struct validate_context *context)
{
/* TODO implement when needed but for now hardcode max value*/
@@ -720,7 +720,7 @@ static bool dce100_validate_surface_sets(
}
enum dc_status dce100_validate_with_context(
const struct core_dc *dc,
struct dc *dc,
const struct dc_validation_set set[],
int set_count,
struct validate_context *context,
@@ -764,7 +764,7 @@ enum dc_status dce100_validate_with_context(
}
enum dc_status dce100_validate_guaranteed(
const struct core_dc *dc,
struct dc *dc,
struct dc_stream_state *dc_stream,
struct validate_context *context)
{
@@ -784,7 +784,7 @@ enum dc_status dce100_validate_guaranteed(
if (result == DC_OK) {
validate_guaranteed_copy_streams(
context, dc->public.caps.max_streams);
context, dc->caps.max_streams);
result = resource_build_scaling_params_for_context(dc, context);
}
@@ -824,7 +824,7 @@ static const struct resource_funcs dce100_res_pool_funcs = {
static bool construct(
uint8_t num_virtual_links,
struct core_dc *dc,
struct dc *dc,
struct dce110_resource_pool *pool)
{
unsigned int i;
@@ -909,9 +909,9 @@ static bool construct(
*************************************************/
pool->base.underlay_pipe_index = NO_UNDERLAY_PIPE;
pool->base.pipe_count = res_cap.num_timing_generator;
dc->public.caps.max_downscale_ratio = 200;
dc->public.caps.i2c_speed_in_khz = 40;
dc->public.caps.max_cursor_size = 128;
dc->caps.max_downscale_ratio = 200;
dc->caps.i2c_speed_in_khz = 40;
dc->caps.max_cursor_size = 128;
for (i = 0; i < pool->base.pipe_count; i++) {
pool->base.timing_generators[i] =
@@ -958,7 +958,7 @@ static bool construct(
}
}
dc->public.caps.max_planes = pool->base.pipe_count;
dc->caps.max_planes = pool->base.pipe_count;
if (!resource_construct(num_virtual_links, dc, &pool->base,
&res_create_funcs))
@@ -978,7 +978,7 @@ res_create_fail:
struct resource_pool *dce100_create_resource_pool(
uint8_t num_virtual_links,
struct core_dc *dc)
struct dc *dc)
{
struct dce110_resource_pool *pool =
dm_alloc(sizeof(struct dce110_resource_pool));
drivers/gpu/drm/amd/display/dc/dce100/dce100_resource.h
+2 -2
View File
@@ -8,13 +8,13 @@
#ifndef DCE100_RESOURCE_H_
#define DCE100_RESOURCE_H_
struct core_dc;
struct dc;
struct resource_pool;
struct dc_validation_set;
struct resource_pool *dce100_create_resource_pool(
uint8_t num_virtual_links,
struct core_dc *dc);
struct dc *dc);
enum dc_status dce100_validate_plane(const struct dc_plane_state *plane_state);
drivers/gpu/drm/amd/display/dc/dce110/dce110_hw_sequencer.c
+36 -36
View File
@@ -164,7 +164,7 @@ static void enable_display_pipe_clock_gating(
}
static bool dce110_enable_display_power_gating(
struct core_dc *dc,
struct dc *dc,
uint8_t controller_id,
struct dc_bios *dcb,
enum pipe_gating_control power_gating)
@@ -944,7 +944,7 @@ static void get_surface_visual_confirm_color(const struct pipe_ctx *pipe_ctx,
}
}
static void program_scaler(const struct core_dc *dc,
static void program_scaler(const struct dc *dc,
const struct pipe_ctx *pipe_ctx)
{
struct tg_color color = {0};
@@ -955,7 +955,7 @@ static void program_scaler(const struct core_dc *dc,
return;
#endif
if (dc->public.debug.surface_visual_confirm)
if (dc->debug.surface_visual_confirm)
get_surface_visual_confirm_color(pipe_ctx, &color);
else
color_space_to_black_color(dc,
@@ -979,7 +979,7 @@ static void program_scaler(const struct core_dc *dc,
static enum dc_status dce110_prog_pixclk_crtc_otg(
struct pipe_ctx *pipe_ctx,
struct validate_context *context,
struct core_dc *dc)
struct dc *dc)
{
struct dc_stream_state *stream = pipe_ctx->stream;
struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
@@ -1035,7 +1035,7 @@ static enum dc_status dce110_prog_pixclk_crtc_otg(
static enum dc_status apply_single_controller_ctx_to_hw(
struct pipe_ctx *pipe_ctx,
struct validate_context *context,
struct core_dc *dc)
struct dc *dc)
{
struct dc_stream_state *stream = pipe_ctx->stream;
struct pipe_ctx *pipe_ctx_old = &dc->current_context->res_ctx.
@@ -1146,7 +1146,7 @@ static enum dc_status apply_single_controller_ctx_to_hw(
/******************************************************************************/
static void power_down_encoders(struct core_dc *dc)
static void power_down_encoders(struct dc *dc)
{
int i;
@@ -1156,7 +1156,7 @@ static void power_down_encoders(struct core_dc *dc)
}
}
static void power_down_controllers(struct core_dc *dc)
static void power_down_controllers(struct dc *dc)
{
int i;
@@ -1166,7 +1166,7 @@ static void power_down_controllers(struct core_dc *dc)
}
}
static void power_down_clock_sources(struct core_dc *dc)
static void power_down_clock_sources(struct dc *dc)
{
int i;
@@ -1181,7 +1181,7 @@ static void power_down_clock_sources(struct core_dc *dc)
}
}
static void power_down_all_hw_blocks(struct core_dc *dc)
static void power_down_all_hw_blocks(struct dc *dc)
{
power_down_encoders(dc);
@@ -1196,7 +1196,7 @@ static void power_down_all_hw_blocks(struct core_dc *dc)
}
static void disable_vga_and_power_gate_all_controllers(
struct core_dc *dc)
struct dc *dc)
{
int i;
struct timing_generator *tg;
@@ -1224,7 +1224,7 @@ static void disable_vga_and_power_gate_all_controllers(
* 3. Enable power gating for controller
* 4. Set acc_mode_change bit (VBIOS will clear this bit when going to FSDOS)
*/
void dce110_enable_accelerated_mode(struct core_dc *dc)
void dce110_enable_accelerated_mode(struct dc *dc)
{
power_down_all_hw_blocks(dc);
@@ -1250,7 +1250,7 @@ static uint32_t compute_pstate_blackout_duration(
}
void dce110_set_displaymarks(
const struct core_dc *dc,
const struct dc *dc,
struct validate_context *context)
{
uint8_t i, num_pipes;
@@ -1316,7 +1316,7 @@ static void set_safe_displaymarks(
}
static void switch_dp_clock_sources(
const struct core_dc *dc,
const struct dc *dc,
struct resource_context *res_ctx)
{
uint8_t i;
@@ -1408,7 +1408,7 @@ static void set_static_screen_control(struct pipe_ctx **pipe_ctx,
* may read PLL register to get pixel clock
*/
static uint32_t get_max_pixel_clock_for_all_paths(
struct core_dc *dc,
struct dc *dc,
struct validate_context *context,
bool pre_mode_set)
{
@@ -1449,7 +1449,7 @@ static uint32_t get_max_pixel_clock_for_all_paths(
* etc support for dcn1.0
*/
static void apply_min_clocks(
struct core_dc *dc,
struct dc *dc,
struct validate_context *context,
enum dm_pp_clocks_state *clocks_state,
bool pre_mode_set)
@@ -1538,7 +1538,7 @@ static void apply_min_clocks(
/*
* Check if FBC can be enabled
*/
static enum dc_status validate_fbc(struct core_dc *dc,
static enum dc_status validate_fbc(struct dc *dc,
struct validate_context *context)
{
struct pipe_ctx *pipe_ctx =
@@ -1568,7 +1568,7 @@ static enum dc_status validate_fbc(struct core_dc *dc,
/*
* Enable FBC
*/
static enum dc_status enable_fbc(struct core_dc *dc,
static enum dc_status enable_fbc(struct dc *dc,
struct validate_context *context)
{
enum dc_status status = validate_fbc(dc, context);
@@ -1597,7 +1597,7 @@ static enum dc_status enable_fbc(struct core_dc *dc,
#endif
static enum dc_status apply_ctx_to_hw_fpga(
struct core_dc *dc,
struct dc *dc,
struct validate_context *context)
{
enum dc_status status = DC_ERROR_UNEXPECTED;
@@ -1627,7 +1627,7 @@ static enum dc_status apply_ctx_to_hw_fpga(
}
static void dce110_reset_hw_ctx_wrap(
struct core_dc *dc,
struct dc *dc,
struct validate_context *context)
{
int i;
@@ -1672,7 +1672,7 @@ static void dce110_reset_hw_ctx_wrap(
enum dc_status dce110_apply_ctx_to_hw(
struct core_dc *dc,
struct dc *dc,
struct validate_context *context)
{
struct dc_bios *dcb = dc->ctx->dc_bios;
@@ -1965,7 +1965,7 @@ static void set_default_colors(struct pipe_ctx *pipe_ctx)
* -------------------------------------------------|
*
******************************************************************************/
static void program_surface_visibility(const struct core_dc *dc,
static void program_surface_visibility(const struct dc *dc,
struct pipe_ctx *pipe_ctx)
{
enum blnd_mode blender_mode = BLND_MODE_CURRENT_PIPE;
@@ -2038,7 +2038,7 @@ static void program_gamut_remap(struct pipe_ctx *pipe_ctx)
* TODO REMOVE, USE UPDATE INSTEAD
*/
static void set_plane_config(
const struct core_dc *dc,
const struct dc *dc,
struct pipe_ctx *pipe_ctx,
struct resource_context *res_ctx)
{
@@ -2117,7 +2117,7 @@ static void set_plane_config(
if (mi->funcs->set_blank)
mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
if (dc->public.config.gpu_vm_support)
if (dc->config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
pipe_ctx->plane_res.mi,
plane_state->format,
@@ -2125,7 +2125,7 @@ static void set_plane_config(
plane_state->rotation);
}
static void update_plane_addr(const struct core_dc *dc,
static void update_plane_addr(const struct dc *dc,
struct pipe_ctx *pipe_ctx)
{
struct dc_plane_state *plane_state = pipe_ctx->plane_state;
@@ -2163,7 +2163,7 @@ void dce110_update_pending_status(struct pipe_ctx *pipe_ctx)
}
}
void dce110_power_down(struct core_dc *dc)
void dce110_power_down(struct dc *dc)
{
power_down_all_hw_blocks(dc);
disable_vga_and_power_gate_all_controllers(dc);
@@ -2208,7 +2208,7 @@ static bool wait_for_reset_trigger_to_occur(
/* Enable timing synchronization for a group of Timing Generators. */
static void dce110_enable_timing_synchronization(
struct core_dc *dc,
struct dc *dc,
int group_index,
int group_size,
struct pipe_ctx *grouped_pipes[])
@@ -2257,7 +2257,7 @@ static void dce110_enable_timing_synchronization(
DC_SYNC_INFO("GSL: Set-up complete.\n");
}
static void init_hw(struct core_dc *dc)
static void init_hw(struct dc *dc)
{
int i;
struct dc_bios *bp;
@@ -2394,7 +2394,7 @@ uint32_t dce110_get_min_vblank_time_us(const struct validate_context *context)
}
static int determine_sclk_from_bounding_box(
const struct core_dc *dc,
const struct dc *dc,
int required_sclk)
{
int i;
@@ -2420,7 +2420,7 @@ static int determine_sclk_from_bounding_box(
}
static void pplib_apply_display_requirements(
struct core_dc *dc,
struct dc *dc,
struct validate_context *context)
{
struct dm_pp_display_configuration *pp_display_cfg = &context->pp_display_cfg;
@@ -2474,7 +2474,7 @@ static void pplib_apply_display_requirements(
}
static void dce110_set_bandwidth(
struct core_dc *dc,
struct dc *dc,
struct validate_context *context,
bool decrease_allowed)
{
@@ -2491,7 +2491,7 @@ static void dce110_set_bandwidth(
}
static void dce110_program_front_end_for_pipe(
struct core_dc *dc, struct pipe_ctx *pipe_ctx)
struct dc *dc, struct pipe_ctx *pipe_ctx)
{
struct mem_input *mi = pipe_ctx->plane_res.mi;
struct pipe_ctx *old_pipe = NULL;
@@ -2572,7 +2572,7 @@ static void dce110_program_front_end_for_pipe(
if (mi->funcs->set_blank)
mi->funcs->set_blank(mi, pipe_ctx->plane_state->visible);
if (dc->public.config.gpu_vm_support)
if (dc->config.gpu_vm_support)
mi->funcs->mem_input_program_pte_vm(
pipe_ctx->plane_res.mi,
plane_state->format,
@@ -2618,7 +2618,7 @@ static void dce110_program_front_end_for_pipe(
}
static void dce110_apply_ctx_for_surface(
struct core_dc *dc,
struct dc *dc,
const struct dc_stream_state *stream,
int num_planes,
struct validate_context *context)
@@ -2648,7 +2648,7 @@ static void dce110_apply_ctx_for_surface(
}
}
static void dce110_power_down_fe(struct core_dc *dc, int fe_idx)
static void dce110_power_down_fe(struct dc *dc, int fe_idx)
{
/* Do not power down fe when stream is active on dce*/
if (dc->current_context->res_ctx.pipe_ctx[fe_idx].stream)
@@ -2662,7 +2662,7 @@ static void dce110_power_down_fe(struct core_dc *dc, int fe_idx)
}
static void dce110_wait_for_mpcc_disconnect(
struct core_dc *dc,
struct dc *dc,
struct resource_pool *res_pool,
struct pipe_ctx *pipe_ctx)
{
@@ -2724,7 +2724,7 @@ static const struct hw_sequencer_funcs dce110_funcs = {
.wait_for_mpcc_disconnect = dce110_wait_for_mpcc_disconnect
};
bool dce110_hw_sequencer_construct(struct core_dc *dc)
bool dce110_hw_sequencer_construct(struct dc *dc)
{
dc->hwss = dce110_funcs;

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