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Merge tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Browse Source 
Pull pin control updates from Linus Walleij:
 "Core changes:

   - Perform basic checks on pin config properties so as not to allow
     directly contradictory settings such as setting a pin to more than
     one bias or drive mode

   - Handle input-threshold-voltage-microvolt property

   - Introduce pinctrl_gpio_get_config() handling in the core for SCMI
     GPIO using pin control

  New drivers:

   - GPIO-by-pin control driver (also appearing in the GPIO pull
     request) fulfilling a promise on a comment from Grant Likely many
     years ago: "can't GPIO just be a front-end for pin control?" it
     turns out it can, if and only if you design something new from
     scratch, such as SCMI

   - Broadcom BCM7038 as a pinctrl-single delegate

   - Mobileye EyeQ6Lplus OLB pin controller

   - Qualcomm Eliza and Hawi families TLMM pin controllers

   - Qualcomm SDM670 and Milos family LPASS LPI pin controllers

   - Qualcomm IPQ5210 pin controller

   - Realtek RTD1625 pin controller support

   - Rockchip RV1103B pin controller support

   - Texas Instruments AM62L as a pinctrl-single delegate

  Improvements:

   - Set config implementation for the Spacemit K1 pin controller"

* tag 'pinctrl-v7.1-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (84 commits)
  pinctrl: qcom: Add Hawi pinctrl driver
  dt-bindings: pinctrl: qcom: Describe Hawi TLMM block
  dt-bindings: pinctrl: pinctrl-max77620: convert to DT schema
  pinctrl: single: Add bcm7038-padconf compatible matching
  dt-bindings: pinctrl: pinctrl-single: Add brcm,bcm7038-padconf
  dt-bindings: pinctrl: apple,pinctrl: Add t8122 compatible
  pinctrl: qcom: sdm670-lpass-lpi: label variables as static
  pinctrl: sophgo: pinctrl-sg2044: Fix wrong module description
  pinctrl: sophgo: pinctrl-sg2042: Fix wrong module description
  pinctrl: qcom: add sdm670 lpi tlmm
  dt-bindings: pinctrl: qcom: Add SDM670 LPASS LPI pinctrl
  dt-bindings: qcom: lpass-lpi-common: add reserved GPIOs property
  pinctrl: qcom: Introduce IPQ5210 TLMM driver
  dt-bindings: pinctrl: qcom: add IPQ5210 pinctrl
  pinctrl: qcom: Drop redundant intr_target_reg on modern SoCs
  pinctrl: qcom: eliza: Fix interrupt target bit
  pinctrl: core: Don't use "proxy" headers
  pinctrl: amd: Support new ACPI ID AMDI0033
  pinctrl: renesas: rzg2l: Drop superfluous blank line
  pinctrl: renesas: rzg2l: Fix save/restore of {IOLH,IEN,PUPD,SMT} registers
  ...
This commit is contained in:
Linus Torvalds
2026-04-18 16:59:09 -07:00
parent 401b0e0bc9 90700e10d2
commit faeab16616
120 changed files with 9879 additions and 606 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/pinctrl/apple,pinctrl.yaml
+3 -1
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@@ -18,7 +18,9 @@ properties:
compatible:
oneOf:
- items:
- const: apple,t6020-pinctrl
- enum:
- apple,t6020-pinctrl
- apple,t8122-pinctrl
- const: apple,t8103-pinctrl
- items:
# Do not add additional SoC to this list.
Documentation/devicetree/bindings/pinctrl/fsl,imx27-iomuxc.yaml
+126
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@@ -0,0 +1,126 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx27-iomuxc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX1/i.MX25/i.MX27 IOMUX Controller
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
properties:
compatible:
enum:
- fsl,imx1-iomuxc
- fsl,imx27-iomuxc
reg:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 1
ranges: true
patternProperties:
'^gpio@[0-9a-f]+$':
type: object
$ref: /schemas/gpio/fsl-imx-gpio.yaml
unevaluatedProperties: false
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
three integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description:
PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32
configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN
is the pin number on the specific port (between 0 and 31)
- description: |
MUX_ID is function + (direction << 2) + (gpio_oconf << 4)
+ (gpio_iconfa << 8) + (gpio_iconfb << 10)
function value is used to select the pin function.
Possible values:
0 - Primary function
1 - Alternate function
2 - GPIO
Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
direction defines the data direction of the pin.
Possible values:
0 - Input
1 - Output
Register: DDIR
gpio_oconf configures the gpio submodule output signal.
This does not have any effect unless GPIO function is
selected. A/B/C_IN are output signals of function blocks
A,B and C. Specific function blocks are described in the
reference manual.
Possible values:
0 - A_IN
1 - B_IN
2 - C_IN
3 - Data Register
Registers: OCR1, OCR2
gpio_iconfa/b configures the gpio submodule input to
functionblocks A and B. GPIO function should be selected if
this is configured.
Possible values:
0 - GPIO_IN
1 - Interrupt Status Register
2 - Pulldown
3 - Pullup
Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
- description:
CONFIG can be 0 or 1, meaning Pullup disable/enable.
required:
- fsl,pins
additionalProperties: false
required:
- compatible
- reg
allOf:
- $ref: pinctrl.yaml#
unevaluatedProperties: false
examples:
- |
pinmux@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
uartgrp {
fsl,pins = <
0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
>;
};
};
Documentation/devicetree/bindings/pinctrl/fsl,imx27-pinctrl.txt
-121
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@@ -1,121 +0,0 @@
* Freescale IMX27 IOMUX Controller
Required properties:
- compatible: "fsl,imx27-iomuxc"
The iomuxc driver node should define subnodes containing of pinctrl configuration subnodes.
Required properties for pin configuration node:
- fsl,pins: three integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN MUX_ID CONFIG>.
PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
configurable pins each. PIN is PORT * 32 + PORT_PIN, PORT_PIN is the pin
number on the specific port (between 0 and 31).
MUX_ID is
function + (direction << 2) + (gpio_oconf << 4) + (gpio_iconfa << 8) + (gpio_iconfb << 10)
function value is used to select the pin function.
Possible values:
0 - Primary function
1 - Alternate function
2 - GPIO
Registers: GIUS (GPIO In Use), GPR (General Purpose Register)
direction defines the data direction of the pin.
Possible values:
0 - Input
1 - Output
Register: DDIR
gpio_oconf configures the gpio submodule output signal. This does not
have any effect unless GPIO function is selected. A/B/C_IN are output
signals of function blocks A,B and C. Specific function blocks are
described in the reference manual.
Possible values:
0 - A_IN
1 - B_IN
2 - C_IN
3 - Data Register
Registers: OCR1, OCR2
gpio_iconfa/b configures the gpio submodule input to functionblocks A and
B. GPIO function should be selected if this is configured.
Possible values:
0 - GPIO_IN
1 - Interrupt Status Register
2 - Pulldown
3 - Pullup
Registers ICONFA1, ICONFA2, ICONFB1 and ICONFB2
CONFIG can be 0 or 1, meaning Pullup disable/enable.
The iomux controller has gpio child nodes which are embedded in the iomux
control registers. They have to be defined as child nodes of the iomux device
node. If gpio subnodes are defined "#address-cells", "#size-cells" and "ranges"
properties for the iomux device node are required.
Example:
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@10015000 {
...
};
...
uart {
pinctrl_uart1: uart-1 {
fsl,pins = <
0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
0x8e 0x004 0x0 /* UART1_CTS__UART1_CTS */
0x8f 0x000 0x0 /* UART1_RTS__UART1_RTS */
>;
};
...
};
};
For convenience there are macros defined in imx27-pinfunc.h which provide PIN
and MUX_ID. They are structured as MX27_PAD_<Pad name>__<Signal name>. The names
are defined in the i.MX27 reference manual.
The above example using macros:
iomuxc: iomuxc@10015000 {
compatible = "fsl,imx27-iomuxc";
reg = <0x10015000 0x600>;
#address-cells = <1>;
#size-cells = <1>;
ranges;
gpio1: gpio@10015000 {
...
};
...
uart {
pinctrl_uart1: uart-1 {
fsl,pins = <
MX27_PAD_UART1_TXD__UART1_TXD 0x0
MX27_PAD_UART1_RXD__UART1_RXD 0x0
MX27_PAD_UART1_CTS__UART1_CTS 0x0
MX27_PAD_UART1_RTS__UART1_RTS 0x0
>;
};
...
};
};
Documentation/devicetree/bindings/pinctrl/fsl,imx35-pinctrl.yaml
+1
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@@ -20,6 +20,7 @@ properties:
compatible:
oneOf:
- enum:
- fsl,imx25-iomuxc
- fsl,imx35-iomuxc
- fsl,imx51-iomuxc
- fsl,imx53-iomuxc
Documentation/devicetree/bindings/pinctrl/marvell,armada3710-xb-pinctrl.yaml
+6 -5
View File
@@ -84,11 +84,12 @@ patternProperties:
properties:
groups:
enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,
pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb, smi,
spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
usb2_drvvbus1, usb32_drvvbus0 ]
items:
enum: [ emmc_nb, i2c1, i2c2, jtag, mii_col, onewire, pcie1,
pcie1_clkreq, pcie1_wakeup, pmic0, pmic1, ptp, ptp_clk,
ptp_trig, pwm0, pwm1, pwm2, pwm3, rgmii, sdio0, sdio_sb,
smi, spi_cs1, spi_cs2, spi_cs3, spi_quad, uart1, uart2,
usb2_drvvbus1, usb32_drvvbus0 ]
function:
enum: [ drvbus, emmc, gpio, i2c, jtag, led, mii, mii_err, onewire,
Documentation/devicetree/bindings/pinctrl/maxim,max77620-pinctrl.yaml
+98
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@@ -0,0 +1,98 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/maxim,max77620-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Pinmux controller function for Maxim MAX77620 Power management IC
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
description:
Device has 8 GPIO pins which can be configured as GPIO as well as the
special IO functions.
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
patternProperties:
"^(pin|gpio).":
type: object
additionalProperties: false
properties:
pins:
items:
enum: [ gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7 ]
function:
items:
enum: [ gpio, lpm-control-in, fps-out, 32k-out1, sd0-dvs-in, sd1-dvs-in,
reference-out ]
drive-push-pull: true
drive-open-drain: true
bias-pull-up: true
bias-pull-down: true
maxim,active-fps-source:
$ref: /schemas/types.yaml#/definitions/uint32
description: |
FPS source for the GPIOs to get enabled/disabled when system is in
active state. Valid values are:
- MAX77620_FPS_SRC_0: FPS source is FPS0.
- MAX77620_FPS_SRC_1: FPS source is FPS1
- MAX77620_FPS_SRC_2: FPS source is FPS2
- MAX77620_FPS_SRC_NONE: GPIO is not controlled by FPS events and
it gets enabled/disabled by register access.
Absence of this property will leave the FPS configuration register
for that GPIO to default configuration.
maxim,active-fps-power-up-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Sequencing event slot number on which the GPIO get enabled when
master FPS input event set to HIGH. This is applicable if FPS source
is selected as FPS0, FPS1 or FPS2.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
maxim,active-fps-power-down-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Sequencing event slot number on which the GPIO get disabled when
master FPS input event set to LOW. This is applicable if FPS source
is selected as FPS0, FPS1 or FPS2.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
maxim,suspend-fps-source:
$ref: /schemas/types.yaml#/definitions/uint32
description:
This is same as property "maxim,active-fps-source" but value get
configured when system enters in to suspend state.
maxim,suspend-fps-power-up-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
This is same as property "maxim,active-fps-power-up-slot" but this
value get configured into FPS configuration register when system
enters into suspend. This is applicable if suspend state FPS source
is selected as FPS0, FPS1 or FPS2.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
maxim,suspend-fps-power-down-slot:
$ref: /schemas/types.yaml#/definitions/uint32
description:
This is same as property "maxim,active-fps-power-down-slot" but this
value get configured into FPS configuration register when system
enters into suspend. This is applicable if suspend state FPS source
is selected as FPS0, FPS1 or FPS2.
enum: [0, 1, 2, 3, 4, 5, 6, 7]
required:
- pins
additionalProperties: false
# see maxim,max77620.yaml for an example
Documentation/devicetree/bindings/pinctrl/pincfg-node.yaml
+100 -7
View File
@@ -162,12 +162,105 @@ properties:
this affects the expected delay in ps before latching a value to
an output pin.
if:
required:
- skew-delay
then:
properties:
skew-delay-input-ps: false
skew-delay-output-ps: false
input-threshold-voltage-microvolt:
description: Specifies the input voltage level of the pin in microvolts.
This defines the reference for VIH (Input High Voltage) and VIL
(Input Low Voltage) thresholds for proper signal detection.
allOf:
- if:
required:
- skew-delay
then:
properties:
skew-delay-input-ps: false
skew-delay-output-ps: false
- if:
required:
- input-disable
then:
properties:
input-enable: false
input-threshold-voltage-microvolt: false
- if:
required:
- output-disable
then:
properties:
output-enable: false
output-impedance-ohms: false
- if:
required:
- output-low
then:
properties:
output-high: false
- if:
required:
- low-power-enable
then:
properties:
low-power-disable: false
- if:
required:
- input-schmitt-disable
then:
properties:
input-schmitt-enable: false
input-schmitt-microvolt: false
- if:
required:
- drive-strength
then:
properties:
drive-strength-microamp: false
- if:
anyOf:
- required:
- drive-open-source
- required:
- drive-open-drain
- required:
- drive-push-pull
then:
oneOf:
- required:
- drive-open-source
- required:
- drive-open-drain
- required:
- drive-push-pull
- if:
anyOf:
- required:
- bias-disable
- required:
- bias-bus-hold
- required:
- bias-pull-up
- required:
- bias-pull-down
- required:
- bias-pull-pin-default
then:
oneOf:
- required:
- bias-disable
- required:
- bias-bus-hold
- required:
- bias-pull-up
- required:
- bias-pull-down
- required:
- bias-pull-pin-default
additionalProperties: true
Documentation/devicetree/bindings/pinctrl/pinctrl-max77620.txt
-127
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@@ -1,127 +0,0 @@
Pincontrol driver for MAX77620 Power management IC from Maxim Semiconductor.
Device has 8 GPIO pins which can be configured as GPIO as well as the
special IO functions.
Please refer file <devicetree/bindings/pinctrl/pinctrl-bindings.txt>
for details of the common pinctrl bindings used by client devices,
including the meaning of the phrase "pin configuration node".
Optional Pinmux properties:
--------------------------
Following properties are required if default setting of pins are required
at boot.
- pinctrl-names: A pinctrl state named per <pinctrl-bindings.txt>.
- pinctrl[0...n]: Properties to contain the phandle for pinctrl states per
<pinctrl-bindings.txt>.
The pin configurations are defined as child of the pinctrl states node. Each
sub-node have following properties:
Required properties:
------------------
- pins: List of pins. Valid values of pins properties are:
gpio0, gpio1, gpio2, gpio3, gpio4, gpio5, gpio6, gpio7.
Optional properties:
-------------------
Following are optional properties defined as pinmux DT binding document
<pinctrl-bindings.txt>. Absence of properties will leave the configuration
on default.
function,
drive-push-pull,
drive-open-drain,
bias-pull-up,
bias-pull-down.
Valid values for function properties are:
gpio, lpm-control-in, fps-out, 32k-out, sd0-dvs-in, sd1-dvs-in,
reference-out
There are also customised properties for the GPIO1, GPIO2 and GPIO3. These
customised properties are required to configure FPS configuration parameters
of these GPIOs. Please refer <devicetree/bindings/mfd/max77620.txt> for more
detail of Flexible Power Sequence (FPS).
- maxim,active-fps-source: FPS source for the GPIOs to get
enabled/disabled when system is in
active state. Valid values are:
- MAX77620_FPS_SRC_0,
FPS source is FPS0.
- MAX77620_FPS_SRC_1,
FPS source is FPS1
- MAX77620_FPS_SRC_2 and
FPS source is FPS2
- MAX77620_FPS_SRC_NONE.
GPIO is not controlled
by FPS events and it gets
enabled/disabled by register
access.
Absence of this property will leave
the FPS configuration register for that
GPIO to default configuration.
- maxim,active-fps-power-up-slot: Sequencing event slot number on which
the GPIO get enabled when
master FPS input event set to HIGH.
Valid values are 0 to 7.
This is applicable if FPS source is
selected as FPS0, FPS1 or FPS2.
- maxim,active-fps-power-down-slot: Sequencing event slot number on which
the GPIO get disabled when master
FPS input event set to LOW.
Valid values are 0 to 7.
This is applicable if FPS source is
selected as FPS0, FPS1 or FPS2.
- maxim,suspend-fps-source: This is same as property
"maxim,active-fps-source" but value
get configured when system enters in
to suspend state.
- maxim,suspend-fps-power-up-slot: This is same as property
"maxim,active-fps-power-up-slot" but
this value get configured into FPS
configuration register when system
enters into suspend.
This is applicable if suspend state
FPS source is selected as FPS0, FPS1 or
- maxim,suspend-fps-power-down-slot: This is same as property
"maxim,active-fps-power-down-slot" but
this value get configured into FPS
configuration register when system
enters into suspend.
This is applicable if suspend state
FPS source is selected as FPS0, FPS1 or
FPS2.
Example:
--------
#include <dt-bindings/mfd/max77620.h>
...
max77620@3c {
pinctrl-names = "default";
pinctrl-0 = <&spmic_default>;
spmic_default: pinmux@0 {
pin_gpio0 {
pins = "gpio0";
function = "gpio";
};
pin_gpio1 {
pins = "gpio1";
function = "fps-out";
maxim,active-fps-source = <MAX77620_FPS_SRC_0>;
};
pin_gpio2 {
pins = "gpio2";
function = "fps-out";
maxim,active-fps-source = <MAX77620_FPS_SRC_1>;
};
};
};
Documentation/devicetree/bindings/pinctrl/pinctrl-single.yaml
+4
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@@ -38,6 +38,10 @@ properties:
- enum:
- marvell,pxa1908-padconf
- const: pinconf-single
- items:
- enum:
- brcm,bcm7038-padconf
- const: pinctrl-single
reg:
maxItems: 1
Documentation/devicetree/bindings/pinctrl/qcom,eliza-tlmm.yaml
+138
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@@ -0,0 +1,138 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,eliza-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Eliza TLMM block
maintainers:
- Abel Vesa <abel.vesa@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Eliza SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,eliza-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 93
gpio-line-names:
maxItems: 185
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-eliza-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-eliza-tlmm-state"
additionalProperties: false
$defs:
qcom-eliza-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9]|18[0-4])$"
- enum: [ ufs_reset ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk0,
audio_ref_clk, cam_mclk, cci_async_in, cci_i2c_scl,
cci_i2c_sda, cci_timer, coex_uart1_rx, coex_uart1_tx,
coex_uart2_rx, coex_uart2_tx, dbg_out_clk,
ddr_bist_complete, ddr_bist_fail, ddr_bist_start,
ddr_bist_stop, ddr_pxi0, ddr_pxi1, dp0_hot, egpio,
gcc_gp1, gcc_gp2, gcc_gp3, gnss_adc0, gnss_adc1,
hdmi_ddc_scl, hdmi_ddc_sda, hdmi_dtest0, hdmi_dtest1,
hdmi_hot_plug, hdmi_pixel_clk, hdmi_rcv_det, hdmi_tx_cec,
host2wlan_sol, i2s0_data0, i2s0_data1, i2s0_sck, i2s0_ws,
ibi_i3c, jitter_bist, mdp_esync0_out, mdp_esync1_out,
mdp_vsync, mdp_vsync0_out, mdp_vsync11_out,
mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out,
mdp_vsync_e, nav_gpio0, nav_gpio1, nav_gpio2, nav_gpio3,
pcie0_clk_req_n, pcie1_clk_req_n, phase_flag,
pll_bist_sync, pll_clk_aux, prng_rosc0, prng_rosc1,
prng_rosc2, prng_rosc3, qdss_cti, qdss_gpio_traceclk,
qdss_gpio_tracectl, qdss_gpio_tracedata, qlink_big_enable,
qlink_big_request, qlink_little_enable,
qlink_little_request, qlink_wmss, qspi0, qspi_clk,
qspi_cs, qup1_se0, qup1_se1, qup1_se2, qup1_se3, qup1_se4,
qup1_se5, qup1_se6, qup1_se7, qup2_se0, qup2_se1,
qup2_se2, qup2_se3, qup2_se4, qup2_se5, qup2_se6,
qup2_se7, resout_gpio, sd_write_protect, sdc1, sdc2,
sdc2_fb_clk, tb_trig_sdc1, tb_trig_sdc2, tmess_prng0,
tmess_prng1, tmess_prng2, tmess_prng3, tsense_pwm1,
tsense_pwm2, tsense_pwm3, tsense_pwm4, uim0_clk,
uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
uim1_present, uim1_reset, usb0_hs, usb_phy, vfr_0, vfr_1,
vsense_trigger_mirnat, wcn_sw_ctrl ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f100000 {
compatible = "qcom,eliza-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
gpio-ranges = <&tlmm 0 0 186>;
gpio-wo-state {
pins = "gpio1";
function = "gpio";
};
qup-uart14-default-state {
pins = "gpio18", "gpio19";
function = "qup2_se5";
drive-strength = <2>;
bias-disable;
};
};
...
Documentation/devicetree/bindings/pinctrl/qcom,hawi-tlmm.yaml
+120
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@@ -0,0 +1,120 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,hawi-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Technologies, Inc. Hawi TLMM block
maintainers:
- Mukesh Ojha <mukesh.ojha@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm Hawi SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,hawi-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 113
gpio-line-names:
maxItems: 226
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-hawi-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-hawi-tlmm-state"
additionalProperties: false
$defs:
qcom-hawi-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-9][0-9]|20[0-9]|21[0-9]|22[0-5])$"
- enum: [ ufs_reset, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ gpio, aoss_cti, atest_char, atest_usb, audio_ext_mclk,
audio_ref_clk, cam_mclk, cci_async_in, cci_i2c0, cci_i2c1,
cci_i2c2, cci_i2c3, cci_i2c4, cci_i2c5, cci_timer, coex_espmi,
coex_uart1_rx, coex_uart1_tx, dbg_out_clk, ddr_bist, ddr_pxi,
dp_hot, egpio, gcc_gp, gnss_adc, host_rst, i2chub0_se0,
i2chub0_se1, i2chub0_se2, i2chub0_se3, i2chub0_se4, i2s0, i2s1,
ibi_i3c, jitter_bist, mdp_esync0, mdp_esync1, mdp_esync2,
mdp_vsync, mdp_vsync_e, mdp_vsync_p, mdp_vsync0_out,
mdp_vsync1_out, mdp_vsync2_out, mdp_vsync3_out, mdp_vsync5_out,
modem_pps_in, modem_pps_out, nav_gpio, nav_gpio0, nav_gpio3,
nav_rffe, pcie0_clk_req_n, pcie0_rst_n, pcie1_clk_req_n,
phase_flag, pll_bist_sync, pll_clk_aux, qdss_cti, qlink,
qspi, qspi_clk, qspi_cs, qup1_se0, qup1_se1, qup1_se2,
qup1_se3, qup1_se4, qup1_se5, qup1_se6, qup1_se7, qup2_se0,
qup2_se1, qup2_se2, qup2_se3, qup2_se4_01, qup2_se4_23,
qup3_se0_01, qup3_se0_23, qup3_se1, qup3_se2, qup3_se3,
qup3_se4, qup3_se5, qup4_se0, qup4_se1, qup4_se2, qup4_se3_01,
qup4_se3_23, qup4_se3_l3, qup4_se4_01, qup4_se4_23, qup4_se4_l3,
rng_rosc, sd_write_protect, sdc4_clk, sdc4_cmd, sdc4_data,
sys_throttle, tb_trig_sdc, tmess_rng, tsense_clm, tsense_pwm,
uim0, uim1, usb0_hs, usb_phy, vfr, vsense_trigger_mirnat,
wcn_sw_ctrl ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@f100000 {
compatible = "qcom,hawi-tlmm";
reg = <0x0f100000 0x300000>;
interrupts = <GIC_ESPI 272 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 227>;
interrupt-controller;
#interrupt-cells = <2>;
qup-uart7-state {
pins = "gpio62", "gpio63";
function = "qup1_se7";
};
};
...
Documentation/devicetree/bindings/pinctrl/qcom,ipq5210-tlmm.yaml
+123
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@@ -0,0 +1,123 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5210-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm IPQ5210 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
description:
Top Level Mode Multiplexer pin controller in Qualcomm IPQ5210 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,ipq5210-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 27
gpio-line-names:
maxItems: 54
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-ipq5210-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-ipq5210-tlmm-state"
additionalProperties: false
$defs:
qcom-ipq5210-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-4][0-9]|5[0-3])$"
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ atest_char_start, atest_char_status0, atest_char_status1,
atest_char_status2, atest_char_status3, atest_tic_en, audio_pri,
audio_pri_mclk_out0, audio_pri_mclk_in0, audio_pri_mclk_out1,
audio_pri_mclk_in1, audio_pri_mclk_out2, audio_pri_mclk_in2,
audio_pri_mclk_out3, audio_pri_mclk_in3, audio_sec,
audio_sec_mclk_out0, audio_sec_mclk_in0, audio_sec_mclk_out1,
audio_sec_mclk_in1, audio_sec_mclk_out2, audio_sec_mclk_in2,
audio_sec_mclk_out3, audio_sec_mclk_in3, core_voltage_0,
cri_trng0, cri_trng1, cri_trng2, cri_trng3, dbg_out_clk, dg_out,
gcc_plltest_bypassnl, gcc_plltest_resetn, gcc_tlmm, gpio, led0,
led1, led2, mdc_mst, mdc_slv0, mdc_slv1, mdc_slv2, mdio_mst,
mdio_slv0, mdio_slv1, mdio_slv2, mux_tod_out, pcie0_clk_req_n,
pcie0_wake, pcie1_clk_req_n, pcie1_wake, pll_test,
pon_active_led, pon_mux_sel, pon_rx, pon_rx_los, pon_tx,
pon_tx_burst, pon_tx_dis, pon_tx_fault, pon_tx_sd, gpn_rx_los,
gpn_tx_burst, gpn_tx_dis, gpn_tx_fault, gpn_tx_sd, pps, pwm0,
pwm1, pwm2, pwm3, qdss_cti_trig_in_a0, qdss_cti_trig_in_a1,
qdss_cti_trig_in_b0, qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_tracectl_a,
qdss_tracedata_a, qrng_rosc0, qrng_rosc1, qrng_rosc2,
qspi_data, qspi_clk, qspi_cs_n, qup_se0, qup_se1, qup_se2,
qup_se3, qup_se4, qup_se5, qup_se5_l1, resout, rx_los0, rx_los1,
rx_los2, sdc_clk, sdc_cmd, sdc_data, tsens_max ]
required:
- pins
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5210-tlmm";
reg = <0x01000000 0x300000>;
gpio-controller;
#gpio-cells = <0x2>;
gpio-ranges = <&tlmm 0 0 54>;
interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <0x2>;
qup-uart1-default-state {
pins = "gpio38", "gpio39";
function = "qup_se1";
drive-strength = <6>;
bias-pull-down;
};
};
Documentation/devicetree/bindings/pinctrl/qcom,lpass-lpi-common.yaml
+8
View File
@@ -27,6 +27,14 @@ properties:
gpio-ranges:
maxItems: 1
gpio-reserved-ranges:
minItems: 1
maxItems: 30
description:
Pins can be reserved for trusted applications or for LPASS, thereby
inaccessible from the OS. This property can be used to mark the pins
which resources should not be accessed by the OS.
required:
- gpio-controller
- "#gpio-cells"
Documentation/devicetree/bindings/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml
+109
View File
@@ -0,0 +1,109 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,milos-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm Milos SoC LPASS LPI TLMM
maintainers:
- Luca Weiss <luca.weiss@fairphone.com>
description:
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
(LPASS) Low Power Island (LPI) of Qualcomm Milos SoC.
properties:
compatible:
const: qcom,milos-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
- description: LPASS LPI MCC registers
clocks:
items:
- description: LPASS Core voting clock
- description: LPASS Audio voting clock
clock-names:
items:
- const: core
- const: audio
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-milos-lpass-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-milos-lpass-state"
additionalProperties: false
$defs:
qcom-milos-lpass-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|1[0-9]|2[0-2])$"
function:
enum: [ dmic1_clk, dmic1_data, dmic2_clk, dmic2_data, dmic3_clk,
dmic3_data, dmic4_clk, dmic4_data, ext_mclk1_a, ext_mclk1_b,
ext_mclk1_c, ext_mclk1_d, ext_mclk1_e, gpio, i2s0_clk,
i2s0_data, i2s0_ws, i2s1_clk, i2s1_data, i2s1_ws, i2s2_clk,
i2s2_data, i2s2_ws, i2s3_clk, i2s3_data, i2s3_ws, qca_swr_clk,
qca_swr_data, slimbus_clk, slimbus_data, swr_rx_clk,
swr_rx_data, swr_tx_clk, swr_tx_data, wsa_swr_clk,
wsa_swr_data ]
description:
Specify the alternative function to be configured for the specified
pins.
allOf:
- $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
- clocks
- clock-names
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h>
pinctrl@3440000 {
compatible = "qcom,milos-lpass-lpi-pinctrl";
reg = <0x03440000 0x20000>,
<0x034d0000 0x10000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpass_tlmm 0 0 23>;
clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>,
<&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>;
clock-names = "core",
"audio";
tx-swr-active-clk-state {
pins = "gpio0";
function = "swr_tx_clk";
drive-strength = <4>;
slew-rate = <1>;
bias-disable;
};
};
Documentation/devicetree/bindings/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml
+81
View File
@@ -0,0 +1,81 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,sdm670-lpass-lpi-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SDM670 SoC LPASS LPI TLMM
maintainers:
- Richard Acayan <mailingradian@gmail.com>
description:
Top Level Mode Multiplexer pin controller in the Low Power Audio SubSystem
(LPASS) Low Power Island (LPI) of Qualcomm SDM670 SoC.
properties:
compatible:
const: qcom,sdm670-lpass-lpi-pinctrl
reg:
items:
- description: LPASS LPI TLMM Control and Status registers
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-sdm670-lpass-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-sdm670-lpass-state"
additionalProperties: false
$defs:
qcom-sdm670-lpass-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,lpass-lpi-common.yaml#/$defs/qcom-tlmm-state
unevaluatedProperties: false
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|1[0-9]|2[0-9]|3[0-1])$"
function:
enum: [ gpio, comp_rx, dmic1_clk, dmic1_data, dmic2_clk, dmic2_data,
i2s1_clk, i2s_data, i2s_ws, lpi_cdc_rst, mclk0, pdm_rx,
pdm_sync, pdm_tx, slimbus_clk ]
description:
Specify the alternative function to be configured for the specified
pins.
allOf:
- $ref: qcom,lpass-lpi-common.yaml#
required:
- compatible
- reg
unevaluatedProperties: false
examples:
- |
lpi_tlmm: pinctrl@62b40000 {
compatible = "qcom,sdm670-lpass-lpi-pinctrl";
reg = <0x62b40000 0x20000>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&lpi_tlmm 0 0 32>;
cdc_comp_default: cdc-comp-default-state {
pins = "gpio22", "gpio24";
function = "comp_rx";
drive-strength = <4>;
};
};
Documentation/devicetree/bindings/pinctrl/qcom,sm8450-lpass-lpi-pinctrl.yaml
+7 -1
View File
@@ -15,7 +15,13 @@ description:
properties:
compatible:
const: qcom,sm8450-lpass-lpi-pinctrl
oneOf:
- const: qcom,sm8450-lpass-lpi-pinctrl
- items:
- enum:
- qcom,qcs8300-lpass-lpi-pinctrl
- qcom,sa8775p-lpass-lpi-pinctrl
- const: qcom,sm8450-lpass-lpi-pinctrl
reg:
items:
Documentation/devicetree/bindings/pinctrl/qcom,sm8650-lpass-lpi-pinctrl.yaml
+3 -1
View File
@@ -19,7 +19,9 @@ properties:
oneOf:
- const: qcom,sm8650-lpass-lpi-pinctrl
- items:
- const: qcom,sm8750-lpass-lpi-pinctrl
- enum:
- qcom,glymur-lpass-lpi-pinctrl
- qcom,sm8750-lpass-lpi-pinctrl
- const: qcom,sm8650-lpass-lpi-pinctrl
reg:
Documentation/devicetree/bindings/pinctrl/realtek,rtd1315e-pinctrl.yaml
+5 -2
View File
@@ -135,8 +135,11 @@ patternProperties:
realtek,duty-cycle:
description: |
An integer describing the level to adjust output duty cycle, controlling
the proportion of positive and negative waveforms in nanoseconds.
An integer describing the level to adjust the output pulse width, it
provides a fixed nanosecond-level adjustment to the rising/falling
edges of an existing signal. It is used for Signal Integrity tuning
(adding/subtracting delay to fine-tune the high/low duration), rather
than generating a specific PWM frequency.
Valid arguments are described as below:
0: 0ns
2: + 0.25ns
Documentation/devicetree/bindings/pinctrl/realtek,rtd1319d-pinctrl.yaml
+5 -2
View File
@@ -134,8 +134,11 @@ patternProperties:
realtek,duty-cycle:
description: |
An integer describing the level to adjust output duty cycle, controlling
the proportion of positive and negative waveforms in nanoseconds.
An integer describing the level to adjust the output pulse width, it
provides a fixed nanosecond-level adjustment to the rising/falling
edges of an existing signal. It is used for Signal Integrity tuning
(adding/subtracting delay to fine-tune the high/low duration), rather
than generating a specific PWM frequency.
Valid arguments are described as below:
0: 0ns
2: + 0.25ns
Documentation/devicetree/bindings/pinctrl/realtek,rtd1619b-pinctrl.yaml
+5 -2
View File
@@ -133,8 +133,11 @@ patternProperties:
realtek,duty-cycle:
description: |
An integer describing the level to adjust output duty cycle, controlling
the proportion of positive and negative waveforms in nanoseconds.
An integer describing the level to adjust the output pulse width, it
provides a fixed nanosecond-level adjustment to the rising/falling
edges of an existing signal. It is used for Signal Integrity tuning
(adding/subtracting delay to fine-tune the high/low duration), rather
than generating a specific PWM frequency.
Valid arguments are described as below:
0: 0ns
2: + 0.25ns

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