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Merge trace/for-next
This commit is contained in:
Steven Rostedt
@@ -66,6 +66,11 @@ Alex Hung <alexhung@gmail.com> <alex.hung@canonical.com>
|
||||
Alex Shi <alexs@kernel.org> <alex.shi@intel.com>
|
||||
Alex Shi <alexs@kernel.org> <alex.shi@linaro.org>
|
||||
Alex Shi <alexs@kernel.org> <alex.shi@linux.alibaba.com>
|
||||
Alice Mikityanska <alice.kernel@fastmail.im> <maxtram95@gmail.com>
|
||||
Alice Mikityanska <alice.kernel@fastmail.im> <maximmi@mellanox.com>
|
||||
Alice Mikityanska <alice.kernel@fastmail.im> <maximmi@nvidia.com>
|
||||
Alice Mikityanska <alice.kernel@fastmail.im> <maxim@isovalent.com>
|
||||
Alice Mikityanska <alice.kernel@fastmail.im> <alice@isovalent.com>
|
||||
Aloka Dixit <quic_alokad@quicinc.com> <alokad@codeaurora.org>
|
||||
Al Viro <viro@ftp.linux.org.uk>
|
||||
Al Viro <viro@zenIV.linux.org.uk>
|
||||
@@ -373,6 +378,7 @@ Jarkko Sakkinen <jarkko@kernel.org> <jarkko.sakkinen@opinsys.com>
|
||||
Jason Gunthorpe <jgg@ziepe.ca> <jgg@mellanox.com>
|
||||
Jason Gunthorpe <jgg@ziepe.ca> <jgg@nvidia.com>
|
||||
Jason Gunthorpe <jgg@ziepe.ca> <jgunthorpe@obsidianresearch.com>
|
||||
Jason Wang <jasowangio@gmail.com> <jasowang@redhat.com>
|
||||
Jason Xing <kerneljasonxing@gmail.com> <kernelxing@tencent.com>
|
||||
<javier@osg.samsung.com> <javier.martinez@collabora.co.uk>
|
||||
Javi Merino <javi.merino@kernel.org> <javi.merino@arm.com>
|
||||
@@ -398,6 +404,7 @@ Jens Axboe <axboe@kernel.dk> <jens.axboe@oracle.com>
|
||||
Jens Axboe <axboe@kernel.dk> <axboe@fb.com>
|
||||
Jens Axboe <axboe@kernel.dk> <axboe@meta.com>
|
||||
Jens Osterkamp <Jens.Osterkamp@de.ibm.com>
|
||||
Jens Wiklander <jenswi@kernel.org> <jens.wiklander@linaro.org>
|
||||
Jernej Skrabec <jernej.skrabec@gmail.com> <jernej.skrabec@siol.net>
|
||||
Jesper Dangaard Brouer <hawk@kernel.org> <brouer@redhat.com>
|
||||
Jesper Dangaard Brouer <hawk@kernel.org> <hawk@comx.dk>
|
||||
@@ -538,6 +545,7 @@ Maciej W. Rozycki <macro@mips.com> <macro@imgtec.com>
|
||||
Maciej W. Rozycki <macro@orcam.me.uk> <macro@linux-mips.org>
|
||||
Maharaja Kennadyrajan <quic_mkenna@quicinc.com> <mkenna@codeaurora.org>
|
||||
Maheshwar Ajja <quic_majja@quicinc.com> <majja@codeaurora.org>
|
||||
Maíra Canal <mairacanal@riseup.net> <maira.canal@usp.br>
|
||||
Malathi Gottam <quic_mgottam@quicinc.com> <mgottam@codeaurora.org>
|
||||
Manikanta Pubbisetty <quic_mpubbise@quicinc.com> <mpubbise@codeaurora.org>
|
||||
Manivannan Sadhasivam <mani@kernel.org> <manivannanece23@gmail.com>
|
||||
@@ -583,8 +591,6 @@ Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@osg.samsung.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@redhat.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <m.chehab@samsung.com>
|
||||
Mauro Carvalho Chehab <mchehab@kernel.org> <mchehab@s-opensource.com>
|
||||
Maxim Mikityanskiy <maxtram95@gmail.com> <maximmi@mellanox.com>
|
||||
Maxim Mikityanskiy <maxtram95@gmail.com> <maximmi@nvidia.com>
|
||||
Maxime Ripard <mripard@kernel.org> <maxime@cerno.tech>
|
||||
Maxime Ripard <mripard@kernel.org> <maxime.ripard@bootlin.com>
|
||||
Maxime Ripard <mripard@kernel.org> <maxime.ripard@free-electrons.com>
|
||||
@@ -593,8 +599,8 @@ Mayuresh Janorkar <mayur@ti.com>
|
||||
Md Sadre Alam <quic_mdalam@quicinc.com> <mdalam@codeaurora.org>
|
||||
Miaoqing Pan <quic_miaoqing@quicinc.com> <miaoqing@codeaurora.org>
|
||||
Michael Buesch <m@bues.ch>
|
||||
Michal Grzeschik <mgr@kernel.org> <m.grzeschik@pengutronix.de>
|
||||
Michal Grzeschik <mgr@kernel.org> <mgr@pengutronix.de>
|
||||
Michael Grzeschik <mgr@kernel.org> <m.grzeschik@pengutronix.de>
|
||||
Michael Grzeschik <mgr@kernel.org> <mgr@pengutronix.de>
|
||||
Michael Riesch <michael.riesch@collabora.com> <michael.riesch@wolfvision.net>
|
||||
Michal Simek <michal.simek@amd.com> <michal.simek@xilinx.com>
|
||||
Michel Dänzer <michel@tungstengraphics.com>
|
||||
@@ -641,7 +647,6 @@ Nicholas Piggin <npiggin@gmail.com> <npiggin@kernel.dk>
|
||||
Nicholas Piggin <npiggin@gmail.com> <npiggin@suse.de>
|
||||
Nicholas Piggin <npiggin@gmail.com> <nickpiggin@yahoo.com.au>
|
||||
Nicholas Piggin <npiggin@gmail.com> <piggin@cyberone.com.au>
|
||||
Nick Desaulniers <nick.desaulniers+lkml@gmail.com> <ndesaulniers@google.com>
|
||||
Nicolas Ferre <nicolas.ferre@microchip.com> <nicolas.ferre@atmel.com>
|
||||
Nicolas Pitre <nico@fluxnic.net> <nicolas.pitre@linaro.org>
|
||||
Nicolas Pitre <nico@fluxnic.net> <nico@linaro.org>
|
||||
@@ -708,6 +713,10 @@ Qi Zheng <qi.zheng@linux.dev> <zhengqi.arch@bytedance.com>
|
||||
Quentin Monnet <qmo@kernel.org> <quentin.monnet@netronome.com>
|
||||
Quentin Monnet <qmo@kernel.org> <quentin@isovalent.com>
|
||||
Quentin Perret <qperret@qperret.net> <quentin.perret@arm.com>
|
||||
Radu Rendec <radu@rendec.net> <radu.rendec@ines.ro>
|
||||
Radu Rendec <radu@rendec.net> <rrendec@arista.com>
|
||||
Radu Rendec <radu@rendec.net> <radu.rendec@gmail.com>
|
||||
Radu Rendec <radu@rendec.net> <rrendec@redhat.com>
|
||||
Rae Moar <raemoar63@gmail.com> <rmoar@google.com>
|
||||
Rafael J. Wysocki <rjw@rjwysocki.net> <rjw@sisk.pl>
|
||||
Rajeev Nandan <quic_rajeevny@quicinc.com> <rajeevny@codeaurora.org>
|
||||
@@ -812,6 +821,7 @@ Simon Wunderlich <sw@simonwunderlich.de> <simon.wunderlich@s2003.tu-chemnitz.de>
|
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Simon Wunderlich <sw@simonwunderlich.de> <simon.wunderlich@saxnet.de>
|
||||
Simon Wunderlich <sw@simonwunderlich.de> <simon@open-mesh.com>
|
||||
Simon Wunderlich <sw@simonwunderlich.de> <siwu@hrz.tu-chemnitz.de>
|
||||
SJ Park <sj@kernel.org>
|
||||
Sricharan Ramabadhran <quic_srichara@quicinc.com> <sricharan@codeaurora.org>
|
||||
Srinivas Kandagatla <srini@kernel.org> <srinivas.kandagatla@st.com>
|
||||
Srinivas Kandagatla <srini@kernel.org> <srinivas.kandagatla@linaro.org>
|
||||
@@ -821,8 +831,8 @@ Sriram Yagnaraman <sriram.yagnaraman@ericsson.com> <sriram.yagnaraman@est.tech>
|
||||
Stanislav Fomichev <sdf@fomichev.me> <sdf@google.com>
|
||||
Stanislav Fomichev <sdf@fomichev.me> <stfomichev@gmail.com>
|
||||
Stefan Wahren <wahrenst@gmx.net> <stefan.wahren@i2se.com>
|
||||
Stéphane Grosjean <stephane.grosjean@hms-networks.com> <s.grosjean@peak-system.com>
|
||||
Stéphane Grosjean <stephane.grosjean@hms-networks.com> <stephane.grosjean@free.fr>
|
||||
Stéphane Grosjean <s.grosjean@peak-system.fr> <s.grosjean@peak-system.com>
|
||||
Stéphane Grosjean <s.grosjean@peak-system.fr> <stephane.grosjean@free.fr>
|
||||
Stéphane Witzmann <stephane.witzmann@ubpmes.univ-bpclermont.fr>
|
||||
Stephen Hemminger <stephen@networkplumber.org> <shemminger@linux-foundation.org>
|
||||
Stephen Hemminger <stephen@networkplumber.org> <shemminger@osdl.org>
|
||||
|
||||
@@ -3626,6 +3626,13 @@ S: 69 rue Dunois
|
||||
S: 75013 Paris
|
||||
S: France
|
||||
|
||||
N: Wolfram Sang
|
||||
E: wsa@kernel.org
|
||||
W: sang-engineering.com
|
||||
P: rsa4096/140DE4CC14A029B6 3991 B1EA B9E2 6751 A4F7 645D 140D E4CC 14A0 29B6
|
||||
D: I2C Maintainer 2012 - 2026
|
||||
S: Berlin, Germany
|
||||
|
||||
N: Aleksa Sarai
|
||||
E: cyphar@cyphar.com
|
||||
W: https://www.cyphar.com/
|
||||
|
||||
@@ -29,3 +29,29 @@ Date: Oct 2025
|
||||
KernelVersion: 6.18
|
||||
Contact: Cédric Le Goater <clg@redhat.com>
|
||||
Description: Read the migration features of the vfio device.
|
||||
|
||||
What: /sys/kernel/debug/vfio/<device>/pci
|
||||
Date: June 2026
|
||||
KernelVersion: 7.2
|
||||
Contact: Alex Williamson <alex.williamson@nvidia.com>
|
||||
Description: This debugfs file directory is used for debugging
|
||||
VFIO PCI devices.
|
||||
|
||||
What: /sys/kernel/debug/vfio/<device>/pci/nointxmask
|
||||
Date: June 2026
|
||||
KernelVersion: 7.2
|
||||
Contact: Alex Williamson <alex.williamson@nvidia.com>
|
||||
Description: Read the nointxmask policy latched for this device. This
|
||||
policy governs whether the device may use PCI 2.3 style
|
||||
INTx masking when supported, reporting a value of "N", or
|
||||
requires APIC level INTx masking, reporting a value of "Y".
|
||||
|
||||
What: /sys/kernel/debug/vfio/<device>/pci/disable_idle_d3
|
||||
Date: June 2026
|
||||
KernelVersion: 7.2
|
||||
Contact: Alex Williamson <alex.williamson@nvidia.com>
|
||||
Description: Read the disable_idle_d3 policy latched for this device. This
|
||||
policy governs whether the device PM runtime usage count is
|
||||
kept elevated while the device is bound to the driver and
|
||||
unused, reporting a value of "Y", or decremented to allow the
|
||||
device to enter a low power state, reporting a value of "N".
|
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|
||||
@@ -22,7 +22,7 @@ Description:
|
||||
|
||||
Reading this attribute gives the state of the DbC. It
|
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can be one of the following states: disabled, enabled,
|
||||
initialized, connected or configured.
|
||||
initialized, connected, configured or suspended.
|
||||
|
||||
What: /sys/bus/pci/drivers/xhci_hcd/.../dbc_idVendor
|
||||
Date: March 2023
|
||||
|
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File diff suppressed because it is too large
Load Diff
@@ -9,6 +9,7 @@ RDMA Controller
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1-2. Why RDMA controller needed?
|
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1-3. How is RDMA controller implemented?
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2. Usage Examples
|
||||
3. RDMA Interface Files
|
||||
|
||||
1. Overview
|
||||
===========
|
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@@ -115,3 +116,68 @@ Following resources can be accounted by rdma controller.
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(d) Delete resource limit::
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||||
|
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echo mlx4_0 hca_handle=max hca_object=max > /sys/fs/cgroup/rdma/1/rdma.max
|
||||
|
||||
3. RDMA Interface Files
|
||||
========================
|
||||
|
||||
The following interface files are available in each non-root RDMA cgroup.
|
||||
|
||||
rdma.max
|
||||
A read-write file which describes the configured resource limit
|
||||
for an RDMA/IB device. See the Usage Examples above.
|
||||
|
||||
rdma.current
|
||||
A read-only file which describes the current resource usage.
|
||||
|
||||
rdma.peak
|
||||
A read-only nested-keyed file which shows the historical high
|
||||
watermark of resource usage per device since the cgroup was created.
|
||||
|
||||
An example for mlx4 and ocrdma device follows::
|
||||
|
||||
mlx4_0 hca_handle=1 hca_object=20
|
||||
ocrdma1 hca_handle=0 hca_object=23
|
||||
|
||||
rdma.events
|
||||
A read-only nested-keyed file which exists on non-root cgroups
|
||||
and contains the following keys:
|
||||
|
||||
max
|
||||
The number of times a process in this cgroup or its
|
||||
descendants attempted an RDMA resource allocation that
|
||||
was rejected because a rdma.max limit in the subtree
|
||||
was reached. This is a hierarchical counter propagated
|
||||
upward to all ancestor cgroups. A value change in this
|
||||
file generates a file modified event.
|
||||
|
||||
alloc_fail
|
||||
The number of RDMA resource allocation attempts that
|
||||
originated in this cgroup or its descendants and failed
|
||||
due to a rdma.max limit being reached. This is a
|
||||
hierarchical counter propagated upward.
|
||||
|
||||
An example for mlx4 device follows::
|
||||
|
||||
mlx4_0 hca_handle.max=5 hca_handle.alloc_fail=3 hca_object.max=0 hca_object.alloc_fail=0
|
||||
|
||||
rdma.events.local
|
||||
Similar to rdma.events but the fields are local to the cgroup,
|
||||
i.e. not hierarchical. The file modified event generated on this
|
||||
file reflects only the local events.
|
||||
|
||||
The following nested keys are defined.
|
||||
|
||||
max
|
||||
The number of times a process in this cgroup or its
|
||||
descendants attempted an RDMA resource allocation that
|
||||
was rejected because this cgroup's own rdma.max limit
|
||||
was reached.
|
||||
|
||||
alloc_fail
|
||||
The number of RDMA resource allocation attempts
|
||||
originating from this cgroup that failed due to this
|
||||
cgroup's or an ancestor's rdma.max limit.
|
||||
|
||||
An example for mlx4 device follows::
|
||||
|
||||
mlx4_0 hca_handle.max=5 hca_handle.alloc_fail=0 hca_object.max=0 hca_object.alloc_fail=0
|
||||
|
||||
@@ -1570,7 +1570,7 @@ The following nested keys are defined.
|
||||
sock (npn)
|
||||
Amount of memory used in network transmission buffers
|
||||
|
||||
vmalloc (npn)
|
||||
vmalloc
|
||||
Amount of memory used for vmap backed memory.
|
||||
|
||||
shmem
|
||||
@@ -1735,7 +1735,7 @@ The following nested keys are defined.
|
||||
Number of pages written from zswap to swap.
|
||||
|
||||
zswap_incomp
|
||||
Number of incompressible pages currently stored in zswap
|
||||
Amount of memory used by incompressible pages currently stored in zswap
|
||||
without compression. These pages could not be compressed to
|
||||
a size smaller than PAGE_SIZE, so they are stored as-is.
|
||||
|
||||
@@ -2257,10 +2257,11 @@ groups D and F will influence each other. Group G will influence nobody::
|
||||
So the ideal way to configure this is to set io.latency in groups A, B, and C.
|
||||
Generally you do not want to set a value lower than the latency your device
|
||||
supports. Experiment to find the value that works best for your workload.
|
||||
Start at higher than the expected latency for your device and watch the
|
||||
avg_lat value in io.stat for your workload group to get an idea of the
|
||||
latency you see during normal operation. Use the avg_lat value as a basis for
|
||||
your real setting, setting at 10-15% higher than the value in io.stat.
|
||||
Start at higher than the expected latency for your device and, with
|
||||
blkcg_debug_stats enabled, watch the avg_lat value in io.stat for your
|
||||
workload group to get an idea of the latency you see during normal operation.
|
||||
Use the avg_lat value as a basis for your real setting, setting at 10-15%
|
||||
higher than the value in io.stat.
|
||||
|
||||
How IO Latency Throttling Works
|
||||
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
|
||||
@@ -2298,7 +2299,9 @@ IO Latency Interface Files
|
||||
|
||||
io.stat
|
||||
If the controller is enabled you will see extra stats in io.stat in
|
||||
addition to the normal ones.
|
||||
addition to the normal ones. These debug stats are only emitted when
|
||||
the blkcg_debug_stats module parameter is enabled (it is disabled by
|
||||
default).
|
||||
|
||||
depth
|
||||
This is the current queue depth for the group.
|
||||
@@ -2934,7 +2937,8 @@ include/linux/misc_cgroup.h.
|
||||
Misc Interface Files
|
||||
~~~~~~~~~~~~~~~~~~~~
|
||||
|
||||
Miscellaneous controller provides 3 interface files. If two misc resources (res_a and res_b) are registered then:
|
||||
Miscellaneous controller provides the following interface files. If two misc
|
||||
resources (res_a and res_b) are registered then:
|
||||
|
||||
misc.capacity
|
||||
A read-only flat-keyed file shown only in the root cgroup. It shows
|
||||
|
||||
@@ -47,11 +47,12 @@ ever have can be described at boot. There are no power-domain considerations
|
||||
as such devices are emulated.
|
||||
|
||||
CPU Hotplug on virtual systems is supported. It is distinct from physical
|
||||
CPU Hotplug as all resources are described as ``present``, but CPUs may be
|
||||
marked as disabled by firmware. Only the CPU's online/offline behaviour is
|
||||
influenced by firmware. An example is where a virtual machine boots with a
|
||||
single CPU, and additional CPUs are added once a cloud orchestrator deploys
|
||||
the workload.
|
||||
CPU Hotplug as all vCPU resources are statically described in the firmware
|
||||
configuration tables (e.g. MADT), meaning their maximum possible count is
|
||||
known at boot. However, vCPUs that are not enabled at boot are not marked
|
||||
as ``present`` by the kernel until they are hotplugged. An example is where
|
||||
a virtual machine boots with a single CPU, and additional CPUs are added
|
||||
once a cloud orchestrator deploys the workload.
|
||||
|
||||
For a virtual machine, the VMM (e.g. Qemu) plays the part of firmware.
|
||||
|
||||
@@ -60,16 +61,19 @@ brought online. Firmware can enforce its policy via PSCI's return codes. e.g.
|
||||
``DENIED``.
|
||||
|
||||
The ACPI tables must describe all the resources of the virtual machine. CPUs
|
||||
that firmware wishes to disable either from boot (or later) should not be
|
||||
``enabled`` in the MADT GICC structures, but should have the ``online capable``
|
||||
bit set, to indicate they can be enabled later. The boot CPU must be marked as
|
||||
``enabled``. The 'always on' GICR structure must be used to describe the
|
||||
redistributors.
|
||||
that are hot-pluggable must have the ``online capable`` bit set and the
|
||||
``enabled`` bit cleared in the MADT GICC structures to indicate they can be
|
||||
enabled later. The boot CPU must be marked as ``enabled`` with its
|
||||
``online capable`` bit cleared. The 'always on' GICR structure must be used
|
||||
to describe the redistributors.
|
||||
|
||||
CPUs described as ``online capable`` but not ``enabled`` can be set to enabled
|
||||
by the DSDT's Processor object's _STA method. On virtual systems the _STA method
|
||||
must always report the CPU as ``present``. Changes to the firmware policy can
|
||||
be notified to the OS via device-check or eject-request.
|
||||
must always set the ``ACPI_STA_DEVICE_PRESENT`` bit, while toggling the
|
||||
``ACPI_STA_DEVICE_ENABLED`` bit to reflect its plug status. The kernel will
|
||||
then dynamically mark the vCPU as ``present`` within the OS when the
|
||||
``ACPI_STA_DEVICE_ENABLED`` bit becomes set during hot-add. Changes to the
|
||||
firmware policy can be notified to the OS via device-check or eject-request.
|
||||
|
||||
CPUs described as ``enabled`` in the static table, should not have their _STA
|
||||
modified dynamically by firmware. Soft-restart features such as kexec will
|
||||
|
||||
@@ -82,121 +82,121 @@ The following keys are defined:
|
||||
version 1.0 of the RISC-V Vector extension manual.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
|
||||
supported, as defined in version 1.0 of the Bit-Manipulation ISA
|
||||
extensions.
|
||||
supported, as defined in version 1.0 of the Bit-Manipulation ISA
|
||||
extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZBB`: The Zbb extension is supported, as defined
|
||||
in version 1.0 of the Bit-Manipulation ISA extensions.
|
||||
in version 1.0 of the Bit-Manipulation ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZBS`: The Zbs extension is supported, as defined
|
||||
in version 1.0 of the Bit-Manipulation ISA extensions.
|
||||
in version 1.0 of the Bit-Manipulation ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZICBOZ`: The Zicboz extension is supported, as
|
||||
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZBC` The Zbc extension is supported, as defined
|
||||
in version 1.0 of the Bit-Manipulation ISA extensions.
|
||||
in version 1.0 of the Bit-Manipulation ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZBKB` The Zbkb extension is supported, as
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZBKC` The Zbkc extension is supported, as
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZBKX` The Zbkx extension is supported, as
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZKND` The Zknd extension is supported, as
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZKNE` The Zkne extension is supported, as
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZKNH` The Zknh extension is supported, as
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZKSED` The Zksed extension is supported, as
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZKSH` The Zksh extension is supported, as
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
defined in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZKT` The Zkt extension is supported, as defined
|
||||
in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
in version 1.0 of the Scalar Crypto ISA extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVBB`: The Zvbb extension is supported as
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVBC`: The Zvbc extension is supported as
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVKB`: The Zvkb extension is supported as
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVKG`: The Zvkg extension is supported as
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVKNED`: The Zvkned extension is supported as
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVKNHA`: The Zvknha extension is supported as
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVKNHB`: The Zvknhb extension is supported as
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVKSED`: The Zvksed extension is supported as
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVKSH`: The Zvksh extension is supported as
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVKT`: The Zvkt extension is supported as
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
defined in version 1.0 of the RISC-V Cryptography Extensions Volume II.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZFH`: The Zfh extension version 1.0 is supported
|
||||
as defined in the RISC-V ISA manual.
|
||||
as defined in the RISC-V ISA manual.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZFHMIN`: The Zfhmin extension version 1.0 is
|
||||
supported as defined in the RISC-V ISA manual.
|
||||
supported as defined in the RISC-V ISA manual.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTNTL`: The Zihintntl extension version 1.0
|
||||
is supported as defined in the RISC-V ISA manual.
|
||||
is supported as defined in the RISC-V ISA manual.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVFH`: The Zvfh extension is supported as
|
||||
defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
|
||||
("Remove draft warnings from Zvfh[min]").
|
||||
defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
|
||||
("Remove draft warnings from Zvfh[min]").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVFHMIN`: The Zvfhmin extension is supported as
|
||||
defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
|
||||
("Remove draft warnings from Zvfh[min]").
|
||||
defined in the RISC-V Vector manual starting from commit e2ccd0548d6c
|
||||
("Remove draft warnings from Zvfh[min]").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZFA`: The Zfa extension is supported as
|
||||
defined in the RISC-V ISA manual starting from commit 056b6ff467c7
|
||||
("Zfa is ratified").
|
||||
defined in the RISC-V ISA manual starting from commit 056b6ff467c7
|
||||
("Zfa is ratified").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZTSO`: The Ztso extension is supported as
|
||||
defined in the RISC-V ISA manual starting from commit 5618fb5a216b
|
||||
("Ztso is now ratified.")
|
||||
defined in the RISC-V ISA manual starting from commit 5618fb5a216b
|
||||
("Ztso is now ratified.")
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZACAS`: The Zacas extension is supported as
|
||||
defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
|
||||
from commit 5059e0ca641c ("update to ratified").
|
||||
defined in the Atomic Compare-and-Swap (CAS) instructions manual starting
|
||||
from commit 5059e0ca641c ("update to ratified").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZICNTR`: The Zicntr extension version 2.0
|
||||
is supported as defined in the RISC-V ISA manual.
|
||||
is supported as defined in the RISC-V ISA manual.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZICOND`: The Zicond extension is supported as
|
||||
defined in the RISC-V Integer Conditional (Zicond) operations extension
|
||||
manual starting from commit 95cf1f9 ("Add changes requested by Ved
|
||||
during signoff")
|
||||
defined in the RISC-V Integer Conditional (Zicond) operations extension
|
||||
manual starting from commit 95cf1f9 ("Add changes requested by Ved
|
||||
during signoff")
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZIHINTPAUSE`: The Zihintpause extension is
|
||||
supported as defined in the RISC-V ISA manual starting from commit
|
||||
d8ab5c78c207 ("Zihintpause is ratified").
|
||||
supported as defined in the RISC-V ISA manual starting from commit
|
||||
d8ab5c78c207 ("Zihintpause is ratified").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZIHPM`: The Zihpm extension version 2.0
|
||||
is supported as defined in the RISC-V ISA manual.
|
||||
is supported as defined in the RISC-V ISA manual.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVE32X`: The Vector sub-extension Zve32x is
|
||||
supported, as defined by version 1.0 of the RISC-V Vector extension manual.
|
||||
@@ -214,84 +214,89 @@ The following keys are defined:
|
||||
supported, as defined by version 1.0 of the RISC-V Vector extension manual.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is
|
||||
supported as defined in the RISC-V ISA manual starting from commit
|
||||
58220614a5f ("Zimop is ratified/1.0").
|
||||
supported as defined in the RISC-V ISA manual starting from commit
|
||||
58220614a5f ("Zimop is ratified/1.0").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard
|
||||
extensions for code size reduction, as ratified in commit 8be3419c1c0
|
||||
("Zcf doesn't exist on RV64 as it contains no instructions") of
|
||||
riscv-code-size-reduction.
|
||||
extensions for code size reduction, as ratified in commit 8be3419c1c0
|
||||
("Zcf doesn't exist on RV64 as it contains no instructions") of
|
||||
riscv-code-size-reduction.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard
|
||||
extensions for code size reduction, as ratified in commit 8be3419c1c0
|
||||
("Zcf doesn't exist on RV64 as it contains no instructions") of
|
||||
riscv-code-size-reduction.
|
||||
extensions for code size reduction, as ratified in commit 8be3419c1c0
|
||||
("Zcf doesn't exist on RV64 as it contains no instructions") of
|
||||
riscv-code-size-reduction.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard
|
||||
extensions for code size reduction, as ratified in commit 8be3419c1c0
|
||||
("Zcf doesn't exist on RV64 as it contains no instructions") of
|
||||
riscv-code-size-reduction.
|
||||
extensions for code size reduction, as ratified in commit 8be3419c1c0
|
||||
("Zcf doesn't exist on RV64 as it contains no instructions") of
|
||||
riscv-code-size-reduction.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard
|
||||
extensions for code size reduction, as ratified in commit 8be3419c1c0
|
||||
("Zcf doesn't exist on RV64 as it contains no instructions") of
|
||||
riscv-code-size-reduction.
|
||||
extensions for code size reduction, as ratified in commit 8be3419c1c0
|
||||
("Zcf doesn't exist on RV64 as it contains no instructions") of
|
||||
riscv-code-size-reduction.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZCMOP`: The Zcmop May-Be-Operations extension is
|
||||
supported as defined in the RISC-V ISA manual starting from commit
|
||||
c732a4f39a4 ("Zcmop is ratified/1.0").
|
||||
supported as defined in the RISC-V ISA manual starting from commit
|
||||
c732a4f39a4 ("Zcmop is ratified/1.0").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZAWRS`: The Zawrs extension is supported as
|
||||
ratified in commit 98918c844281 ("Merge pull request #1217 from
|
||||
riscv/zawrs") of riscv-isa-manual.
|
||||
ratified in commit 98918c844281 ("Merge pull request #1217 from
|
||||
riscv/zawrs") of riscv-isa-manual.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZAAMO`: The Zaamo extension is supported as
|
||||
defined in the in the RISC-V ISA manual starting from commit e87412e621f1
|
||||
("integrate Zaamo and Zalrsc text (#1304)").
|
||||
defined in the in the RISC-V ISA manual starting from commit e87412e621f1
|
||||
("integrate Zaamo and Zalrsc text (#1304)").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZALASR`: The Zalasr extension is supported as
|
||||
frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
|
||||
frozen at commit 194f0094 ("Version 0.9 for freeze") of riscv-zalasr.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZALRSC`: The Zalrsc extension is supported as
|
||||
defined in the in the RISC-V ISA manual starting from commit e87412e621f1
|
||||
("integrate Zaamo and Zalrsc text (#1304)").
|
||||
defined in the in the RISC-V ISA manual starting from commit e87412e621f1
|
||||
("integrate Zaamo and Zalrsc text (#1304)").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_SUPM`: The Supm extension is supported as
|
||||
defined in version 1.0 of the RISC-V Pointer Masking extensions.
|
||||
defined in version 1.0 of the RISC-V Pointer Masking extensions.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZFBFMIN`: The Zfbfmin extension is supported as
|
||||
defined in the RISC-V ISA manual starting from commit 4dc23d6229de
|
||||
("Added Chapter title to BF16").
|
||||
defined in the RISC-V ISA manual starting from commit 4dc23d6229de
|
||||
("Added Chapter title to BF16").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVFBFMIN`: The Zvfbfmin extension is supported as
|
||||
defined in the RISC-V ISA manual starting from commit 4dc23d6229de
|
||||
("Added Chapter title to BF16").
|
||||
defined in the RISC-V ISA manual starting from commit 4dc23d6229de
|
||||
("Added Chapter title to BF16").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZVFBFWMA`: The Zvfbfwma extension is supported as
|
||||
defined in the RISC-V ISA manual starting from commit 4dc23d6229de
|
||||
("Added Chapter title to BF16").
|
||||
defined in the RISC-V ISA manual starting from commit 4dc23d6229de
|
||||
("Added Chapter title to BF16").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZICBOM`: The Zicbom extension is supported, as
|
||||
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZABHA`: The Zabha extension is supported as
|
||||
ratified in commit 49f49c842ff9 ("Update to Rafified state") of
|
||||
riscv-zabha.
|
||||
ratified in commit 49f49c842ff9 ("Update to Rafified state") of
|
||||
riscv-zabha.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZICBOP`: The Zicbop extension is supported, as
|
||||
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZILSD`: The Zilsd extension is supported as
|
||||
defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
|
||||
load/store pair for RV32 with the main manual") of the riscv-isa-manual.
|
||||
defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
|
||||
load/store pair for RV32 with the main manual") of the riscv-isa-manual.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZCLSD`: The Zclsd extension is supported as
|
||||
defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
|
||||
load/store pair for RV32 with the main manual") of the riscv-isa-manual.
|
||||
defined in the RISC-V ISA manual starting from commit f88abf1 ("Integrating
|
||||
load/store pair for RV32 with the main manual") of the riscv-isa-manual.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZICFILP`: The Zicfilp extension is supported,
|
||||
as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI)
|
||||
extensions specification, ratified in commit 302a2d45c243
|
||||
("Update build-pdf.yml") of riscv-cfi.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: Deprecated. Returns similar values to
|
||||
:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
|
||||
mistakenly classified as a bitmask rather than a value.
|
||||
:c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`, but the key was
|
||||
mistakenly classified as a bitmask rather than a value.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_SCALAR_PERF`: An enum value describing
|
||||
the performance of misaligned scalar native word accesses on the selected set
|
||||
@@ -326,7 +331,7 @@ The following keys are defined:
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_TIME_CSR_FREQ`: Frequency (in Hz) of `time CSR`.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_MISALIGNED_VECTOR_PERF`: An enum value describing the
|
||||
performance of misaligned vector accesses on the selected set of processors.
|
||||
performance of misaligned vector accesses on the selected set of processors.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_MISALIGNED_VECTOR_UNKNOWN`: The performance of misaligned
|
||||
vector accesses is unknown.
|
||||
@@ -348,7 +353,7 @@ The following keys are defined:
|
||||
* MIPS
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XMIPSEXECTL`: The xmipsexectl vendor
|
||||
extension is supported in the MIPS ISA extensions spec.
|
||||
extension is supported in the MIPS ISA extensions spec.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_VENDOR_EXT_THEAD_0`: A bitmask containing the
|
||||
thead vendor extensions that are compatible with the
|
||||
@@ -357,8 +362,8 @@ The following keys are defined:
|
||||
* T-HEAD
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XTHEADVECTOR`: The xtheadvector vendor
|
||||
extension is supported in the T-Head ISA extensions spec starting from
|
||||
commit a18c801634 ("Add T-Head VECTOR vendor extension. ").
|
||||
extension is supported in the T-Head ISA extensions spec starting from
|
||||
commit a18c801634 ("Add T-Head VECTOR vendor extension. ").
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_ZICBOM_BLOCK_SIZE`: An unsigned int which
|
||||
represents the size of the Zicbom block in bytes.
|
||||
@@ -370,20 +375,20 @@ The following keys are defined:
|
||||
* SIFIVE
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCDOD`: The Xsfqmaccdod vendor
|
||||
extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
|
||||
Extensions Specification.
|
||||
extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
|
||||
Extensions Specification.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVQMACCQOQ`: The Xsfqmaccqoq vendor
|
||||
extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
|
||||
Instruction Extensions Specification.
|
||||
extension is supported in version 1.1 of SiFive Int8 Matrix Multiplication
|
||||
Instruction Extensions Specification.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFNRCLIPXFQF`: The Xsfvfnrclipxfqf
|
||||
vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
|
||||
Clip Instructions Extensions Specification.
|
||||
vendor extension is supported in version 1.0 of SiFive FP32-to-int8 Ranged
|
||||
Clip Instructions Extensions Specification.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_VENDOR_EXT_XSFVFWMACCQQQ`: The Xsfvfwmaccqqq
|
||||
vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
|
||||
Instruction Extensions Specification.
|
||||
vendor extension is supported in version 1.0 of Matrix Multiply Accumulate
|
||||
Instruction Extensions Specification.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_ZICBOP_BLOCK_SIZE`: An unsigned int which
|
||||
represents the size of the Zicbop block in bytes.
|
||||
@@ -391,3 +396,8 @@ The following keys are defined:
|
||||
* :c:macro:`RISCV_HWPROBE_KEY_IMA_EXT_1`: A bitmask containing additional
|
||||
extensions that are compatible with the
|
||||
:c:macro:`RISCV_HWPROBE_BASE_BEHAVIOR_IMA`: base system behavior.
|
||||
|
||||
* :c:macro:`RISCV_HWPROBE_EXT_ZICFISS`: The Zicfiss extension is supported,
|
||||
as defined in version 1.0 of the RISC-V Control-flow Integrity (CFI)
|
||||
extensions specification, ratified in commit 302a2d45c243
|
||||
("Update build-pdf.yml") of riscv-cfi.
|
||||
|
||||
@@ -6,14 +6,14 @@ Block ciphers
|
||||
AES
|
||||
---
|
||||
|
||||
Support for the AES block cipher.
|
||||
This API provides support for the AES block cipher.
|
||||
|
||||
.. kernel-doc:: include/crypto/aes.h
|
||||
|
||||
DES
|
||||
---
|
||||
|
||||
Support for the DES block cipher. This algorithm is obsolete and is supported
|
||||
only for backwards compatibility.
|
||||
This API provides support for the DES block cipher. This algorithm is obsolete
|
||||
and is supported only for backwards compatibility.
|
||||
|
||||
.. kernel-doc:: include/crypto/des.h
|
||||
|
||||
@@ -6,81 +6,83 @@ Hash functions, MACs, and XOFs
|
||||
AES-CMAC and AES-XCBC-MAC
|
||||
-------------------------
|
||||
|
||||
Support for the AES-CMAC and AES-XCBC-MAC message authentication codes.
|
||||
This API provides support for the AES-CMAC and AES-XCBC-MAC message
|
||||
authentication codes.
|
||||
|
||||
.. kernel-doc:: include/crypto/aes-cbc-macs.h
|
||||
|
||||
BLAKE2b
|
||||
-------
|
||||
|
||||
Support for the BLAKE2b cryptographic hash function.
|
||||
This API provides support for the BLAKE2b cryptographic hash function.
|
||||
|
||||
.. kernel-doc:: include/crypto/blake2b.h
|
||||
|
||||
BLAKE2s
|
||||
-------
|
||||
|
||||
Support for the BLAKE2s cryptographic hash function.
|
||||
This API provides support for the BLAKE2s cryptographic hash function.
|
||||
|
||||
.. kernel-doc:: include/crypto/blake2s.h
|
||||
|
||||
GHASH and POLYVAL
|
||||
-----------------
|
||||
|
||||
Support for the GHASH and POLYVAL universal hash functions. These algorithms
|
||||
are used only as internal components of other algorithms.
|
||||
This API provides support for the GHASH and POLYVAL universal hash functions.
|
||||
These algorithms are used only as internal components of other algorithms.
|
||||
|
||||
.. kernel-doc:: include/crypto/gf128hash.h
|
||||
|
||||
MD5
|
||||
---
|
||||
|
||||
Support for the MD5 cryptographic hash function and HMAC-MD5. This algorithm is
|
||||
obsolete and is supported only for backwards compatibility.
|
||||
This API provides support for the MD5 cryptographic hash function and HMAC-MD5.
|
||||
This algorithm is obsolete and is supported only for backwards compatibility.
|
||||
|
||||
.. kernel-doc:: include/crypto/md5.h
|
||||
|
||||
NH
|
||||
--
|
||||
|
||||
Support for the NH universal hash function. This algorithm is used only as an
|
||||
internal component of other algorithms.
|
||||
This API provides support for the NH universal hash function. This algorithm is
|
||||
used only as an internal component of other algorithms.
|
||||
|
||||
.. kernel-doc:: include/crypto/nh.h
|
||||
|
||||
Poly1305
|
||||
--------
|
||||
|
||||
Support for the Poly1305 universal hash function. This algorithm is used only
|
||||
as an internal component of other algorithms.
|
||||
This API provides support for the Poly1305 universal hash function. This
|
||||
algorithm is used only as an internal component of other algorithms.
|
||||
|
||||
.. kernel-doc:: include/crypto/poly1305.h
|
||||
|
||||
SHA-1
|
||||
-----
|
||||
|
||||
Support for the SHA-1 cryptographic hash function and HMAC-SHA1. This algorithm
|
||||
is obsolete and is supported only for backwards compatibility.
|
||||
This API provides support for the SHA-1 cryptographic hash function and
|
||||
HMAC-SHA1. This algorithm is obsolete and is supported only for backwards
|
||||
compatibility.
|
||||
|
||||
.. kernel-doc:: include/crypto/sha1.h
|
||||
|
||||
SHA-2
|
||||
-----
|
||||
|
||||
Support for the SHA-2 family of cryptographic hash functions, including SHA-224,
|
||||
SHA-256, SHA-384, and SHA-512. This also includes their corresponding HMACs:
|
||||
HMAC-SHA224, HMAC-SHA256, HMAC-SHA384, and HMAC-SHA512.
|
||||
This API provides support for the SHA-2 family of cryptographic hash functions,
|
||||
including SHA-224, SHA-256, SHA-384, and SHA-512. This also includes their
|
||||
corresponding HMACs: HMAC-SHA224, HMAC-SHA256, HMAC-SHA384, and HMAC-SHA512.
|
||||
|
||||
.. kernel-doc:: include/crypto/sha2.h
|
||||
|
||||
SHA-3
|
||||
-----
|
||||
|
||||
The SHA-3 functions are documented in :ref:`sha3`.
|
||||
The SHA-3 API is documented in :ref:`sha3`.
|
||||
|
||||
SM3
|
||||
---
|
||||
|
||||
Support for the SM3 cryptographic hash function.
|
||||
This API provides support for the SM3 cryptographic hash function.
|
||||
|
||||
.. kernel-doc:: include/crypto/sm3.h
|
||||
|
||||
@@ -6,6 +6,6 @@ Digital signature algorithms
|
||||
ML-DSA
|
||||
------
|
||||
|
||||
Support for the ML-DSA digital signature algorithm.
|
||||
This API provides support for the ML-DSA digital signature algorithm.
|
||||
|
||||
.. kernel-doc:: include/crypto/mldsa.h
|
||||
|
||||
@@ -4,8 +4,9 @@
|
||||
Crypto library
|
||||
==============
|
||||
|
||||
``lib/crypto/`` provides faster and easier access to cryptographic algorithms
|
||||
than the traditional crypto API.
|
||||
The Linux kernel's crypto library (``lib/crypto/``) provides kernel-internal
|
||||
users of cryptographic algorithms with faster and easier access to those
|
||||
algorithms than the traditional kernel crypto API.
|
||||
|
||||
Each cryptographic algorithm is supported via a set of dedicated functions.
|
||||
"Crypto agility", where needed, is left to calling code.
|
||||
|
||||
@@ -193,7 +193,6 @@ allOf:
|
||||
- mediatek,mt8183-mmc
|
||||
- mediatek,mt8186-mmc
|
||||
- mediatek,mt8188-mmc
|
||||
- mediatek,mt8189-mmc
|
||||
- mediatek,mt8195-mmc
|
||||
- mediatek,mt8196-mmc
|
||||
- mediatek,mt8516-mmc
|
||||
@@ -348,6 +347,34 @@ allOf:
|
||||
- const: axi_cg
|
||||
- const: ahb_cg
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mediatek,mt8189-mmc
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 6
|
||||
items:
|
||||
- description: source clock
|
||||
- description: HCLK which used for host
|
||||
- description: independent source clock gate
|
||||
- description: bus clock used for internal register access
|
||||
- description: peripheral bus clock gate
|
||||
- description: AXI bus clock gate
|
||||
- description: crypto clock used for data encrypt/decrypt (optional)
|
||||
clock-names:
|
||||
minItems: 6
|
||||
items:
|
||||
- const: source
|
||||
- const: hclk
|
||||
- const: source_cg
|
||||
- const: bus_clk
|
||||
- const: pclk_cg
|
||||
- const: axi_cg
|
||||
- const: crypto
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
|
||||
@@ -457,6 +457,13 @@ properties:
|
||||
merged in the riscv-isa-manual by commit dbc79cf28a2 ("Initial seed
|
||||
of zc.adoc to src tree.").
|
||||
|
||||
- const: zclsd
|
||||
description:
|
||||
The Zclsd extension implements the compressed (16-bit) version of the
|
||||
Load/Store Pair for RV32. As with Zilsd, this extension was ratified
|
||||
in commit f88abf1 ("Integrating load/store pair for RV32 with the
|
||||
main manual") of riscv-isa-manual.
|
||||
|
||||
- const: zcmop
|
||||
description:
|
||||
The standard Zcmop extension version 1.0, as ratified in commit
|
||||
@@ -487,6 +494,22 @@ properties:
|
||||
in commit 64074bc ("Update version numbers for Zfh/Zfinx") of
|
||||
riscv-isa-manual.
|
||||
|
||||
- const: zicbom
|
||||
description:
|
||||
The standard Zicbom extension for base cache management operations as
|
||||
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
|
||||
- const: zicbop
|
||||
description:
|
||||
The standard Zicbop extension for cache-block prefetch instructions
|
||||
as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
|
||||
riscv-CMOs.
|
||||
|
||||
- const: zicboz
|
||||
description:
|
||||
The standard Zicboz extension for cache-block zeroing as ratified
|
||||
in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
|
||||
- const: ziccamoa
|
||||
description:
|
||||
The standard Ziccamoa extension for main memory (cacheability and
|
||||
@@ -514,6 +537,66 @@ properties:
|
||||
guarantee on LR/SC sequences, as ratified in commit b1d806605f87
|
||||
("Updated to ratified state.") of the riscv profiles specification.
|
||||
|
||||
- const: zicfilp
|
||||
description: |
|
||||
The standard Zicfilp extension for enforcing forward edge
|
||||
control-flow integrity as ratified in commit 3f8e450 ("merge
|
||||
pull request #227 from ved-rivos/0709") of riscv-cfi
|
||||
github repo.
|
||||
|
||||
- const: zicfiss
|
||||
description: |
|
||||
The standard Zicfiss extension for enforcing backward edge
|
||||
control-flow integrity as ratified in commit 3f8e450 ("merge
|
||||
pull request #227 from ved-rivos/0709") of riscv-cfi
|
||||
github repo.
|
||||
|
||||
- const: zicntr
|
||||
description:
|
||||
The standard Zicntr extension for base counters and timers, as
|
||||
ratified in the 20191213 version of the unprivileged ISA
|
||||
specification.
|
||||
|
||||
- const: zicond
|
||||
description:
|
||||
The standard Zicond extension for conditional arithmetic and
|
||||
conditional-select/move operations as ratified in commit 95cf1f9
|
||||
("Add changes requested by Ved during signoff") of riscv-zicond.
|
||||
|
||||
- const: zicsr
|
||||
description: |
|
||||
The standard Zicsr extension for control and status register
|
||||
instructions, as ratified in the 20191213 version of the
|
||||
unprivileged ISA specification.
|
||||
|
||||
This does not include Chapter 10, "Counters", which documents
|
||||
special case read-only CSRs, that were moved into the Zicntr and
|
||||
Zihpm extensions after the ratification of the 20191213 version of
|
||||
the unprivileged specification.
|
||||
|
||||
- const: zifencei
|
||||
description:
|
||||
The standard Zifencei extension for instruction-fetch fence, as
|
||||
ratified in the 20191213 version of the unprivileged ISA
|
||||
specification.
|
||||
|
||||
- const: zihintntl
|
||||
description:
|
||||
The standard Zihintntl extension for non-temporal locality hints, as
|
||||
ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
|
||||
riscv-isa-manual.
|
||||
|
||||
- const: zihintpause
|
||||
description:
|
||||
The standard Zihintpause extension for pause hints, as ratified in
|
||||
commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
|
||||
|
||||
- const: zihpm
|
||||
description:
|
||||
The standard Zihpm extension for hardware performance counters, as
|
||||
ratified in the 20191213 version of the unprivileged ISA
|
||||
specification.
|
||||
|
||||
- const: zilsd
|
||||
description:
|
||||
The standard Zilsd extension which provides support for aligned
|
||||
@@ -521,12 +604,10 @@ properties:
|
||||
encodings, as ratified in commit f88abf1 ("Integrating
|
||||
load/store pair for RV32 with the main manual") of riscv-isa-manual.
|
||||
|
||||
- const: zclsd
|
||||
- const: zimop
|
||||
description:
|
||||
The Zclsd extension implements the compressed (16-bit) version of the
|
||||
Load/Store Pair for RV32. As with Zilsd, this extension was ratified
|
||||
in commit f88abf1 ("Integrating load/store pair for RV32 with the
|
||||
main manual") of riscv-isa-manual.
|
||||
The standard Zimop extension version 1.0, as ratified in commit
|
||||
58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
|
||||
|
||||
- const: zk
|
||||
description:
|
||||
@@ -590,87 +671,6 @@ properties:
|
||||
in version 1.0 of RISC-V Cryptography Extensions Volume I
|
||||
specification.
|
||||
|
||||
- const: zicbom
|
||||
description:
|
||||
The standard Zicbom extension for base cache management operations as
|
||||
ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
|
||||
- const: zicbop
|
||||
description:
|
||||
The standard Zicbop extension for cache-block prefetch instructions
|
||||
as ratified in commit 3dd606f ("Create cmobase-v1.0.pdf") of
|
||||
riscv-CMOs.
|
||||
|
||||
- const: zicboz
|
||||
description:
|
||||
The standard Zicboz extension for cache-block zeroing as ratified
|
||||
in commit 3dd606f ("Create cmobase-v1.0.pdf") of riscv-CMOs.
|
||||
|
||||
- const: zicfilp
|
||||
description: |
|
||||
The standard Zicfilp extension for enforcing forward edge
|
||||
control-flow integrity as ratified in commit 3f8e450 ("merge
|
||||
pull request #227 from ved-rivos/0709") of riscv-cfi
|
||||
github repo.
|
||||
|
||||
- const: zicfiss
|
||||
description: |
|
||||
The standard Zicfiss extension for enforcing backward edge
|
||||
control-flow integrity as ratified in commit 3f8e450 ("merge
|
||||
pull request #227 from ved-rivos/0709") of riscv-cfi
|
||||
github repo.
|
||||
|
||||
- const: zicntr
|
||||
description:
|
||||
The standard Zicntr extension for base counters and timers, as
|
||||
ratified in the 20191213 version of the unprivileged ISA
|
||||
specification.
|
||||
|
||||
- const: zicond
|
||||
description:
|
||||
The standard Zicond extension for conditional arithmetic and
|
||||
conditional-select/move operations as ratified in commit 95cf1f9
|
||||
("Add changes requested by Ved during signoff") of riscv-zicond.
|
||||
|
||||
- const: zicsr
|
||||
description: |
|
||||
The standard Zicsr extension for control and status register
|
||||
instructions, as ratified in the 20191213 version of the
|
||||
unprivileged ISA specification.
|
||||
|
||||
This does not include Chapter 10, "Counters", which documents
|
||||
special case read-only CSRs, that were moved into the Zicntr and
|
||||
Zihpm extensions after the ratification of the 20191213 version of
|
||||
the unprivileged specification.
|
||||
|
||||
- const: zifencei
|
||||
description:
|
||||
The standard Zifencei extension for instruction-fetch fence, as
|
||||
ratified in the 20191213 version of the unprivileged ISA
|
||||
specification.
|
||||
|
||||
- const: zihintpause
|
||||
description:
|
||||
The standard Zihintpause extension for pause hints, as ratified in
|
||||
commit d8ab5c7 ("Zihintpause is ratified") of the riscv-isa-manual.
|
||||
|
||||
- const: zihintntl
|
||||
description:
|
||||
The standard Zihintntl extension for non-temporal locality hints, as
|
||||
ratified in commit 0dc91f5 ("Zihintntl is ratified") of the
|
||||
riscv-isa-manual.
|
||||
|
||||
- const: zihpm
|
||||
description:
|
||||
The standard Zihpm extension for hardware performance counters, as
|
||||
ratified in the 20191213 version of the unprivileged ISA
|
||||
specification.
|
||||
|
||||
- const: zimop
|
||||
description:
|
||||
The standard Zimop extension version 1.0, as ratified in commit
|
||||
58220614a5f ("Zimop is ratified/1.0") of the riscv-isa-manual.
|
||||
|
||||
- const: ztso
|
||||
description:
|
||||
The standard Ztso extension for total store ordering, as ratified
|
||||
@@ -809,18 +809,18 @@ properties:
|
||||
instructions, as ratified in commit 56ed795 ("Update
|
||||
riscv-crypto-spec-vector.adoc") of riscv-crypto.
|
||||
|
||||
- const: zvksh
|
||||
description: |
|
||||
The standard Zvksh extension for ShangMi suite: SM3 secure hash
|
||||
instructions, as ratified in commit 56ed795 ("Update
|
||||
riscv-crypto-spec-vector.adoc") of riscv-crypto.
|
||||
|
||||
- const: zvksg
|
||||
description:
|
||||
The standard Zvksg extension for ShangMi algorithm suite with GCM
|
||||
instructions, as ratified in commit 56ed795 ("Update
|
||||
riscv-crypto-spec-vector.adoc") of riscv-crypto.
|
||||
|
||||
- const: zvksh
|
||||
description: |
|
||||
The standard Zvksh extension for ShangMi suite: SM3 secure hash
|
||||
instructions, as ratified in commit 56ed795 ("Update
|
||||
riscv-crypto-spec-vector.adoc") of riscv-crypto.
|
||||
|
||||
- const: zvkt
|
||||
description:
|
||||
The standard Zvkt extension for vector data-independent execution
|
||||
|
||||
@@ -21,6 +21,7 @@ properties:
|
||||
- qcom,sc8280xp-lpass-rx-macro
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,eliza-lpass-rx-macro
|
||||
- qcom,kaanapali-lpass-rx-macro
|
||||
- qcom,sm8650-lpass-rx-macro
|
||||
- qcom,sm8750-lpass-rx-macro
|
||||
|
||||
@@ -21,6 +21,7 @@ properties:
|
||||
- qcom,sc8280xp-lpass-tx-macro
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,eliza-lpass-tx-macro
|
||||
- qcom,kaanapali-lpass-tx-macro
|
||||
- qcom,sm8650-lpass-tx-macro
|
||||
- qcom,sm8750-lpass-tx-macro
|
||||
|
||||
@@ -21,6 +21,7 @@ properties:
|
||||
- qcom,sc8280xp-lpass-va-macro
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,eliza-lpass-va-macro
|
||||
- qcom,glymur-lpass-va-macro
|
||||
- qcom,kaanapali-lpass-va-macro
|
||||
- qcom,sm8650-lpass-va-macro
|
||||
|
||||
@@ -20,6 +20,7 @@ properties:
|
||||
- qcom,sc8280xp-lpass-wsa-macro
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,eliza-lpass-wsa-macro
|
||||
- qcom,glymur-lpass-wsa-macro
|
||||
- qcom,kaanapali-lpass-wsa-macro
|
||||
- qcom,sm8650-lpass-wsa-macro
|
||||
|
||||
@@ -23,6 +23,7 @@ properties:
|
||||
- const: qcom,sdm845-sndcard
|
||||
- items:
|
||||
- enum:
|
||||
- qcom,eliza-sndcard
|
||||
- qcom,kaanapali-sndcard
|
||||
- qcom,sm8550-sndcard
|
||||
- qcom,sm8650-sndcard
|
||||
|
||||
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Reference in New Issue
Block a user