mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branches 'clk-bindings', 'clk-cleanup', 'clk-pwm', 'clk-hw-device', 'clk-xilinx' and 'clk-adi' into clk-next
- Support atomic PWMs in the PWM clk driver - clk_hw_get_dev() and clk_hw_get_of_node() helpers * clk-bindings: (30 commits) dt-bindings: clock: convert lpc1850-cgu.txt to yaml format dt-bindings: clock: Convert qca,ath79-pll to DT schema dt-bindings: clock: Convert nuvoton,npcm750-clk to DT schema dt-bindings: clock: Convert moxa,moxart-clock to DT schema dt-bindings: clock: Convert microchip,pic32mzda-clk to DT schema dt-bindings: clock: Convert maxim,max9485 to DT schema dt-bindings: clock: Convert qcom,krait-cc to DT schema dt-bindings: clock: qcom: Remove double colon from description dt-bindings: clock: convert lpc1850-ccu.txt to yaml format dt-bindings: clock: Convert alphascale,asm9260-clock-controller to DT schema dt-bindings: clock: Convert marvell,armada-370-corediv-clock to DT schema dt-bindings: clock: Convert marvell,armada-3700-periph-clock to DT schema dt-bindings: clock: Convert marvell,mvebu-core-clock to DT schema dt-bindings: clock: Convert marvell,berlin2-clk to DT schema dt-bindings: clock: Convert marvell,dove-divider-clock to DT schema dt-bindings: clock: Convert marvell,armada-3700-tbg-clock to DT schema dt-bindings: clock: Convert marvell-armada-370-gating-clock to DT schema dt-bindings: clock: Convert marvell,armada-xp-cpu-clock to DT schema dt-bindings: clock: Convert TI-NSPIRE clocks to DT schema dt-bindings: clock: Convert lsi,axm5516-clks to DT schema ... * clk-cleanup: (29 commits) clk: clocking-wizard: Fix the round rate handling for versal clk: Fix typos clk: tegra: periph: Make tegra_clk_periph_ops static clk: tegra: periph: Fix error handling and resolve unsigned compare warning clk: imx: scu: convert from round_rate() to determine_rate() clk: imx: pllv4: convert from round_rate() to determine_rate() clk: imx: pllv3: convert from round_rate() to determine_rate() clk: imx: pllv2: convert from round_rate() to determine_rate() clk: imx: pll14xx: convert from round_rate() to determine_rate() clk: imx: pfd: convert from round_rate() to determine_rate() clk: imx: frac-pll: convert from round_rate() to determine_rate() clk: imx: fracn-gppll: convert from round_rate() to determine_rate() clk: imx: fixup-div: convert from round_rate() to determine_rate() clk: imx: cpu: convert from round_rate() to determine_rate() clk: imx: busy: convert from round_rate() to determine_rate() clk: imx: composite-93: remove round_rate() in favor of determine_rate() clk: imx: composite-8m: remove round_rate() in favor of determine_rate() clk: bcm: bcm2835: convert from round_rate() to determine_rate() MAINTAINERS: Include clk.py under COMMON CLK FRAMEWORK entry clk: ti: Simplify ti_find_clock_provider() ... * clk-pwm: clk: pwm: Make use of non-sleeping PWMs clk: pwm: Don't reconfigure running PWM at probe time clk: pwm: Convert to use pwm_apply_might_sleep() clk: pwm: Let .get_duty_cycle() return the real duty cycle * clk-hw-device: clk: tests: add clk_hw_get_dev() and clk_hw_get_of_node() tests clk: tests: Make clk_register_clk_parent_data_device_driver() common clk: add a clk_hw helpers to get the clock device or device_node * clk-xilinx: clk: xilinx: vcu: Update vcu init/reset sequence clk: xilinx: vcu: unregister pll_post only if registered correctly * clk-adi: clk: clk-axi-clkgen: fix coding style issues clk: clk-axi-clkgen move to min/max() clk: clk-axi-clkgen: detect axi_clkgen_limits at runtime include: adi-axi-common: add new helper macros include: linux: move adi-axi-common.h out of fpga clk: clk-axi-clkgen: make sure to include mod_devicetable.h clk: clk-axi-clkgen: fix fpfd_max frequency for zynq
This commit is contained in:
Stephen Boyd
@@ -1,114 +0,0 @@
|
||||
Alphascale Clock Controller
|
||||
|
||||
The ACC (Alphascale Clock Controller) is responsible for choosing proper
|
||||
clock source, setting dividers and clock gates.
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||||
|
||||
Required properties for the ACC node:
|
||||
- compatible: must be "alphascale,asm9260-clock-controller"
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||||
- reg: must contain the ACC register base and size
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||||
- #clock-cells : shall be set to 1.
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||||
|
||||
Simple one-cell clock specifier format is used, where the only cell is used
|
||||
as an index of the clock inside the provider.
|
||||
It is encouraged to use dt-binding for clock index definitions. SoC specific
|
||||
dt-binding should be included to the device tree descriptor. For example
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||||
Alphascale ASM9260:
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#include <dt-bindings/clock/alphascale,asm9260.h>
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|
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This binding contains two types of clock providers:
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_AHB_ - AHB gate;
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_SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
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All clock specific details can be found in the SoC documentation.
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CLKID_AHB_ROM 0
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CLKID_AHB_RAM 1
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CLKID_AHB_GPIO 2
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CLKID_AHB_MAC 3
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CLKID_AHB_EMI 4
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CLKID_AHB_USB0 5
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CLKID_AHB_USB1 6
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CLKID_AHB_DMA0 7
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CLKID_AHB_DMA1 8
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CLKID_AHB_UART0 9
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CLKID_AHB_UART1 10
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CLKID_AHB_UART2 11
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CLKID_AHB_UART3 12
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CLKID_AHB_UART4 13
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CLKID_AHB_UART5 14
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CLKID_AHB_UART6 15
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CLKID_AHB_UART7 16
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CLKID_AHB_UART8 17
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CLKID_AHB_UART9 18
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CLKID_AHB_I2S0 19
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CLKID_AHB_I2C0 20
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CLKID_AHB_I2C1 21
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CLKID_AHB_SSP0 22
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CLKID_AHB_IOCONFIG 23
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CLKID_AHB_WDT 24
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CLKID_AHB_CAN0 25
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CLKID_AHB_CAN1 26
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CLKID_AHB_MPWM 27
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CLKID_AHB_SPI0 28
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CLKID_AHB_SPI1 29
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CLKID_AHB_QEI 30
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CLKID_AHB_QUADSPI0 31
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CLKID_AHB_CAMIF 32
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CLKID_AHB_LCDIF 33
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CLKID_AHB_TIMER0 34
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CLKID_AHB_TIMER1 35
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CLKID_AHB_TIMER2 36
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CLKID_AHB_TIMER3 37
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CLKID_AHB_IRQ 38
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CLKID_AHB_RTC 39
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CLKID_AHB_NAND 40
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CLKID_AHB_ADC0 41
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CLKID_AHB_LED 42
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CLKID_AHB_DAC0 43
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CLKID_AHB_LCD 44
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CLKID_AHB_I2S1 45
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CLKID_AHB_MAC1 46
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CLKID_SYS_CPU 47
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CLKID_SYS_AHB 48
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CLKID_SYS_I2S0M 49
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CLKID_SYS_I2S0S 50
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CLKID_SYS_I2S1M 51
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CLKID_SYS_I2S1S 52
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CLKID_SYS_UART0 53
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CLKID_SYS_UART1 54
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CLKID_SYS_UART2 55
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CLKID_SYS_UART3 56
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CLKID_SYS_UART4 56
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CLKID_SYS_UART5 57
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CLKID_SYS_UART6 58
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CLKID_SYS_UART7 59
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CLKID_SYS_UART8 60
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CLKID_SYS_UART9 61
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CLKID_SYS_SPI0 62
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CLKID_SYS_SPI1 63
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CLKID_SYS_QUADSPI 64
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CLKID_SYS_SSP0 65
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CLKID_SYS_NAND 66
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CLKID_SYS_TRACE 67
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CLKID_SYS_CAMM 68
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CLKID_SYS_WDT 69
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CLKID_SYS_CLKOUT 70
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CLKID_SYS_MAC 71
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CLKID_SYS_LCD 72
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CLKID_SYS_ADCANA 73
|
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|
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Example of clock consumer with _SYS_ and _AHB_ sinks.
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uart4: serial@80010000 {
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compatible = "alphascale,asm9260-uart";
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reg = <0x80010000 0x4000>;
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clocks = <&acc CLKID_SYS_UART4>, <&acc CLKID_AHB_UART4>;
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interrupts = <19>;
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};
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Clock consumer with only one, _AHB_ sink.
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timer0: timer@80088000 {
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compatible = "alphascale,asm9260-timer";
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reg = <0x80088000 0x4000>;
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clocks = <&acc CLKID_AHB_TIMER0>;
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interrupts = <29>;
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};
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@@ -0,0 +1,49 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
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$id: http://devicetree.org/schemas/clock/alphascale,asm9260-clock-controller.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Alphascale Clock Controller
|
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|
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maintainers:
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- Oleksij Rempel <linux@rempel-privat.de>
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|
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description: |
|
||||
The ACC (Alphascale Clock Controller) is responsible for choosing proper
|
||||
clock source, setting dividers and clock gates.
|
||||
|
||||
Simple one-cell clock specifier format is used, where the only cell is used
|
||||
as an index of the clock inside the provider.
|
||||
It is encouraged to use dt-binding for clock index definitions. SoC specific
|
||||
dt-binding should be included to the device tree descriptor. For example
|
||||
Alphascale ASM9260:
|
||||
|
||||
#include <dt-bindings/clock/alphascale,asm9260.h>
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||||
|
||||
This binding contains two types of clock providers:
|
||||
|
||||
_AHB_ - AHB gate;
|
||||
_SYS_ - adjustable clock source. Not all peripheral have _SYS_ clock provider.
|
||||
|
||||
All clock specific details can be found in the SoC documentation.
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properties:
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compatible:
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const: alphascale,asm9260-clock-controller
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reg:
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maxItems: 1
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'#clock-cells':
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const: 1
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clocks:
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maxItems: 1
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required:
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- compatible
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- reg
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- '#clock-cells'
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|
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additionalProperties: false
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||||
@@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
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||||
$id: http://devicetree.org/schemas/clock/apm,xgene-device-clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: APM X-Gene SoC device clocks
|
||||
|
||||
maintainers:
|
||||
- Khuong Dinh <khuong@os.amperecomputing.com>
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|
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properties:
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||||
compatible:
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const: apm,xgene-device-clock
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reg:
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minItems: 1
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maxItems: 2
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reg-names:
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items:
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- enum: [ csr-reg, div-reg ]
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- const: div-reg
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minItems: 1
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clocks:
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maxItems: 1
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"#clock-cells":
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const: 1
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clock-output-names:
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maxItems: 1
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clock-names:
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maxItems: 1
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csr-offset:
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description: Offset to the CSR reset register
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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csr-mask:
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description: CSR reset mask bit
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0xf
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enable-offset:
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description: Offset to the enable register
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 8
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enable-mask:
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description: CSR enable mask bit
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0xf
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divider-offset:
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description: Offset to the divider register
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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divider-width:
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description: Width of the divider register
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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divider-shift:
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description: Bit shift of the divider register
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$ref: /schemas/types.yaml#/definitions/uint32
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default: 0
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|
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required:
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- compatible
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- reg
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- clocks
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- '#clock-cells'
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- clock-output-names
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additionalProperties: false
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@@ -0,0 +1,50 @@
|
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/apm,xgene-socpll-clock.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: APM X-Gene SoC PLL, PCPPLL, and PMD clocks
|
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|
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maintainers:
|
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- Khuong Dinh <khuong@os.amperecomputing.com>
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|
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properties:
|
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compatible:
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items:
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- enum:
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- apm,xgene-pcppll-clock
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- apm,xgene-pcppll-v2-clock
|
||||
- apm,xgene-pmd-clock
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- apm,xgene-socpll-clock
|
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- apm,xgene-socpll-v2-clock
|
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|
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reg:
|
||||
maxItems: 1
|
||||
|
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reg-names:
|
||||
items:
|
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- enum: [ csr-reg, div-reg ]
|
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- const: div-reg
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minItems: 1
|
||||
|
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clocks:
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maxItems: 1
|
||||
|
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clock-names:
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enum: [ pcppll, socpll ]
|
||||
|
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"#clock-cells":
|
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const: 1
|
||||
|
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clock-output-names:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- '#clock-cells'
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- clock-output-names
|
||||
|
||||
additionalProperties: false
|
||||
@@ -1,71 +0,0 @@
|
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* Peripheral Clock bindings for Marvell Armada 37xx SoCs
|
||||
|
||||
Marvell Armada 37xx SoCs provide peripheral clocks which are
|
||||
used as clock source for the peripheral of the SoC.
|
||||
|
||||
There are two different blocks associated to north bridge and south
|
||||
bridge.
|
||||
|
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The peripheral clock consumer should specify the desired clock by
|
||||
having the clock ID in its "clocks" phandle cell.
|
||||
|
||||
The following is a list of provided IDs for Armada 3700 North bridge clocks:
|
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ID Clock name Description
|
||||
-----------------------------------
|
||||
0 mmc MMC controller
|
||||
1 sata_host Sata Host
|
||||
2 sec_at Security AT
|
||||
3 sac_dap Security DAP
|
||||
4 tsecm Security Engine
|
||||
5 setm_tmx Serial Embedded Trace Module
|
||||
6 avs Adaptive Voltage Scaling
|
||||
7 sqf SPI
|
||||
8 pwm PWM
|
||||
9 i2c_2 I2C 2
|
||||
10 i2c_1 I2C 1
|
||||
11 ddr_phy DDR PHY
|
||||
12 ddr_fclk DDR F clock
|
||||
13 trace Trace
|
||||
14 counter Counter
|
||||
15 eip97 EIP 97
|
||||
16 cpu CPU
|
||||
|
||||
The following is a list of provided IDs for Armada 3700 South bridge clocks:
|
||||
ID Clock name Description
|
||||
-----------------------------------
|
||||
0 gbe-50 50 MHz parent clock for Gigabit Ethernet
|
||||
1 gbe-core parent clock for Gigabit Ethernet core
|
||||
2 gbe-125 125 MHz parent clock for Gigabit Ethernet
|
||||
3 gbe1-50 50 MHz clock for Gigabit Ethernet port 1
|
||||
4 gbe0-50 50 MHz clock for Gigabit Ethernet port 0
|
||||
5 gbe1-125 125 MHz clock for Gigabit Ethernet port 1
|
||||
6 gbe0-125 125 MHz clock for Gigabit Ethernet port 0
|
||||
7 gbe1-core Gigabit Ethernet core port 1
|
||||
8 gbe0-core Gigabit Ethernet core port 0
|
||||
9 gbe-bm Gigabit Ethernet Buffer Manager
|
||||
10 sdio SDIO
|
||||
11 usb32-sub2-sys USB 2 clock
|
||||
12 usb32-ss-sys USB 3 clock
|
||||
13 pcie PCIe controller
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible : shall be "marvell,armada-3700-periph-clock-nb" for the
|
||||
north bridge block, or
|
||||
"marvell,armada-3700-periph-clock-sb" for the south bridge block
|
||||
- reg : must be the register address of North/South Bridge Clock register
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
- clocks : list of the parent clock phandle in the following order:
|
||||
TBG-A P, TBG-B P, TBG-A S, TBG-B S and finally the xtal clock.
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
nb_perih_clk: nb-periph-clk@13000{
|
||||
compatible = "marvell,armada-3700-periph-clock-nb";
|
||||
reg = <0x13000 0x1000>;
|
||||
clocks = <&tbg 0>, <&tbg 1>, <&tbg 2>,
|
||||
<&tbg 3>, <&xtalclk>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -1,27 +0,0 @@
|
||||
* Time Base Generator Clock bindings for Marvell Armada 37xx SoCs
|
||||
|
||||
Marvell Armada 37xx SoCs provide Time Base Generator clocks which are
|
||||
used as parent clocks for the peripheral clocks.
|
||||
|
||||
The TBG clock consumer should specify the desired clock by having the
|
||||
clock ID in its "clocks" phandle cell.
|
||||
|
||||
The following is a list of provided IDs and clock names on Armada 3700:
|
||||
0 = TBG A P
|
||||
1 = TBG B P
|
||||
2 = TBG A S
|
||||
3 = TBG B S
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "marvell,armada-3700-tbg-clock"
|
||||
- reg : must be the register address of North Bridge PLL register
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
Example:
|
||||
|
||||
tbg: tbg@13200 {
|
||||
compatible = "marvell,armada-3700-tbg-clock";
|
||||
reg = <0x13200 0x1000>;
|
||||
clocks = <&xtalclk>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -1,41 +0,0 @@
|
||||
* Clock bindings for Axis ARTPEC-6 chip
|
||||
|
||||
The bindings are based on the clock provider binding in
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
External clocks:
|
||||
----------------
|
||||
|
||||
There are two external inputs to the main clock controller which should be
|
||||
provided using the common clock bindings.
|
||||
- "sys_refclk": External 50 Mhz oscillator (required)
|
||||
- "i2s_refclk": Alternate audio reference clock (optional).
|
||||
|
||||
Main clock controller
|
||||
---------------------
|
||||
|
||||
Required properties:
|
||||
- #clock-cells: Should be <1>
|
||||
See dt-bindings/clock/axis,artpec6-clkctrl.h for the list of valid identifiers.
|
||||
- compatible: Should be "axis,artpec6-clkctrl"
|
||||
- reg: Must contain the base address and length of the system controller
|
||||
- clocks: Must contain a phandle entry for each clock in clock-names
|
||||
- clock-names: Must include the external oscillator ("sys_refclk"). Optional
|
||||
ones are the audio reference clock ("i2s_refclk") and the audio fractional
|
||||
dividers ("frac_clk0" and "frac_clk1").
|
||||
|
||||
Examples:
|
||||
|
||||
ext_clk: ext_clk {
|
||||
#clock-cells = <0>;
|
||||
compatible = "fixed-clock";
|
||||
clock-frequency = <50000000>;
|
||||
};
|
||||
|
||||
clkctrl: clkctrl@f8000000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "axis,artpec6-clkctrl";
|
||||
reg = <0xf8000000 0x48>;
|
||||
clocks = <&ext_clk>;
|
||||
clock-names = "sys_refclk";
|
||||
};
|
||||
@@ -0,0 +1,55 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/axis,artpec6-clkctrl.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Axis ARTPEC-6 clock controller
|
||||
|
||||
maintainers:
|
||||
- Lars Persson <lars.persson@axis.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: axis,artpec6-clkctrl
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: external 50 MHz oscillator.
|
||||
- description: optional audio reference clock.
|
||||
- description: fractional audio clock divider 0.
|
||||
- description: fractional audio clock divider 1.
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: sys_refclk
|
||||
- const: i2s_refclk
|
||||
- const: frac_clk0
|
||||
- const: frac_clk1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#clock-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@f8000000 {
|
||||
compatible = "axis,artpec6-clkctrl";
|
||||
reg = <0xf8000000 0x48>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&ext_clk>;
|
||||
clock-names = "sys_refclk";
|
||||
};
|
||||
@@ -1,60 +0,0 @@
|
||||
Broadcom BCM2835 CPRMAN clocks
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
The CPRMAN clock controller generates clocks in the audio power domain
|
||||
of the BCM2835. There is a level of PLLs deriving from an external
|
||||
oscillator, a level of PLL dividers that produce channels off of the
|
||||
few PLLs, and a level of mostly-generic clock generators sourcing from
|
||||
the PLL channels. Most other hardware components source from the
|
||||
clock generators, but a few (like the ARM or HDMI) will source from
|
||||
the PLL dividers directly.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of the following,
|
||||
"brcm,bcm2711-cprman"
|
||||
"brcm,bcm2835-cprman"
|
||||
- #clock-cells: Should be <1>. The permitted clock-specifier values can be
|
||||
found in include/dt-bindings/clock/bcm2835.h
|
||||
- reg: Specifies base physical address and size of the registers
|
||||
- clocks: phandles to the parent clocks used as input to the module, in
|
||||
the following order:
|
||||
|
||||
- External oscillator
|
||||
- DSI0 byte clock
|
||||
- DSI0 DDR2 clock
|
||||
- DSI0 DDR clock
|
||||
- DSI1 byte clock
|
||||
- DSI1 DDR2 clock
|
||||
- DSI1 DDR clock
|
||||
|
||||
Only external oscillator is required. The DSI clocks may
|
||||
not be present, in which case their children will be
|
||||
unusable.
|
||||
|
||||
Example:
|
||||
|
||||
clk_osc: clock@3 {
|
||||
compatible = "fixed-clock";
|
||||
reg = <3>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "osc";
|
||||
clock-frequency = <19200000>;
|
||||
};
|
||||
|
||||
clocks: cprman@7e101000 {
|
||||
compatible = "brcm,bcm2835-cprman";
|
||||
#clock-cells = <1>;
|
||||
reg = <0x7e101000 0x2000>;
|
||||
clocks = <&clk_osc>;
|
||||
};
|
||||
|
||||
i2c0: i2c@7e205000 {
|
||||
compatible = "brcm,bcm2835-i2c";
|
||||
reg = <0x7e205000 0x1000>;
|
||||
interrupts = <2 21>;
|
||||
clocks = <&clocks BCM2835_CLOCK_VPU>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
};
|
||||
@@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/brcm,bcm2835-cprman.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM2835 CPRMAN clocks
|
||||
|
||||
maintainers:
|
||||
- Stefan Wahren <wahrenst@gmx.net>
|
||||
- Raspberry Pi Kernel Maintenance <kernel-list@raspberrypi.com>
|
||||
|
||||
description:
|
||||
The CPRMAN clock controller generates clocks in the audio power domain of the
|
||||
BCM2835. There is a level of PLLs deriving from an external oscillator, a
|
||||
level of PLL dividers that produce channels off of the few PLLs, and a level
|
||||
of mostly-generic clock generators sourcing from the PLL channels. Most other
|
||||
hardware components source from the clock generators, but a few (like the ARM
|
||||
or HDMI) will source from the PLL dividers directly.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,bcm2711-cprman
|
||||
- brcm,bcm2835-cprman
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: External oscillator clock.
|
||||
- description: DSI0 byte clock.
|
||||
- description: DSI0 DDR2 clock.
|
||||
- description: DSI0 DDR clock.
|
||||
- description: DSI1 byte clock.
|
||||
- description: DSI1 DDR2 clock.
|
||||
- description: DSI1 DDR clock.
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#clock-cells'
|
||||
- reg
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@7e101000 {
|
||||
compatible = "brcm,bcm2835-cprman";
|
||||
reg = <0x7e101000 0x2000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&clk_osc>;
|
||||
};
|
||||
@@ -1,36 +0,0 @@
|
||||
Broadcom BCM53573 ILP clock
|
||||
===========================
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
This binding is used for ILP clock (sometimes referred as "slow clock")
|
||||
on Broadcom BCM53573 devices using Cortex-A7 CPU.
|
||||
|
||||
ILP's rate has to be calculated on runtime and it depends on ALP clock
|
||||
which has to be referenced.
|
||||
|
||||
This clock is part of PMU (Power Management Unit), a Broadcom's device
|
||||
handing power-related aspects. Its node must be sub-node of the PMU
|
||||
device.
|
||||
|
||||
Required properties:
|
||||
- compatible: "brcm,bcm53573-ilp"
|
||||
- clocks: has to reference an ALP clock
|
||||
- #clock-cells: should be <0>
|
||||
- clock-output-names: from common clock bindings, should contain clock
|
||||
name
|
||||
|
||||
Example:
|
||||
|
||||
pmu@18012000 {
|
||||
compatible = "simple-mfd", "syscon";
|
||||
reg = <0x18012000 0x00001000>;
|
||||
|
||||
ilp {
|
||||
compatible = "brcm,bcm53573-ilp";
|
||||
clocks = <&alp>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "ilp";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,46 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/brcm,bcm53573-ilp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Broadcom BCM53573 ILP clock
|
||||
|
||||
maintainers:
|
||||
- Rafał Miłecki <rafal@milecki.pl>
|
||||
|
||||
description: >
|
||||
ILP clock (sometimes referred as "slow clock") on Broadcom BCM53573 devices
|
||||
using Cortex-A7 CPU.
|
||||
|
||||
ILP's rate has to be calculated on runtime and it depends on ALP clock which
|
||||
has to be referenced.
|
||||
|
||||
This clock is part of PMU (Power Management Unit), a Broadcom device handling
|
||||
power-related aspects. Its node must be sub-node of the PMU device.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: brcm,bcm53573-ilp
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
|
||||
clock-output-names:
|
||||
items:
|
||||
- const: ilp
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ilp {
|
||||
compatible = "brcm,bcm53573-ilp";
|
||||
clocks = <&alp>;
|
||||
#clock-cells = <0>;
|
||||
clock-output-names = "ilp";
|
||||
};
|
||||
@@ -1,24 +0,0 @@
|
||||
Gated Clock Controller Bindings for MIPS based BCM63XX SoCs
|
||||
|
||||
Required properties:
|
||||
- compatible: must be one of:
|
||||
"brcm,bcm3368-clocks"
|
||||
"brcm,bcm6318-clocks"
|
||||
"brcm,bcm6318-ubus-clocks"
|
||||
"brcm,bcm6328-clocks"
|
||||
"brcm,bcm6358-clocks"
|
||||
"brcm,bcm6362-clocks"
|
||||
"brcm,bcm6368-clocks"
|
||||
"brcm,bcm63268-clocks"
|
||||
|
||||
- reg: Address and length of the register set
|
||||
- #clock-cells: must be <1>
|
||||
|
||||
|
||||
Example:
|
||||
|
||||
clkctl: clock-controller@10000004 {
|
||||
compatible = "brcm,bcm6328-clocks";
|
||||
reg = <0x10000004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,44 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/brcm,bcm63xx-clocks.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MIPS based BCM63XX SoCs Gated Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Álvaro Fernández Rojas <noltari@gmail.com>
|
||||
- Jonas Gorski <jonas.gorski@gmail.com>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- brcm,bcm3368-clocks
|
||||
- brcm,bcm6318-clocks
|
||||
- brcm,bcm6318-ubus-clocks
|
||||
- brcm,bcm6328-clocks
|
||||
- brcm,bcm6358-clocks
|
||||
- brcm,bcm6362-clocks
|
||||
- brcm,bcm6368-clocks
|
||||
- brcm,bcm63268-clocks
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@10000004 {
|
||||
compatible = "brcm,bcm6328-clocks";
|
||||
reg = <0x10000004 0x4>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,47 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/cirrus,ep7209-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Cirrus Logic CLPS711X Clock Controller
|
||||
|
||||
maintainers:
|
||||
- Alexander Shiyan <shc_work@mail.ru>
|
||||
|
||||
description:
|
||||
See include/dt-bindings/clock/clps711x-clock.h for the full list of CLPS711X
|
||||
clock IDs.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: cirrus,ep7312-clk
|
||||
- const: cirrus,ep7209-clk
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
startup-frequency:
|
||||
description: Factory set CPU startup frequency in HZ.
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
|
||||
"#clock-cells":
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- startup-frequency
|
||||
- "#clock-cells"
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
clock-controller@80000000 {
|
||||
compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
|
||||
reg = <0x80000000 0xc000>;
|
||||
#clock-cells = <1>;
|
||||
startup-frequency = <73728000>;
|
||||
};
|
||||
@@ -1,19 +0,0 @@
|
||||
* Clock bindings for the Cirrus Logic CLPS711X CPUs
|
||||
|
||||
Required properties:
|
||||
- compatible : Shall contain "cirrus,ep7209-clk".
|
||||
- reg : Address of the internal register set.
|
||||
- startup-frequency: Factory set CPU startup frequency in HZ.
|
||||
- #clock-cells : Should be <1>.
|
||||
|
||||
The clock consumer should specify the desired clock by having the clock
|
||||
ID in its "clocks" phandle cell. See include/dt-bindings/clock/clps711x-clock.h
|
||||
for the full list of CLPS711X clock IDs.
|
||||
|
||||
Example:
|
||||
clks: clks@80000000 {
|
||||
#clock-cells = <1>;
|
||||
compatible = "cirrus,ep7312-clk", "cirrus,ep7209-clk";
|
||||
reg = <0x80000000 0xc000>;
|
||||
startup-frequency = <73728000>;
|
||||
};
|
||||
@@ -1,28 +0,0 @@
|
||||
PLL divider based Dove clocks
|
||||
|
||||
Marvell Dove has a 2GHz PLL, which feeds into a set of dividers to provide
|
||||
high speed clocks for a number of peripherals. These dividers are part of
|
||||
the PMU, and thus this node should be a child of the PMU node.
|
||||
|
||||
The following clocks are provided:
|
||||
|
||||
ID Clock
|
||||
-------------
|
||||
0 AXI bus clock
|
||||
1 GPU clock
|
||||
2 VMeta clock
|
||||
3 LCD clock
|
||||
|
||||
Required properties:
|
||||
- compatible : shall be "marvell,dove-divider-clock"
|
||||
- reg : shall be the register address of the Core PLL and Clock Divider
|
||||
Control 0 register. This will cover that register, as well as the
|
||||
Core PLL and Clock Divider Control 1 register. Thus, it will have
|
||||
a size of 8.
|
||||
- #clock-cells : from common clock binding; shall be set to 1
|
||||
|
||||
divider_clk: core-clock@64 {
|
||||
compatible = "marvell,dove-divider-clock";
|
||||
reg = <0x0064 0x8>;
|
||||
#clock-cells = <1>;
|
||||
};
|
||||
@@ -0,0 +1,136 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/img,pistachio-clk.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Imagination Technologies Pistachio SoC clock controllers
|
||||
|
||||
maintainers:
|
||||
- Andrew Bresticker <abrestic@chromium.org>
|
||||
|
||||
description: |
|
||||
Pistachio has four clock controllers (core clock, peripheral clock, peripheral
|
||||
general control, and top general control) which are instantiated individually
|
||||
from the device-tree.
|
||||
|
||||
Core clock controller:
|
||||
|
||||
The core clock controller generates clocks for the CPU, RPU (WiFi + BT
|
||||
co-processor), audio, and several peripherals.
|
||||
|
||||
Peripheral clock controller:
|
||||
|
||||
The peripheral clock controller generates clocks for the DDR, ROM, and other
|
||||
peripherals. The peripheral system clock ("periph_sys") generated by the core
|
||||
clock controller is the input clock to the peripheral clock controller.
|
||||
|
||||
Peripheral general control:
|
||||
|
||||
The peripheral general control block generates system interface clocks and
|
||||
resets for various peripherals. It also contains miscellaneous peripheral
|
||||
control registers.
|
||||
|
||||
Top-level general control:
|
||||
|
||||
The top-level general control block contains miscellaneous control registers
|
||||
and gates for the external clocks "audio_clk_in" and "enet_clk_in".
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- img,pistachio-clk
|
||||
- img,pistachio-clk-periph
|
||||
- img,pistachio-cr-periph
|
||||
- img,pistachio-cr-top
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: img,pistachio-clk
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External 52Mhz oscillator
|
||||
- description: Alternate audio reference clock
|
||||
- description: Alternate ethernet PHY clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: xtal
|
||||
- const: audio_refclk_ext_gate
|
||||
- const: ext_enet_in_gate
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: img,pistachio-clk-periph
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: Peripheral system clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: periph_sys_core
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: img,pistachio-cr-periph
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: System interface clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: sys
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: img,pistachio-cr-top
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: External audio reference clock
|
||||
- description: External ethernet PHY clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: audio_clk_in
|
||||
- const: enet_clk_in
|
||||
|
||||
additionalProperties: false
|
||||
@@ -1,77 +0,0 @@
|
||||
* NXP LPC1850 Clock Control Unit (CCU)
|
||||
|
||||
Each CGU base clock has several clock branches which can be turned on
|
||||
or off independently by the Clock Control Units CCU1 or CCU2. The
|
||||
branch clocks are distributed between CCU1 and CCU2.
|
||||
|
||||
- Above text taken from NXP LPC1850 User Manual.
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Should be "nxp,lpc1850-ccu"
|
||||
- reg:
|
||||
Shall define the base and range of the address space
|
||||
containing clock control registers
|
||||
- #clock-cells:
|
||||
Shall have value <1>. The permitted clock-specifier values
|
||||
are the branch clock names defined in table below.
|
||||
- clocks:
|
||||
Shall contain a list of phandles for the base clocks routed
|
||||
from the CGU to the specific CCU. See mapping of base clocks
|
||||
and CCU in table below.
|
||||
- clock-names:
|
||||
Shall contain a list of names for the base clock routed
|
||||
from the CGU to the specific CCU. Valid CCU clock names:
|
||||
"base_usb0_clk", "base_periph_clk", "base_usb1_clk",
|
||||
"base_cpu_clk", "base_spifi_clk", "base_spi_clk",
|
||||
"base_apb1_clk", "base_apb3_clk", "base_adchs_clk",
|
||||
"base_sdio_clk", "base_ssp0_clk", "base_ssp1_clk",
|
||||
"base_uart0_clk", "base_uart1_clk", "base_uart2_clk",
|
||||
"base_uart3_clk", "base_audio_clk"
|
||||
|
||||
Which branch clocks that are available on the CCU depends on the
|
||||
specific LPC part. Check the user manual for your specific part.
|
||||
|
||||
A list of CCU clocks can be found in dt-bindings/clock/lpc18xx-ccu.h.
|
||||
|
||||
Example board file:
|
||||
|
||||
soc {
|
||||
ccu1: clock-controller@40051000 {
|
||||
compatible = "nxp,lpc1850-ccu";
|
||||
reg = <0x40051000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&cgu BASE_APB3_CLK>, <&cgu BASE_APB1_CLK>,
|
||||
<&cgu BASE_SPIFI_CLK>, <&cgu BASE_CPU_CLK>,
|
||||
<&cgu BASE_PERIPH_CLK>, <&cgu BASE_USB0_CLK>,
|
||||
<&cgu BASE_USB1_CLK>, <&cgu BASE_SPI_CLK>;
|
||||
clock-names = "base_apb3_clk", "base_apb1_clk",
|
||||
"base_spifi_clk", "base_cpu_clk",
|
||||
"base_periph_clk", "base_usb0_clk",
|
||||
"base_usb1_clk", "base_spi_clk";
|
||||
};
|
||||
|
||||
ccu2: clock-controller@40052000 {
|
||||
compatible = "nxp,lpc1850-ccu";
|
||||
reg = <0x40052000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&cgu BASE_AUDIO_CLK>, <&cgu BASE_UART3_CLK>,
|
||||
<&cgu BASE_UART2_CLK>, <&cgu BASE_UART1_CLK>,
|
||||
<&cgu BASE_UART0_CLK>, <&cgu BASE_SSP1_CLK>,
|
||||
<&cgu BASE_SSP0_CLK>, <&cgu BASE_SDIO_CLK>;
|
||||
clock-names = "base_audio_clk", "base_uart3_clk",
|
||||
"base_uart2_clk", "base_uart1_clk",
|
||||
"base_uart0_clk", "base_ssp1_clk",
|
||||
"base_ssp0_clk", "base_sdio_clk";
|
||||
};
|
||||
|
||||
/* A user of CCU branch clocks */
|
||||
uart1: serial@40082000 {
|
||||
...
|
||||
clocks = <&ccu2 CLK_APB0_UART1>, <&ccu1 CLK_CPU_UART1>;
|
||||
...
|
||||
};
|
||||
};
|
||||
@@ -1,131 +0,0 @@
|
||||
* NXP LPC1850 Clock Generation Unit (CGU)
|
||||
|
||||
The CGU generates multiple independent clocks for the core and the
|
||||
peripheral blocks of the LPC18xx. Each independent clock is called
|
||||
a base clock and itself is one of the inputs to the two Clock
|
||||
Control Units (CCUs) which control the branch clocks to the
|
||||
individual peripherals.
|
||||
|
||||
The CGU selects the inputs to the clock generators from multiple
|
||||
clock sources, controls the clock generation, and routes the outputs
|
||||
of the clock generators through the clock source bus to the output
|
||||
stages. Each output stage provides an independent clock source and
|
||||
corresponds to one of the base clocks for the LPC18xx.
|
||||
|
||||
- Above text taken from NXP LPC1850 User Manual.
|
||||
|
||||
|
||||
This binding uses the common clock binding:
|
||||
Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
Required properties:
|
||||
- compatible:
|
||||
Should be "nxp,lpc1850-cgu"
|
||||
- reg:
|
||||
Shall define the base and range of the address space
|
||||
containing clock control registers
|
||||
- #clock-cells:
|
||||
Shall have value <1>. The permitted clock-specifier values
|
||||
are the base clock numbers defined below.
|
||||
- clocks:
|
||||
Shall contain a list of phandles for the external input
|
||||
sources to the CGU. The list shall be in the following
|
||||
order: xtal, 32khz, enet_rx_clk, enet_tx_clk, gp_clkin.
|
||||
- clock-indices:
|
||||
Shall be an ordered list of numbers defining the base clock
|
||||
number provided by the CGU.
|
||||
- clock-output-names:
|
||||
Shall be an ordered list of strings defining the names of
|
||||
the clocks provided by the CGU.
|
||||
|
||||
Which base clocks that are available on the CGU depends on the
|
||||
specific LPC part. Base clocks are numbered from 0 to 27.
|
||||
|
||||
Number: Name: Description:
|
||||
0 BASE_SAFE_CLK Base safe clock (always on) for WWDT
|
||||
1 BASE_USB0_CLK Base clock for USB0
|
||||
2 BASE_PERIPH_CLK Base clock for Cortex-M0SUB subsystem,
|
||||
SPI, and SGPIO
|
||||
3 BASE_USB1_CLK Base clock for USB1
|
||||
4 BASE_CPU_CLK System base clock for ARM Cortex-M core
|
||||
and APB peripheral blocks #0 and #2
|
||||
5 BASE_SPIFI_CLK Base clock for SPIFI
|
||||
6 BASE_SPI_CLK Base clock for SPI
|
||||
7 BASE_PHY_RX_CLK Base clock for Ethernet PHY Receive clock
|
||||
8 BASE_PHY_TX_CLK Base clock for Ethernet PHY Transmit clock
|
||||
9 BASE_APB1_CLK Base clock for APB peripheral block # 1
|
||||
10 BASE_APB3_CLK Base clock for APB peripheral block # 3
|
||||
11 BASE_LCD_CLK Base clock for LCD
|
||||
12 BASE_ADCHS_CLK Base clock for ADCHS
|
||||
13 BASE_SDIO_CLK Base clock for SD/MMC
|
||||
14 BASE_SSP0_CLK Base clock for SSP0
|
||||
15 BASE_SSP1_CLK Base clock for SSP1
|
||||
16 BASE_UART0_CLK Base clock for UART0
|
||||
17 BASE_UART1_CLK Base clock for UART1
|
||||
18 BASE_UART2_CLK Base clock for UART2
|
||||
19 BASE_UART3_CLK Base clock for UART3
|
||||
20 BASE_OUT_CLK Base clock for CLKOUT pin
|
||||
24-21 - Reserved
|
||||
25 BASE_AUDIO_CLK Base clock for audio system (I2S)
|
||||
26 BASE_CGU_OUT0_CLK Base clock for CGU_OUT0 clock output
|
||||
27 BASE_CGU_OUT1_CLK Base clock for CGU_OUT1 clock output
|
||||
|
||||
BASE_PERIPH_CLK and BASE_SPI_CLK is only available on LPC43xx.
|
||||
BASE_ADCHS_CLK is only available on LPC4370.
|
||||
|
||||
|
||||
Example board file:
|
||||
|
||||
/ {
|
||||
clocks {
|
||||
xtal: xtal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <12000000>;
|
||||
};
|
||||
|
||||
xtal32: xtal32 {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <32768>;
|
||||
};
|
||||
|
||||
enet_rx_clk: enet_rx_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "enet_rx_clk";
|
||||
};
|
||||
|
||||
enet_tx_clk: enet_tx_clk {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "enet_tx_clk";
|
||||
};
|
||||
|
||||
gp_clkin: gp_clkin {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <0>;
|
||||
clock-output-names = "gp_clkin";
|
||||
};
|
||||
};
|
||||
|
||||
soc {
|
||||
cgu: clock-controller@40050000 {
|
||||
compatible = "nxp,lpc1850-cgu";
|
||||
reg = <0x40050000 0x1000>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>, <&creg_clk 1>, <&enet_rx_clk>, <&enet_tx_clk>, <&gp_clkin>;
|
||||
};
|
||||
|
||||
/* A CGU and CCU clock consumer */
|
||||
lcdc: lcdc@40008000 {
|
||||
...
|
||||
clocks = <&cgu BASE_LCD_CLK>, <&ccu1 CLK_CPU_LCD>;
|
||||
clock-names = "clcdclk", "apb_pclk";
|
||||
...
|
||||
};
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user