mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Massive net driver const-ification.
This commit is contained in:
1 parent
c499ec24c3
commit
f71e130966
43 files changed
+118
-118
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+2
-2
@@ -841,7 +841,7 @@ enum xcvr_types {
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XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
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};
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static struct media_table {
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static const struct media_table {
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char *name;
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unsigned int media_bits:16, /* Bits to set in Wn4_Media register. */
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mask:8, /* The transceiver-present bit in Wn3_Config.*/
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@@ -1445,7 +1445,7 @@ static int __devinit vortex_probe1(struct device *gendev,
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}
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{
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static const char * ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
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static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
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unsigned int config;
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EL3WINDOW(3);
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vp->available_media = ioread16(ioaddr + Wn3_Options);
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@@ -1276,7 +1276,7 @@ static int cp_change_mtu(struct net_device *dev, int new_mtu)
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}
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#endif /* BROKEN */
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static char mii_2_8139_map[8] = {
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static const char mii_2_8139_map[8] = {
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BasicModeCtrl,
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BasicModeStatus,
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0,
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@@ -229,7 +229,7 @@ typedef enum {
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/* indexed by board_t, above */
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static struct {
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static const struct {
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const char *name;
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u32 hw_flags;
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} board_info[] __devinitdata = {
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@@ -1192,7 +1192,7 @@ static int __devinit read_eeprom (void __iomem *ioaddr, int location, int addr_l
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#define mdio_delay() RTL_R8(Config4)
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static char mii_2_8139_map[8] = {
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static const char mii_2_8139_map[8] = {
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BasicModeCtrl,
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BasicModeStatus,
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0,
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+5
-5
@@ -46,7 +46,7 @@ typedef enum {
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} board_t;
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/* indexed by board_t, above */
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static struct {
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static const struct {
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char *name;
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} board_info[] __devinitdata = {
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{ "Broadcom NetXtreme II BCM5706 1000Base-T" },
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@@ -3476,7 +3476,7 @@ bnx2_test_registers(struct bnx2 *bp)
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{
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int ret;
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int i;
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static struct {
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static const struct {
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u16 offset;
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u16 flags;
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u32 rw_mask;
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@@ -3891,7 +3891,7 @@ reg_test_err:
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static int
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bnx2_do_mem_test(struct bnx2 *bp, u32 start, u32 size)
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{
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static u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
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static const u32 test_pattern[] = { 0x00000000, 0xffffffff, 0x55555555,
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0xaaaaaaaa , 0xaa55aa55, 0x55aa55aa };
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int i;
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@@ -3916,7 +3916,7 @@ bnx2_test_memory(struct bnx2 *bp)
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{
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int ret = 0;
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int i;
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static struct {
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static const struct {
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u32 offset;
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u32 len;
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} mem_tbl[] = {
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@@ -5122,7 +5122,7 @@ static struct {
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#define STATS_OFFSET32(offset_name) (offsetof(struct statistics_block, offset_name) / 4)
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static unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
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static const unsigned long bnx2_stats_offset_arr[BNX2_NUM_STATS] = {
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STATS_OFFSET32(stat_IfHCInOctets_hi),
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STATS_OFFSET32(stat_IfHCInBadOctets_hi),
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STATS_OFFSET32(stat_IfHCOutOctets_hi),
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+42
-42
@@ -14,20 +14,20 @@
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* accompanying it.
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*/
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static int bnx2_COM_b06FwReleaseMajor = 0x1;
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static int bnx2_COM_b06FwReleaseMinor = 0x0;
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static int bnx2_COM_b06FwReleaseFix = 0x0;
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static u32 bnx2_COM_b06FwStartAddr = 0x080008b4;
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static u32 bnx2_COM_b06FwTextAddr = 0x08000000;
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static int bnx2_COM_b06FwTextLen = 0x57bc;
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static u32 bnx2_COM_b06FwDataAddr = 0x08005840;
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static int bnx2_COM_b06FwDataLen = 0x0;
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static u32 bnx2_COM_b06FwRodataAddr = 0x080057c0;
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static int bnx2_COM_b06FwRodataLen = 0x58;
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static u32 bnx2_COM_b06FwBssAddr = 0x08005860;
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static int bnx2_COM_b06FwBssLen = 0x88;
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static u32 bnx2_COM_b06FwSbssAddr = 0x08005840;
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static int bnx2_COM_b06FwSbssLen = 0x1c;
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static const int bnx2_COM_b06FwReleaseMajor = 0x1;
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static const int bnx2_COM_b06FwReleaseMinor = 0x0;
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static const int bnx2_COM_b06FwReleaseFix = 0x0;
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static const u32 bnx2_COM_b06FwStartAddr = 0x080008b4;
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static const u32 bnx2_COM_b06FwTextAddr = 0x08000000;
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static const int bnx2_COM_b06FwTextLen = 0x57bc;
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static const u32 bnx2_COM_b06FwDataAddr = 0x08005840;
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static const int bnx2_COM_b06FwDataLen = 0x0;
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static const u32 bnx2_COM_b06FwRodataAddr = 0x080057c0;
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static const int bnx2_COM_b06FwRodataLen = 0x58;
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static const u32 bnx2_COM_b06FwBssAddr = 0x08005860;
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static const int bnx2_COM_b06FwBssLen = 0x88;
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static const u32 bnx2_COM_b06FwSbssAddr = 0x08005840;
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static const int bnx2_COM_b06FwSbssLen = 0x1c;
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static u32 bnx2_COM_b06FwText[(0x57bc/4) + 1] = {
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0x0a00022d, 0x00000000, 0x00000000, 0x0000000d, 0x636f6d20, 0x322e352e,
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0x38000000, 0x02050802, 0x00000000, 0x00000003, 0x00000014, 0x00000032,
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@@ -2325,20 +2325,20 @@ static u32 bnx2_rv2p_proc2[] = {
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0x0000000c, 0x29520000, 0x00000018, 0x80000002, 0x0000000c, 0x29800000,
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0x00000018, 0x00570000 };
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static int bnx2_TPAT_b06FwReleaseMajor = 0x1;
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static int bnx2_TPAT_b06FwReleaseMinor = 0x0;
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static int bnx2_TPAT_b06FwReleaseFix = 0x0;
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static u32 bnx2_TPAT_b06FwStartAddr = 0x08000860;
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static u32 bnx2_TPAT_b06FwTextAddr = 0x08000800;
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static int bnx2_TPAT_b06FwTextLen = 0x122c;
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static u32 bnx2_TPAT_b06FwDataAddr = 0x08001a60;
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static int bnx2_TPAT_b06FwDataLen = 0x0;
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static u32 bnx2_TPAT_b06FwRodataAddr = 0x00000000;
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static int bnx2_TPAT_b06FwRodataLen = 0x0;
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static u32 bnx2_TPAT_b06FwBssAddr = 0x08001aa0;
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static int bnx2_TPAT_b06FwBssLen = 0x250;
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static u32 bnx2_TPAT_b06FwSbssAddr = 0x08001a60;
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static int bnx2_TPAT_b06FwSbssLen = 0x34;
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static const int bnx2_TPAT_b06FwReleaseMajor = 0x1;
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static const int bnx2_TPAT_b06FwReleaseMinor = 0x0;
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static const int bnx2_TPAT_b06FwReleaseFix = 0x0;
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static const u32 bnx2_TPAT_b06FwStartAddr = 0x08000860;
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static const u32 bnx2_TPAT_b06FwTextAddr = 0x08000800;
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static const int bnx2_TPAT_b06FwTextLen = 0x122c;
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static const u32 bnx2_TPAT_b06FwDataAddr = 0x08001a60;
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static const int bnx2_TPAT_b06FwDataLen = 0x0;
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static const u32 bnx2_TPAT_b06FwRodataAddr = 0x00000000;
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static const int bnx2_TPAT_b06FwRodataLen = 0x0;
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static const u32 bnx2_TPAT_b06FwBssAddr = 0x08001aa0;
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static const int bnx2_TPAT_b06FwBssLen = 0x250;
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static const u32 bnx2_TPAT_b06FwSbssAddr = 0x08001a60;
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static const int bnx2_TPAT_b06FwSbssLen = 0x34;
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static u32 bnx2_TPAT_b06FwText[(0x122c/4) + 1] = {
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0x0a000218, 0x00000000, 0x00000000, 0x0000000d, 0x74706174, 0x20322e35,
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0x2e313100, 0x02050b01, 0x00000000, 0x00000000, 0x00000000, 0x00000000,
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@@ -2540,20 +2540,20 @@ static u32 bnx2_TPAT_b06FwRodata[(0x0/4) + 1] = { 0x0 };
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static u32 bnx2_TPAT_b06FwBss[(0x250/4) + 1] = { 0x0 };
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static u32 bnx2_TPAT_b06FwSbss[(0x34/4) + 1] = { 0x0 };
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static int bnx2_TXP_b06FwReleaseMajor = 0x1;
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static int bnx2_TXP_b06FwReleaseMinor = 0x0;
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static int bnx2_TXP_b06FwReleaseFix = 0x0;
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static u32 bnx2_TXP_b06FwStartAddr = 0x080034b0;
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static u32 bnx2_TXP_b06FwTextAddr = 0x08000000;
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static int bnx2_TXP_b06FwTextLen = 0x5748;
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static u32 bnx2_TXP_b06FwDataAddr = 0x08005760;
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static int bnx2_TXP_b06FwDataLen = 0x0;
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static u32 bnx2_TXP_b06FwRodataAddr = 0x00000000;
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static int bnx2_TXP_b06FwRodataLen = 0x0;
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static u32 bnx2_TXP_b06FwBssAddr = 0x080057a0;
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static int bnx2_TXP_b06FwBssLen = 0x1c4;
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static u32 bnx2_TXP_b06FwSbssAddr = 0x08005760;
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static int bnx2_TXP_b06FwSbssLen = 0x38;
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static const int bnx2_TXP_b06FwReleaseMajor = 0x1;
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static const int bnx2_TXP_b06FwReleaseMinor = 0x0;
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static const int bnx2_TXP_b06FwReleaseFix = 0x0;
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static const u32 bnx2_TXP_b06FwStartAddr = 0x080034b0;
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static const u32 bnx2_TXP_b06FwTextAddr = 0x08000000;
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static const int bnx2_TXP_b06FwTextLen = 0x5748;
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static const u32 bnx2_TXP_b06FwDataAddr = 0x08005760;
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static const int bnx2_TXP_b06FwDataLen = 0x0;
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static const u32 bnx2_TXP_b06FwRodataAddr = 0x00000000;
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static const int bnx2_TXP_b06FwRodataLen = 0x0;
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static const u32 bnx2_TXP_b06FwBssAddr = 0x080057a0;
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static const int bnx2_TXP_b06FwBssLen = 0x1c4;
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static const u32 bnx2_TXP_b06FwSbssAddr = 0x08005760;
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static const int bnx2_TXP_b06FwSbssLen = 0x38;
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static u32 bnx2_TXP_b06FwText[(0x5748/4) + 1] = {
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0x0a000d2c, 0x00000000, 0x00000000, 0x0000000d, 0x74787020, 0x322e352e,
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0x38000000, 0x02050800, 0x0000000a, 0x000003e8, 0x0000ea60, 0x00000000,
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@@ -1261,7 +1261,7 @@ int bond_alb_xmit(struct sk_buff *skb, struct net_device *bond_dev)
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struct ethhdr *eth_data;
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struct alb_bond_info *bond_info = &(BOND_ALB_INFO(bond));
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struct slave *tx_slave = NULL;
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static u32 ip_bcast = 0xffffffff;
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static const u32 ip_bcast = 0xffffffff;
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int hash_size = 0;
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int do_tx_balance = 1;
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u32 hash_index = 0;
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@@ -131,7 +131,7 @@ MODULE_PARM_DESC(arp_ip_target, "arp targets in n.n.n.n form");
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/*----------------------------- Global variables ----------------------------*/
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static const char *version =
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static const char * const version =
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DRV_DESCRIPTION ": v" DRV_VERSION " (" DRV_RELDATE ")\n";
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LIST_HEAD(bond_dev_list);
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@@ -686,7 +686,7 @@ int t1_init_hw_modules(adapter_t *adapter)
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*/
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static void __devinit get_pci_mode(adapter_t *adapter, struct chelsio_pci_params *p)
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{
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static unsigned short speed_map[] = { 33, 66, 100, 133 };
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static const unsigned short speed_map[] = { 33, 66, 100, 133 };
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u32 pci_mode;
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pci_read_config_dword(adapter->pdev, A_PCICFG_MODE, &pci_mode);
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+1
-1
@@ -993,7 +993,7 @@ dgrs_download(struct net_device *dev0)
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int is;
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unsigned long i;
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static int iv2is[16] = {
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static const int iv2is[16] = {
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0, 0, 0, ES4H_IS_INT3,
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0, ES4H_IS_INT5, 0, ES4H_IS_INT7,
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0, 0, ES4H_IS_INT10, ES4H_IS_INT11,
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@@ -1,4 +1,4 @@
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static int dgrs_firmnum = 550;
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static const int dgrs_firmnum = 550;
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static char dgrs_firmver[] = "$Version$";
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static char dgrs_firmdate[] = "11/16/96 03:45:15";
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static unsigned char dgrs_code[] __initdata = {
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@@ -9963,4 +9963,4 @@ static unsigned char dgrs_code[] __initdata = {
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109,46,99,0,114,99,0,0,48,120,0,0,
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0,0,0,0,0,0,0,0,0,0,0,0
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} ;
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static int dgrs_ncode = 119520 ;
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static const int dgrs_ncode = 119520 ;
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+2
-2
@@ -90,8 +90,8 @@ module_param(tx_coalesce, int, 0); /* HW xmit count each TxDMAComplete */
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#define EnableInt() \
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writew(DEFAULT_INTR, ioaddr + IntEnable)
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static int max_intrloop = 50;
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static int multicast_filter_limit = 0x40;
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static const int max_intrloop = 50;
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static const int multicast_filter_limit = 0x40;
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static int rio_open (struct net_device *dev);
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static void rio_timer (unsigned long data);
|
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@@ -27,7 +27,7 @@
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rx_align support: enables rx DMA without causing unaligned accesses.
|
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*/
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static const char *version =
|
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static const char * const version =
|
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"eepro100.c:v1.09j-t 9/29/99 Donald Becker http://www.scyld.com/network/eepro100.html\n"
|
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"eepro100.c: $Revision: 1.36 $ 2000/11/17 Modified by Andrey V. Savochkin <saw@saw.sw.com.sg> and others\n";
|
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@@ -469,7 +469,7 @@ static const char i82558_config_cmd[CONFIG_DATA_SIZE] = {
|
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0x31, 0x05, };
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/* PHY media interface chips. */
|
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static const char *phys[] = {
|
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static const char * const phys[] = {
|
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"None", "i82553-A/B", "i82553-C", "i82503",
|
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"DP83840", "80c240", "80c24", "i82555",
|
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"unknown-8", "unknown-9", "DP83840A", "unknown-11",
|
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|
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@@ -225,7 +225,7 @@ struct epic_chip_info {
|
||||
|
||||
|
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/* indexed by chip_t */
|
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static struct epic_chip_info pci_id_tbl[] = {
|
||||
static const struct epic_chip_info pci_id_tbl[] = {
|
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{ "SMSC EPIC/100 83c170",
|
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EPIC_IOTYPE, EPIC_TOTAL_SIZE, TYPE2_INTR | NO_MII | MII_PWRDWN },
|
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{ "SMSC EPIC/100 83c170",
|
||||
@@ -291,7 +291,7 @@ enum CommandBits {
|
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RxDone | RxStarted | RxEarlyWarn | RxOverflow | RxFull)
|
||||
#define EpicNormalEvent (0x0000ffff & ~EpicNapiEvent)
|
||||
|
||||
static u16 media2miictl[16] = {
|
||||
static const u16 media2miictl[16] = {
|
||||
0, 0x0C00, 0x0C00, 0x2000, 0x0100, 0x2100, 0, 0,
|
||||
0, 0, 0, 0, 0, 0, 0, 0 };
|
||||
|
||||
|
||||
@@ -160,7 +160,7 @@ struct chip_info {
|
||||
int flags;
|
||||
};
|
||||
|
||||
static struct chip_info skel_netdrv_tbl[] = {
|
||||
static const struct chip_info skel_netdrv_tbl[] = {
|
||||
{"100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
|
||||
{"100/10M Ethernet PCI Adapter", 136, HAS_CHIP_XCVR},
|
||||
{"1000/100/10M Ethernet PCI Adapter", 136, HAS_MII_XCVR},
|
||||
|
||||
@@ -427,7 +427,7 @@ that case.
|
||||
static void hamachi_timer(unsigned long data);
|
||||
|
||||
enum capability_flags {CanHaveMII=1, };
|
||||
static struct chip_info {
|
||||
static const struct chip_info {
|
||||
u16 vendor_id, device_id, device_id_mask, pad;
|
||||
const char *name;
|
||||
void (*media_timer)(unsigned long data);
|
||||
|
||||
@@ -189,7 +189,7 @@ static int mtu;
|
||||
|
||||
/* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
|
||||
This chip uses a 512 element hash table based on the Ethernet CRC. */
|
||||
static int multicast_filter_limit = 100;
|
||||
static const int multicast_filter_limit = 100;
|
||||
|
||||
/* Set the copy breakpoint for the copy-only-tiny-frames scheme.
|
||||
Setting to > 1518 effectively disables this feature. */
|
||||
@@ -374,7 +374,7 @@ enum pcistuff {
|
||||
|
||||
|
||||
/* array of board data directly indexed by pci_tbl[x].driver_data */
|
||||
static struct {
|
||||
static const struct {
|
||||
const char *name;
|
||||
unsigned long flags;
|
||||
} natsemi_pci_info[] __devinitdata = {
|
||||
|
||||
@@ -117,7 +117,7 @@ enum ne2k_pci_chipsets {
|
||||
};
|
||||
|
||||
|
||||
static struct {
|
||||
static const struct {
|
||||
char *name;
|
||||
int flags;
|
||||
} pci_clone_list[] __devinitdata = {
|
||||
|
||||
@@ -651,7 +651,7 @@ static void FASTCALL(phy_intr(struct net_device *ndev));
|
||||
static void fastcall phy_intr(struct net_device *ndev)
|
||||
{
|
||||
struct ns83820 *dev = PRIV(ndev);
|
||||
static char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
|
||||
static const char *speeds[] = { "10", "100", "1000", "1000(?)", "1000F" };
|
||||
u32 cfg, new_cfg;
|
||||
u32 tbisr, tanar, tanlpar;
|
||||
int speed, fullduplex, newlinkstate;
|
||||
|
||||
@@ -341,7 +341,7 @@ static void tc574_detach(struct pcmcia_device *p_dev)
|
||||
#define CS_CHECK(fn, ret) \
|
||||
do { last_fn = (fn); if ((last_ret = (ret)) != 0) goto cs_failed; } while (0)
|
||||
|
||||
static char *ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
|
||||
static const char *ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
|
||||
|
||||
static void tc574_config(dev_link_t *link)
|
||||
{
|
||||
|
||||
@@ -115,7 +115,7 @@ struct el3_private {
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
static char *if_names[] = { "auto", "10baseT", "10base2", "AUI" };
|
||||
static const char *if_names[] = { "auto", "10baseT", "10base2", "AUI" };
|
||||
|
||||
/*====================================================================*/
|
||||
|
||||
|
||||
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