mirror of
https://github.com/linux-msm/laptops-kernel.git
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Merge tag 'char-misc-5.2-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc
Pull char/misc update part 2 from Greg KH:
"Here is the "real" big set of char/misc driver patches for 5.2-rc1
Loads of different driver subsystem stuff in here, all over the places:
- thunderbolt driver updates
- habanalabs driver updates
- nvmem driver updates
- extcon driver updates
- intel_th driver updates
- mei driver updates
- coresight driver updates
- soundwire driver cleanups and updates
- fastrpc driver updates
- other minor driver updates
- chardev minor fixups
Feels like this tree is getting to be a dumping ground of "small
driver subsystems" these days. Which is fine with me, if it makes
things easier for those subsystem maintainers.
All of these have been in linux-next for a while with no reported
issues"
* tag 'char-misc-5.2-rc1-part2' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (255 commits)
intel_th: msu: Add current window tracking
intel_th: msu: Add a sysfs attribute to trigger window switch
intel_th: msu: Correct the block wrap detection
intel_th: Add switch triggering support
intel_th: gth: Factor out trace start/stop
intel_th: msu: Factor out pipeline draining
intel_th: msu: Switch over to scatterlist
intel_th: msu: Replace open-coded list_{first,last,next}_entry variants
intel_th: Only report useful IRQs to subdevices
intel_th: msu: Start handling IRQs
intel_th: pci: Use MSI interrupt signalling
intel_th: Communicate IRQ via resource
intel_th: Add "rtit" source device
intel_th: Skip subdevices if their MMIO is missing
intel_th: Rework resource passing between glue layers and core
intel_th: SPDX-ify the documentation
intel_th: msu: Fix single mode with IOMMU
coresight: funnel: Support static funnel
dt-bindings: arm: coresight: Unify funnel DT binding
coresight: replicator: Add new device id for static replicator
...
This commit is contained in:
Linus Torvalds
@@ -6,6 +6,8 @@ Description:
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This file allows user to read/write the raw NVMEM contents.
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Permissions for write to this file depends on the nvmem
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provider configuration.
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Note: This file is only present if CONFIG_NVMEM_SYSFS
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is enabled
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ex:
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hexdump /sys/bus/nvmem/devices/qfprom0/nvmem
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@@ -30,4 +30,12 @@ Description: (RW) Configure MSC buffer size for "single" or "multi" modes.
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there are no active users and tracing is not enabled) and then
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allocates a new one.
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What: /sys/bus/intel_th/devices/<intel_th_id>-msc<msc-id>/win_switch
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Date: May 2019
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KernelVersion: 5.2
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Contact: Alexander Shishkin <alexander.shishkin@linux.intel.com>
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Description: (RW) Trigger window switch for the MSC's buffer, in
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multi-window mode. In "multi" mode, accepts writes of "1", thereby
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triggering a window switch for the buffer. Returns an error in any
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other operating mode or attempts to write something other than "1".
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@@ -65,3 +65,18 @@ Description: Display the ME firmware version.
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<platform>:<major>.<minor>.<milestone>.<build_no>.
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There can be up to three such blocks for different
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FW components.
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What: /sys/class/mei/meiN/dev_state
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Date: Mar 2019
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KernelVersion: 5.1
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Contact: Tomas Winkler <tomas.winkler@intel.com>
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Description: Display the ME device state.
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The device state can have following values:
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INITIALIZING
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INIT_CLIENTS
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ENABLED
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RESETTING
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DISABLED
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POWER_DOWN
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POWER_UP
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|
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@@ -8,7 +8,8 @@ through the intermediate links connecting the source to the currently selected
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sink. Each CoreSight component device should use these properties to describe
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its hardware characteristcs.
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* Required properties for all components *except* non-configurable replicators:
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* Required properties for all components *except* non-configurable replicators
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and non-configurable funnels:
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|
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* compatible: These have to be supplemented with "arm,primecell" as
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drivers are using the AMBA bus interface. Possible values include:
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@@ -24,8 +25,10 @@ its hardware characteristcs.
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discovered at boot time when the device is probed.
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"arm,coresight-tmc", "arm,primecell";
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- Trace Funnel:
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"arm,coresight-funnel", "arm,primecell";
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- Trace Programmable Funnel:
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"arm,coresight-dynamic-funnel", "arm,primecell";
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"arm,coresight-funnel", "arm,primecell"; (OBSOLETE. For
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backward compatibility and will be removed)
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|
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- Embedded Trace Macrocell (version 3.x) and
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Program Flow Trace Macrocell:
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@@ -65,11 +68,17 @@ its hardware characteristcs.
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"stm-stimulus-base", each corresponding to the areas defined in "reg".
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|
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* Required properties for devices that don't show up on the AMBA bus, such as
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non-configurable replicators:
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non-configurable replicators and non-configurable funnels:
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* compatible: Currently supported value is (note the absence of the
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AMBA markee):
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- "arm,coresight-replicator"
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- Coresight Non-configurable Replicator:
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"arm,coresight-static-replicator";
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"arm,coresight-replicator"; (OBSOLETE. For backward
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compatibility and will be removed)
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|
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- Coresight Non-configurable Funnel:
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"arm,coresight-static-funnel";
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* port or ports: see "Graph bindings for Coresight" below.
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@@ -169,7 +178,7 @@ Example:
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/* non-configurable replicators don't show up on the
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* AMBA bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-replicator";
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compatible = "arm,coresight-static-replicator";
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|
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out-ports {
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#address-cells = <1>;
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@@ -200,8 +209,45 @@ Example:
|
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};
|
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};
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funnel {
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/*
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* non-configurable funnel don't show up on the AMBA
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* bus. As such no need to add "arm,primecell".
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*/
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compatible = "arm,coresight-static-funnel";
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clocks = <&crg_ctrl HI3660_PCLK>;
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clock-names = "apb_pclk";
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|
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out-ports {
|
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port {
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combo_funnel_out: endpoint {
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remote-endpoint = <&top_funnel_in>;
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};
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};
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};
|
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in-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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combo_funnel_in0: endpoint {
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remote-endpoint = <&cluster0_etf_out>;
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};
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};
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port@1 {
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reg = <1>;
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combo_funnel_in1: endpoint {
|
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remote-endpoint = <&cluster1_etf_out>;
|
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};
|
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};
|
||||
};
|
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};
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|
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funnel@20040000 {
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compatible = "arm,coresight-funnel", "arm,primecell";
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compatible = "arm,coresight-dynamic-funnel", "arm,primecell";
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reg = <0 0x20040000 0 0x1000>;
|
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|
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clocks = <&oscclk6a>;
|
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|
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@@ -9,6 +9,7 @@ Required properties:
|
||||
|
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- compatible : Must be one of
|
||||
|
||||
"u-blox,neo-6m"
|
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"u-blox,neo-8"
|
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"u-blox,neo-m8"
|
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|
||||
|
||||
@@ -0,0 +1,47 @@
|
||||
======================================================================
|
||||
Device tree bindings for Aspeed AST2400/AST2500 PCI-to-AHB Bridge Control Driver
|
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======================================================================
|
||||
|
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The bridge is available on platforms with the VGA enabled on the Aspeed device.
|
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In this case, the host has access to a 64KiB window into all of the BMC's
|
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memory. The BMC can disable this bridge. If the bridge is enabled, the host
|
||||
has read access to all the regions of memory, however the host only has read
|
||||
and write access depending on a register controlled by the BMC.
|
||||
|
||||
Required properties:
|
||||
===================
|
||||
|
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- compatible: must be one of:
|
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- "aspeed,ast2400-p2a-ctrl"
|
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- "aspeed,ast2500-p2a-ctrl"
|
||||
|
||||
Optional properties:
|
||||
===================
|
||||
|
||||
- memory-region: A phandle to a reserved_memory region to be used for the PCI
|
||||
to AHB mapping
|
||||
|
||||
The p2a-control node should be the child of a syscon node with the required
|
||||
property:
|
||||
|
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- compatible : Should be one of the following:
|
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"aspeed,ast2400-scu", "syscon", "simple-mfd"
|
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"aspeed,g4-scu", "syscon", "simple-mfd"
|
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"aspeed,ast2500-scu", "syscon", "simple-mfd"
|
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"aspeed,g5-scu", "syscon", "simple-mfd"
|
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|
||||
Example
|
||||
===================
|
||||
|
||||
g4 Example
|
||||
----------
|
||||
|
||||
syscon: scu@1e6e2000 {
|
||||
compatible = "aspeed,ast2400-scu", "syscon", "simple-mfd";
|
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reg = <0x1e6e2000 0x1a8>;
|
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|
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p2a: p2a-control {
|
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compatible = "aspeed,ast2400-p2a-ctrl";
|
||||
memory-region = <&reserved_memory>;
|
||||
};
|
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};
|
||||
@@ -8,11 +8,12 @@ Required properties:
|
||||
"allwinner,sun8i-h3-sid"
|
||||
"allwinner,sun50i-a64-sid"
|
||||
"allwinner,sun50i-h5-sid"
|
||||
"allwinner,sun50i-h6-sid"
|
||||
|
||||
- reg: Should contain registers location and length
|
||||
|
||||
= Data cells =
|
||||
Are child nodes of qfprom, bindings of which as described in
|
||||
Are child nodes of sunxi-sid, bindings of which as described in
|
||||
bindings/nvmem/nvmem.txt
|
||||
|
||||
Example for sun4i:
|
||||
|
||||
@@ -1,7 +1,8 @@
|
||||
Freescale i.MX6 On-Chip OTP Controller (OCOTP) device tree bindings
|
||||
|
||||
This binding represents the on-chip eFuse OTP controller found on
|
||||
i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ and i.MX6SLL SoCs.
|
||||
i.MX6Q/D, i.MX6DL/S, i.MX6SL, i.MX6SX, i.MX6UL, i.MX6ULL/ULZ, i.MX6SLL,
|
||||
i.MX7D/S, i.MX7ULP and i.MX8MQ SoCs.
|
||||
|
||||
Required properties:
|
||||
- compatible: should be one of
|
||||
@@ -13,6 +14,7 @@ Required properties:
|
||||
"fsl,imx7d-ocotp" (i.MX7D/S),
|
||||
"fsl,imx6sll-ocotp" (i.MX6SLL),
|
||||
"fsl,imx7ulp-ocotp" (i.MX7ULP),
|
||||
"fsl,imx8mq-ocotp" (i.MX8MQ),
|
||||
followed by "syscon".
|
||||
- #address-cells : Should be 1
|
||||
- #size-cells : Should be 1
|
||||
|
||||
@@ -0,0 +1,31 @@
|
||||
STMicroelectronics STM32 Factory-programmed data device tree bindings
|
||||
|
||||
This represents STM32 Factory-programmed read only non-volatile area: locked
|
||||
flash, OTP, read-only HW regs... This contains various information such as:
|
||||
analog calibration data for temperature sensor (e.g. TS_CAL1, TS_CAL2),
|
||||
internal vref (VREFIN_CAL), unique device ID...
|
||||
|
||||
Required properties:
|
||||
- compatible: Should be one of:
|
||||
"st,stm32f4-otp"
|
||||
"st,stm32mp15-bsec"
|
||||
- reg: Offset and length of factory-programmed area.
|
||||
- #address-cells: Should be '<1>'.
|
||||
- #size-cells: Should be '<1>'.
|
||||
|
||||
Optional Data cells:
|
||||
- Must be child nodes as described in nvmem.txt.
|
||||
|
||||
Example on stm32f4:
|
||||
romem: nvmem@1fff7800 {
|
||||
compatible = "st,stm32f4-otp";
|
||||
reg = <0x1fff7800 0x400>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
/* Data cells: ts_cal1 at 0x1fff7a2c */
|
||||
ts_cal1: calib@22c {
|
||||
reg = <0x22c 0x2>;
|
||||
};
|
||||
...
|
||||
};
|
||||
@@ -1,3 +1,5 @@
|
||||
.. SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
=======================
|
||||
Intel(R) Trace Hub (TH)
|
||||
=======================
|
||||
|
||||
@@ -8068,6 +8068,7 @@ F: drivers/gpio/gpio-intel-mid.c
|
||||
|
||||
INTERCONNECT API
|
||||
M: Georgi Djakov <georgi.djakov@linaro.org>
|
||||
L: linux-pm@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/interconnect/
|
||||
F: Documentation/devicetree/bindings/interconnect/
|
||||
|
||||
@@ -3121,6 +3121,7 @@ static void binder_transaction(struct binder_proc *proc,
|
||||
|
||||
if (target_node && target_node->txn_security_ctx) {
|
||||
u32 secid;
|
||||
size_t added_size;
|
||||
|
||||
security_task_getsecid(proc->tsk, &secid);
|
||||
ret = security_secid_to_secctx(secid, &secctx, &secctx_sz);
|
||||
@@ -3130,7 +3131,15 @@ static void binder_transaction(struct binder_proc *proc,
|
||||
return_error_line = __LINE__;
|
||||
goto err_get_secctx_failed;
|
||||
}
|
||||
extra_buffers_size += ALIGN(secctx_sz, sizeof(u64));
|
||||
added_size = ALIGN(secctx_sz, sizeof(u64));
|
||||
extra_buffers_size += added_size;
|
||||
if (extra_buffers_size < added_size) {
|
||||
/* integer overflow of extra_buffers_size */
|
||||
return_error = BR_FAILED_REPLY;
|
||||
return_error_param = EINVAL;
|
||||
return_error_line = __LINE__;
|
||||
goto err_bad_extra_size;
|
||||
}
|
||||
}
|
||||
|
||||
trace_binder_transaction(reply, t, target_node);
|
||||
@@ -3480,6 +3489,7 @@ err_copy_data_failed:
|
||||
t->buffer->transaction = NULL;
|
||||
binder_alloc_free_buf(&target_proc->alloc, t->buffer);
|
||||
err_binder_alloc_buf_failed:
|
||||
err_bad_extra_size:
|
||||
if (secctx)
|
||||
security_release_secctx(secctx, secctx_sz);
|
||||
err_get_secctx_failed:
|
||||
|
||||
@@ -973,6 +973,8 @@ static acpi_status hpet_resources(struct acpi_resource *res, void *data)
|
||||
if (ACPI_SUCCESS(status)) {
|
||||
hdp->hd_phys_address = addr.address.minimum;
|
||||
hdp->hd_address = ioremap(addr.address.minimum, addr.address.address_length);
|
||||
if (!hdp->hd_address)
|
||||
return AE_ERROR;
|
||||
|
||||
if (hpet_is_known(hdp)) {
|
||||
iounmap(hdp->hd_address);
|
||||
|
||||
@@ -30,7 +30,7 @@ config EXTCON_ARIZONA
|
||||
|
||||
config EXTCON_AXP288
|
||||
tristate "X-Power AXP288 EXTCON support"
|
||||
depends on MFD_AXP20X && USB_SUPPORT && X86
|
||||
depends on MFD_AXP20X && USB_SUPPORT && X86 && ACPI
|
||||
select USB_ROLE_SWITCH
|
||||
help
|
||||
Say Y here to enable support for USB peripheral detection
|
||||
@@ -60,6 +60,13 @@ config EXTCON_INTEL_CHT_WC
|
||||
Say Y here to enable extcon support for charger detection / control
|
||||
on the Intel Cherrytrail Whiskey Cove PMIC.
|
||||
|
||||
config EXTCON_INTEL_MRFLD
|
||||
tristate "Intel Merrifield Basin Cove PMIC extcon driver"
|
||||
depends on INTEL_SOC_PMIC_MRFLD
|
||||
help
|
||||
Say Y here to enable extcon support for charger detection / control
|
||||
on the Intel Merrifield Basin Cove PMIC.
|
||||
|
||||
config EXTCON_MAX14577
|
||||
tristate "Maxim MAX14577/77836 EXTCON Support"
|
||||
depends on MFD_MAX14577
|
||||
|
||||
@@ -11,6 +11,7 @@ obj-$(CONFIG_EXTCON_AXP288) += extcon-axp288.o
|
||||
obj-$(CONFIG_EXTCON_GPIO) += extcon-gpio.o
|
||||
obj-$(CONFIG_EXTCON_INTEL_INT3496) += extcon-intel-int3496.o
|
||||
obj-$(CONFIG_EXTCON_INTEL_CHT_WC) += extcon-intel-cht-wc.o
|
||||
obj-$(CONFIG_EXTCON_INTEL_MRFLD) += extcon-intel-mrfld.o
|
||||
obj-$(CONFIG_EXTCON_MAX14577) += extcon-max14577.o
|
||||
obj-$(CONFIG_EXTCON_MAX3355) += extcon-max3355.o
|
||||
obj-$(CONFIG_EXTCON_MAX77693) += extcon-max77693.o
|
||||
|
||||
@@ -205,7 +205,7 @@ EXPORT_SYMBOL(devm_extcon_register_notifier);
|
||||
|
||||
/**
|
||||
* devm_extcon_unregister_notifier()
|
||||
- Resource-managed extcon_unregister_notifier()
|
||||
* - Resource-managed extcon_unregister_notifier()
|
||||
* @dev: the device owning the extcon device being created
|
||||
* @edev: the extcon device
|
||||
* @id: the unique id among the extcon enumeration
|
||||
|
||||
@@ -1726,6 +1726,16 @@ static int arizona_extcon_remove(struct platform_device *pdev)
|
||||
struct arizona_extcon_info *info = platform_get_drvdata(pdev);
|
||||
struct arizona *arizona = info->arizona;
|
||||
int jack_irq_rise, jack_irq_fall;
|
||||
bool change;
|
||||
|
||||
regmap_update_bits_check(arizona->regmap, ARIZONA_MIC_DETECT_1,
|
||||
ARIZONA_MICD_ENA, 0,
|
||||
&change);
|
||||
|
||||
if (change) {
|
||||
regulator_disable(info->micvdd);
|
||||
pm_runtime_put(info->dev);
|
||||
}
|
||||
|
||||
gpiod_put(info->micd_pol_gpio);
|
||||
|
||||
|
||||
@@ -17,6 +17,8 @@
|
||||
#include <linux/regmap.h>
|
||||
#include <linux/slab.h>
|
||||
|
||||
#include "extcon-intel.h"
|
||||
|
||||
#define CHT_WC_PHYCTRL 0x5e07
|
||||
|
||||
#define CHT_WC_CHGRCTRL0 0x5e16
|
||||
@@ -29,7 +31,15 @@
|
||||
#define CHT_WC_CHGRCTRL0_DBPOFF BIT(6)
|
||||
#define CHT_WC_CHGRCTRL0_CHR_WDT_NOKICK BIT(7)
|
||||
|
||||
#define CHT_WC_CHGRCTRL1 0x5e17
|
||||
#define CHT_WC_CHGRCTRL1 0x5e17
|
||||
#define CHT_WC_CHGRCTRL1_FUSB_INLMT_100 BIT(0)
|
||||
#define CHT_WC_CHGRCTRL1_FUSB_INLMT_150 BIT(1)
|
||||
#define CHT_WC_CHGRCTRL1_FUSB_INLMT_500 BIT(2)
|
||||
#define CHT_WC_CHGRCTRL1_FUSB_INLMT_900 BIT(3)
|
||||
#define CHT_WC_CHGRCTRL1_FUSB_INLMT_1500 BIT(4)
|
||||
#define CHT_WC_CHGRCTRL1_FTEMP_EVENT BIT(5)
|
||||
#define CHT_WC_CHGRCTRL1_OTGMODE BIT(6)
|
||||
#define CHT_WC_CHGRCTRL1_DBPEN BIT(7)
|
||||
|
||||
#define CHT_WC_USBSRC 0x5e29
|
||||
#define CHT_WC_USBSRC_STS_MASK GENMASK(1, 0)
|
||||
@@ -48,6 +58,13 @@
|
||||
#define CHT_WC_USBSRC_TYPE_OTHER 8
|
||||
#define CHT_WC_USBSRC_TYPE_DCP_EXTPHY 9
|
||||
|
||||
#define CHT_WC_CHGDISCTRL 0x5e2f
|
||||
#define CHT_WC_CHGDISCTRL_OUT BIT(0)
|
||||
/* 0 - open drain, 1 - regular push-pull output */
|
||||
#define CHT_WC_CHGDISCTRL_DRV BIT(4)
|
||||
/* 0 - pin is controlled by SW, 1 - by HW */
|
||||
#define CHT_WC_CHGDISCTRL_FN BIT(6)
|
||||
|
||||
#define CHT_WC_PWRSRC_IRQ 0x6e03
|
||||
#define CHT_WC_PWRSRC_IRQ_MASK 0x6e0f
|
||||
#define CHT_WC_PWRSRC_STS 0x6e1e
|
||||
@@ -65,15 +82,6 @@
|
||||
#define CHT_WC_VBUS_GPIO_CTLO_DRV_OD BIT(4)
|
||||
#define CHT_WC_VBUS_GPIO_CTLO_DIR_OUT BIT(5)
|
||||
|
||||
enum cht_wc_usb_id {
|
||||
USB_ID_OTG,
|
||||
USB_ID_GND,
|
||||
USB_ID_FLOAT,
|
||||
USB_RID_A,
|
||||
USB_RID_B,
|
||||
USB_RID_C,
|
||||
};
|
||||
|
||||
enum cht_wc_mux_select {
|
||||
MUX_SEL_PMIC = 0,
|
||||
MUX_SEL_SOC,
|
||||
@@ -101,9 +109,9 @@ static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts)
|
||||
{
|
||||
switch ((pwrsrc_sts & CHT_WC_PWRSRC_USBID_MASK) >> CHT_WC_PWRSRC_USBID_SHIFT) {
|
||||
case CHT_WC_PWRSRC_RID_GND:
|
||||
return USB_ID_GND;
|
||||
return INTEL_USB_ID_GND;
|
||||
case CHT_WC_PWRSRC_RID_FLOAT:
|
||||
return USB_ID_FLOAT;
|
||||
return INTEL_USB_ID_FLOAT;
|
||||
case CHT_WC_PWRSRC_RID_ACA:
|
||||
default:
|
||||
/*
|
||||
@@ -111,7 +119,7 @@ static int cht_wc_extcon_get_id(struct cht_wc_extcon_data *ext, int pwrsrc_sts)
|
||||
* the USBID GPADC channel here and determine ACA role
|
||||
* based on that.
|
||||
*/
|
||||
return USB_ID_FLOAT;
|
||||
return INTEL_USB_ID_FLOAT;
|
||||
}
|
||||
}
|
||||
|
||||
@@ -198,6 +206,30 @@ static void cht_wc_extcon_set_5v_boost(struct cht_wc_extcon_data *ext,
|
||||
dev_err(ext->dev, "Error writing Vbus GPIO CTLO: %d\n", ret);
|
||||
}
|
||||
|
||||
static void cht_wc_extcon_set_otgmode(struct cht_wc_extcon_data *ext,
|
||||
bool enable)
|
||||
{
|
||||
unsigned int val = enable ? CHT_WC_CHGRCTRL1_OTGMODE : 0;
|
||||
int ret;
|
||||
|
||||
ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL1,
|
||||
CHT_WC_CHGRCTRL1_OTGMODE, val);
|
||||
if (ret)
|
||||
dev_err(ext->dev, "Error updating CHGRCTRL1 reg: %d\n", ret);
|
||||
}
|
||||
|
||||
static void cht_wc_extcon_enable_charging(struct cht_wc_extcon_data *ext,
|
||||
bool enable)
|
||||
{
|
||||
unsigned int val = enable ? 0 : CHT_WC_CHGDISCTRL_OUT;
|
||||
int ret;
|
||||
|
||||
ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
|
||||
CHT_WC_CHGDISCTRL_OUT, val);
|
||||
if (ret)
|
||||
dev_err(ext->dev, "Error updating CHGDISCTRL reg: %d\n", ret);
|
||||
}
|
||||
|
||||
/* Small helper to sync EXTCON_CHG_USB_SDP and EXTCON_USB state */
|
||||
static void cht_wc_extcon_set_state(struct cht_wc_extcon_data *ext,
|
||||
unsigned int cable, bool state)
|
||||
@@ -221,11 +253,17 @@ static void cht_wc_extcon_pwrsrc_event(struct cht_wc_extcon_data *ext)
|
||||
}
|
||||
|
||||
id = cht_wc_extcon_get_id(ext, pwrsrc_sts);
|
||||
if (id == USB_ID_GND) {
|
||||
if (id == INTEL_USB_ID_GND) {
|
||||
cht_wc_extcon_enable_charging(ext, false);
|
||||
cht_wc_extcon_set_otgmode(ext, true);
|
||||
|
||||
/* The 5v boost causes a false VBUS / SDP detect, skip */
|
||||
goto charger_det_done;
|
||||
}
|
||||
|
||||
cht_wc_extcon_set_otgmode(ext, false);
|
||||
cht_wc_extcon_enable_charging(ext, true);
|
||||
|
||||
/* Plugged into a host/charger or not connected? */
|
||||
if (!(pwrsrc_sts & CHT_WC_PWRSRC_VBUS)) {
|
||||
/* Route D+ and D- to PMIC for future charger detection */
|
||||
@@ -248,7 +286,7 @@ set_state:
|
||||
ext->previous_cable = cable;
|
||||
}
|
||||
|
||||
ext->usb_host = ((id == USB_ID_GND) || (id == USB_RID_A));
|
||||
ext->usb_host = ((id == INTEL_USB_ID_GND) || (id == INTEL_USB_RID_A));
|
||||
extcon_set_state_sync(ext->edev, EXTCON_USB_HOST, ext->usb_host);
|
||||
}
|
||||
|
||||
@@ -278,6 +316,14 @@ static int cht_wc_extcon_sw_control(struct cht_wc_extcon_data *ext, bool enable)
|
||||
{
|
||||
int ret, mask, val;
|
||||
|
||||
val = enable ? 0 : CHT_WC_CHGDISCTRL_FN;
|
||||
ret = regmap_update_bits(ext->regmap, CHT_WC_CHGDISCTRL,
|
||||
CHT_WC_CHGDISCTRL_FN, val);
|
||||
if (ret)
|
||||
dev_err(ext->dev,
|
||||
"Error setting sw control for CHGDIS pin: %d\n",
|
||||
ret);
|
||||
|
||||
mask = CHT_WC_CHGRCTRL0_SWCONTROL | CHT_WC_CHGRCTRL0_CCSM_OFF;
|
||||
val = enable ? mask : 0;
|
||||
ret = regmap_update_bits(ext->regmap, CHT_WC_CHGRCTRL0, mask, val);
|
||||
@@ -329,7 +375,10 @@ static int cht_wc_extcon_probe(struct platform_device *pdev)
|
||||
/* Enable sw control */
|
||||
ret = cht_wc_extcon_sw_control(ext, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
goto disable_sw_control;
|
||||
|
||||
/* Disable charging by external battery charger */
|
||||
cht_wc_extcon_enable_charging(ext, false);
|
||||
|
||||
/* Register extcon device */
|
||||
ret = devm_extcon_dev_register(ext->dev, ext->edev);
|
||||
|
||||
@@ -0,0 +1,284 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
/*
|
||||
* extcon driver for Basin Cove PMIC
|
||||
*
|
||||
* Copyright (c) 2019, Intel Corporation.
|
||||
* Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
|
||||
*/
|
||||
|
||||
#include <linux/extcon-provider.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/mfd/intel_soc_pmic.h>
|
||||
#include <linux/mfd/intel_soc_pmic_mrfld.h>
|
||||
#include <linux/mod_devicetable.h>
|
||||
#include <linux/module.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/regmap.h>
|
||||
|
||||
#include "extcon-intel.h"
|
||||
|
||||
#define BCOVE_USBIDCTRL 0x19
|
||||
#define BCOVE_USBIDCTRL_ID BIT(0)
|
||||
#define BCOVE_USBIDCTRL_ACA BIT(1)
|
||||
#define BCOVE_USBIDCTRL_ALL (BCOVE_USBIDCTRL_ID | BCOVE_USBIDCTRL_ACA)
|
||||
|
||||
#define BCOVE_USBIDSTS 0x1a
|
||||
#define BCOVE_USBIDSTS_GND BIT(0)
|
||||
#define BCOVE_USBIDSTS_RARBRC_MASK GENMASK(2, 1)
|
||||
#define BCOVE_USBIDSTS_RARBRC_SHIFT 1
|
||||
#define BCOVE_USBIDSTS_NO_ACA 0
|
||||
#define BCOVE_USBIDSTS_R_ID_A 1
|
||||
#define BCOVE_USBIDSTS_R_ID_B 2
|
||||
#define BCOVE_USBIDSTS_R_ID_C 3
|
||||
#define BCOVE_USBIDSTS_FLOAT BIT(3)
|
||||
#define BCOVE_USBIDSTS_SHORT BIT(4)
|
||||
|
||||
#define BCOVE_CHGRIRQ_ALL (BCOVE_CHGRIRQ_VBUSDET | BCOVE_CHGRIRQ_DCDET | \
|
||||
BCOVE_CHGRIRQ_BATTDET | BCOVE_CHGRIRQ_USBIDDET)
|
||||
|
||||
#define BCOVE_CHGRCTRL0 0x4b
|
||||
#define BCOVE_CHGRCTRL0_CHGRRESET BIT(0)
|
||||
#define BCOVE_CHGRCTRL0_EMRGCHREN BIT(1)
|
||||
#define BCOVE_CHGRCTRL0_EXTCHRDIS BIT(2)
|
||||
#define BCOVE_CHGRCTRL0_SWCONTROL BIT(3)
|
||||
#define BCOVE_CHGRCTRL0_TTLCK BIT(4)
|
||||
#define BCOVE_CHGRCTRL0_BIT_5 BIT(5)
|
||||
#define BCOVE_CHGRCTRL0_BIT_6 BIT(6)
|
||||
#define BCOVE_CHGRCTRL0_CHR_WDT_NOKICK BIT(7)
|
||||
|
||||
struct mrfld_extcon_data {
|
||||
struct device *dev;
|
||||
struct regmap *regmap;
|
||||
struct extcon_dev *edev;
|
||||
unsigned int status;
|
||||
unsigned int id;
|
||||
};
|
||||
|
||||
static const unsigned int mrfld_extcon_cable[] = {
|
||||
EXTCON_USB,
|
||||
EXTCON_USB_HOST,
|
||||
EXTCON_CHG_USB_SDP,
|
||||
EXTCON_CHG_USB_CDP,
|
||||
EXTCON_CHG_USB_DCP,
|
||||
EXTCON_CHG_USB_ACA,
|
||||
EXTCON_NONE,
|
||||
};
|
||||
|
||||
static int mrfld_extcon_clear(struct mrfld_extcon_data *data, unsigned int reg,
|
||||
unsigned int mask)
|
||||
{
|
||||
return regmap_update_bits(data->regmap, reg, mask, 0x00);
|
||||
}
|
||||
|
||||
static int mrfld_extcon_set(struct mrfld_extcon_data *data, unsigned int reg,
|
||||
unsigned int mask)
|
||||
{
|
||||
return regmap_update_bits(data->regmap, reg, mask, 0xff);
|
||||
}
|
||||
|
||||
static int mrfld_extcon_sw_control(struct mrfld_extcon_data *data, bool enable)
|
||||
{
|
||||
unsigned int mask = BCOVE_CHGRCTRL0_SWCONTROL;
|
||||
struct device *dev = data->dev;
|
||||
int ret;
|
||||
|
||||
if (enable)
|
||||
ret = mrfld_extcon_set(data, BCOVE_CHGRCTRL0, mask);
|
||||
else
|
||||
ret = mrfld_extcon_clear(data, BCOVE_CHGRCTRL0, mask);
|
||||
if (ret)
|
||||
dev_err(dev, "can't set SW control: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int mrfld_extcon_get_id(struct mrfld_extcon_data *data)
|
||||
{
|
||||
struct regmap *regmap = data->regmap;
|
||||
unsigned int id;
|
||||
bool ground;
|
||||
int ret;
|
||||
|
||||
ret = regmap_read(regmap, BCOVE_USBIDSTS, &id);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (id & BCOVE_USBIDSTS_FLOAT)
|
||||
return INTEL_USB_ID_FLOAT;
|
||||
|
||||
switch ((id & BCOVE_USBIDSTS_RARBRC_MASK) >> BCOVE_USBIDSTS_RARBRC_SHIFT) {
|
||||
case BCOVE_USBIDSTS_R_ID_A:
|
||||
return INTEL_USB_RID_A;
|
||||
case BCOVE_USBIDSTS_R_ID_B:
|
||||
return INTEL_USB_RID_B;
|
||||
case BCOVE_USBIDSTS_R_ID_C:
|
||||
return INTEL_USB_RID_C;
|
||||
}
|
||||
|
||||
/*
|
||||
* PMIC A0 reports USBIDSTS_GND = 1 for ID_GND,
|
||||
* but PMIC B0 reports USBIDSTS_GND = 0 for ID_GND.
|
||||
* Thus we must check this bit at last.
|
||||
*/
|
||||
ground = id & BCOVE_USBIDSTS_GND;
|
||||
switch ('A' + BCOVE_MAJOR(data->id)) {
|
||||
case 'A':
|
||||
return ground ? INTEL_USB_ID_GND : INTEL_USB_ID_FLOAT;
|
||||
case 'B':
|
||||
return ground ? INTEL_USB_ID_FLOAT : INTEL_USB_ID_GND;
|
||||
}
|
||||
|
||||
/* Unknown or unsupported type */
|
||||
return INTEL_USB_ID_FLOAT;
|
||||
}
|
||||
|
||||
static int mrfld_extcon_role_detect(struct mrfld_extcon_data *data)
|
||||
{
|
||||
unsigned int id;
|
||||
bool usb_host;
|
||||
int ret;
|
||||
|
||||
ret = mrfld_extcon_get_id(data);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
id = ret;
|
||||
|
||||
usb_host = (id == INTEL_USB_ID_GND) || (id == INTEL_USB_RID_A);
|
||||
extcon_set_state_sync(data->edev, EXTCON_USB_HOST, usb_host);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mrfld_extcon_cable_detect(struct mrfld_extcon_data *data)
|
||||
{
|
||||
struct regmap *regmap = data->regmap;
|
||||
unsigned int status, change;
|
||||
int ret;
|
||||
|
||||
/*
|
||||
* It seems SCU firmware clears the content of BCOVE_CHGRIRQ1
|
||||
* and makes it useless for OS. Instead we compare a previously
|
||||
* stored status to the current one, provided by BCOVE_SCHGRIRQ1.
|
||||
*/
|
||||
ret = regmap_read(regmap, BCOVE_SCHGRIRQ1, &status);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
change = status ^ data->status;
|
||||
if (!change)
|
||||
return -ENODATA;
|
||||
|
||||
if (change & BCOVE_CHGRIRQ_USBIDDET) {
|
||||
ret = mrfld_extcon_role_detect(data);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
data->status = status;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static irqreturn_t mrfld_extcon_interrupt(int irq, void *dev_id)
|
||||
{
|
||||
struct mrfld_extcon_data *data = dev_id;
|
||||
int ret;
|
||||
|
||||
ret = mrfld_extcon_cable_detect(data);
|
||||
|
||||
mrfld_extcon_clear(data, BCOVE_MIRQLVL1, BCOVE_LVL1_CHGR);
|
||||
|
||||
return ret ? IRQ_NONE: IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static int mrfld_extcon_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct device *dev = &pdev->dev;
|
||||
struct intel_soc_pmic *pmic = dev_get_drvdata(dev->parent);
|
||||
struct regmap *regmap = pmic->regmap;
|
||||
struct mrfld_extcon_data *data;
|
||||
unsigned int id;
|
||||
int irq, ret;
|
||||
|
||||
irq = platform_get_irq(pdev, 0);
|
||||
if (irq < 0)
|
||||
return irq;
|
||||
|
||||
data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
|
||||
data->dev = dev;
|
||||
data->regmap = regmap;
|
||||
|
||||
data->edev = devm_extcon_dev_allocate(dev, mrfld_extcon_cable);
|
||||
if (IS_ERR(data->edev))
|
||||
return -ENOMEM;
|
||||
|
||||
ret = devm_extcon_dev_register(dev, data->edev);
|
||||
if (ret < 0) {
|
||||
dev_err(dev, "can't register extcon device: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = devm_request_threaded_irq(dev, irq, NULL, mrfld_extcon_interrupt,
|
||||
IRQF_ONESHOT | IRQF_SHARED, pdev->name,
|
||||
data);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't register IRQ handler: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
ret = regmap_read(regmap, BCOVE_ID, &id);
|
||||
if (ret) {
|
||||
dev_err(dev, "can't read PMIC ID: %d\n", ret);
|
||||
return ret;
|
||||
}
|
||||
|
||||
data->id = id;
|
||||
|
||||
ret = mrfld_extcon_sw_control(data, true);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
/* Get initial state */
|
||||
mrfld_extcon_role_detect(data);
|
||||
|
||||
mrfld_extcon_clear(data, BCOVE_MIRQLVL1, BCOVE_LVL1_CHGR);
|
||||
mrfld_extcon_clear(data, BCOVE_MCHGRIRQ1, BCOVE_CHGRIRQ_ALL);
|
||||
|
||||
mrfld_extcon_set(data, BCOVE_USBIDCTRL, BCOVE_USBIDCTRL_ALL);
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int mrfld_extcon_remove(struct platform_device *pdev)
|
||||
{
|
||||
struct mrfld_extcon_data *data = platform_get_drvdata(pdev);
|
||||
|
||||
mrfld_extcon_sw_control(data, false);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static const struct platform_device_id mrfld_extcon_id_table[] = {
|
||||
{ .name = "mrfld_bcove_pwrsrc" },
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(platform, mrfld_extcon_id_table);
|
||||
|
||||
static struct platform_driver mrfld_extcon_driver = {
|
||||
.driver = {
|
||||
.name = "mrfld_bcove_pwrsrc",
|
||||
},
|
||||
.probe = mrfld_extcon_probe,
|
||||
.remove = mrfld_extcon_remove,
|
||||
.id_table = mrfld_extcon_id_table,
|
||||
};
|
||||
module_platform_driver(mrfld_extcon_driver);
|
||||
|
||||
MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
|
||||
MODULE_DESCRIPTION("extcon driver for Intel Merrifield Basin Cove PMIC");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@@ -0,0 +1,20 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0 */
|
||||
/*
|
||||
* Header file for Intel extcon hardware
|
||||
*
|
||||
* Copyright (C) 2019 Intel Corporation. All rights reserved.
|
||||
*/
|
||||
|
||||
#ifndef __EXTCON_INTEL_H__
|
||||
#define __EXTCON_INTEL_H__
|
||||
|
||||
enum extcon_intel_usb_id {
|
||||
INTEL_USB_ID_OTG,
|
||||
INTEL_USB_ID_GND,
|
||||
INTEL_USB_ID_FLOAT,
|
||||
INTEL_USB_RID_A,
|
||||
INTEL_USB_RID_B,
|
||||
INTEL_USB_RID_C,
|
||||
};
|
||||
|
||||
#endif /* __EXTCON_INTEL_H__ */
|
||||
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Reference in New Issue
Block a user