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Merge tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

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Pull MIPS updates from Thomas Bogendoerfer:

 - DT updates for ralink, mobileye and atheros/qualcomm

 - Clean up of mc146818 usage

 - Speed up delay calibration for CPS

 - Other cleanups and fixes

* tag 'mips_6.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (50 commits)
  MIPS: Don't use %pK through printk
  MIPS: Update Joshua Kinard's e-mail address
  MIPS: mobileye: dts: eyeq5,eyeq6h: rename the emmc controller
  MIPS: mm: tlb-r4k: Uniquify TLB entries on init
  MIPS: SGI-IP27: Delete an unnecessary check before kfree() in hub_domain_free()
  mips/malta,loongson2ef: use generic mc146818_get_time function
  mips: remove redundant macro mc146818_decode_year
  mips/mach-rm: remove custom mc146818rtc.h file
  mips: remove unused function mc146818_set_rtc_mmss
  MIPS: CPS: Optimise delay CPU calibration for SMP
  MIPS: CPS: Improve mips_cps_first_online_in_cluster()
  MIPS: disable MMID when not supported by the hardware
  MIPS: eyeq5_defconfig: add I2C subsystem, driver and temp sensor driver
  MIPS: eyeq5_defconfig: add GPIO subsystem & driver
  MIPS: mobileye: eyeq5: add two GPIO bank nodes
  MIPS: mobileye: eyeq5: add evaluation board I2C temp sensor
  MIPS: mobileye: eyeq5: add 5 I2C controller nodes
  MIPS: eyeq5_defconfig: Update for v6.16-rc1
  MIPS: vpe-mt: add missing prototypes for vpe_{alloc,start,stop,free}
  mips: boot: use 'targets' instead of extra-y in Makefile
  ...
This commit is contained in:
Linus Torvalds
2025-07-31 11:08:55 -07:00
parent 5ae8021583 3ebcbf079c
commit f1aa129d80
63 changed files with 569 additions and 247 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
+16 -12
View File
@@ -26,18 +26,22 @@ description: |
properties:
compatible:
items:
- enum:
- ralink,mt7620-sysc
- ralink,mt7628-sysc
- ralink,mt7688-sysc
- ralink,rt2880-sysc
- ralink,rt3050-sysc
- ralink,rt3052-sysc
- ralink,rt3352-sysc
- ralink,rt3883-sysc
- ralink,rt5350-sysc
- const: syscon
oneOf:
- items:
- enum:
- ralink,mt7620-sysc
- ralink,mt7688-sysc
- ralink,rt2880-sysc
- ralink,rt3050-sysc
- ralink,rt3052-sysc
- ralink,rt3352-sysc
- ralink,rt3883-sysc
- ralink,rt5350-sysc
- const: syscon
- items:
- const: ralink,mt7628-sysc
- const: ralink,mt7688-sysc
- const: syscon
reg:
maxItems: 1
arch/mips/Kconfig
+2
View File
@@ -562,6 +562,7 @@ config MIPS_MALTA
select MIPS_L1_CACHE_SHIFT_6
select MIPS_MSC
select PCI_GT64XXX_PCI0
select RTC_MC146818_LIB
select SMP_UP if SMP
select SWAP_IO_SPACE
select SYS_HAS_CPU_MIPS32_R1
@@ -1836,6 +1837,7 @@ config CPU_LOONGSON2EF
select CPU_SUPPORTS_64BIT_KERNEL
select CPU_SUPPORTS_HIGHMEM
select CPU_SUPPORTS_HUGEPAGES
select RTC_MC146818_LIB
config CPU_LOONGSON32
bool
arch/mips/boot/Makefile
+4 -4
View File
@@ -54,10 +54,10 @@ UIMAGE_ENTRYADDR = $(VMLINUX_ENTRY_ADDRESS)
# Compressed vmlinux images
#
extra-y += vmlinux.bin.bz2
extra-y += vmlinux.bin.gz
extra-y += vmlinux.bin.lzma
extra-y += vmlinux.bin.lzo
targets += vmlinux.bin.bz2
targets += vmlinux.bin.gz
targets += vmlinux.bin.lzma
targets += vmlinux.bin.lzo
$(obj)/vmlinux.bin.bz2: $(obj)/vmlinux.bin FORCE
$(call if_changed,bzip2)
arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
+8
View File
@@ -21,3 +21,11 @@
<0x8 0x02000000 0x0 0x7E000000>;
};
};
&i2c2 {
temperature-sensor@48 {
compatible = "ti,tmp112";
reg = <0x48>;
label = "U60";
};
};
arch/mips/boot/dts/mobileye/eyeq5.dtsi
+127
View File
@@ -110,6 +110,81 @@
ranges;
compatible = "simple-bus";
i2c0: i2c@300000 {
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
reg = <0 0x300000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>; /* Fast mode */
#address-cells = <1>;
#size-cells = <0>;
clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
clock-names = "i2cclk", "apb_pclk";
resets = <&olb 0 13>;
i2c-transfer-timeout-us = <10000>;
mobileye,olb = <&olb 0>;
};
i2c1: i2c@400000 {
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
reg = <0 0x400000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>; /* Fast mode */
#address-cells = <1>;
#size-cells = <0>;
clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
clock-names = "i2cclk", "apb_pclk";
resets = <&olb 0 14>;
i2c-transfer-timeout-us = <10000>;
mobileye,olb = <&olb 1>;
};
i2c2: i2c@500000 {
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
reg = <0 0x500000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>; /* Fast mode */
#address-cells = <1>;
#size-cells = <0>;
clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
clock-names = "i2cclk", "apb_pclk";
resets = <&olb 0 15>;
i2c-transfer-timeout-us = <10000>;
mobileye,olb = <&olb 2>;
};
i2c3: i2c@600000 {
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
reg = <0 0x600000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 4 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>; /* Fast mode */
#address-cells = <1>;
#size-cells = <0>;
clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
clock-names = "i2cclk", "apb_pclk";
resets = <&olb 0 16>;
i2c-transfer-timeout-us = <10000>;
mobileye,olb = <&olb 3>;
};
i2c4: i2c@700000 {
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
reg = <0 0x700000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 5 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <400000>; /* Fast mode */
#address-cells = <1>;
#size-cells = <0>;
clocks = <&olb 35>, <&olb EQ5C_PER_I2C>;
clock-names = "i2cclk", "apb_pclk";
resets = <&olb 0 17>;
i2c-transfer-timeout-us = <10000>;
mobileye,olb = <&olb 4>;
};
uart0: serial@800000 {
compatible = "arm,pl011", "arm,primecell";
reg = <0 0x800000 0x0 0x1000>;
@@ -178,6 +253,58 @@
clocks = <&olb EQ5C_CPU_CORE0>;
};
};
emmc: mmc@2200000 {
compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc";
reg = <0 0x2200000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&olb EQ5C_PER_EMMC>;
bus-width = <8>;
max-frequency = <200000000>;
mmc-ddr-1_8v;
sd-uhs-ddr50;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <32>;
cdns,phy-dll-delay-sdclk-hsmmc = <32>;
cdns,phy-dll-delay-strobe = <32>;
};
gpio0: gpio@1400000 {
compatible = "mobileye,eyeq5-gpio";
reg = <0x0 0x1400000 0x0 0x1000>;
gpio-bank = <0>;
ngpios = <29>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&olb 0 0 29>;
interrupt-controller;
#interrupt-cells = <2>;
resets = <&olb 0 26>;
};
gpio1: gpio@1500000 {
compatible = "mobileye,eyeq5-gpio";
reg = <0x0 0x1500000 0x0 0x1000>;
gpio-bank = <1>;
ngpios = <23>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 14 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&olb 0 29 23>;
interrupt-controller;
#interrupt-cells = <2>;
resets = <&olb 0 26>;
};
};
};
arch/mips/boot/dts/mobileye/eyeq6h.dtsi
+22
View File
@@ -109,6 +109,28 @@
clock-names = "ref";
};
emmc: mmc@d8010000 {
compatible = "mobileye,eyeq-sd4hc", "cdns,sd4hc";
reg = <0 0xd8010000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SHARED 91 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&olb_south EQ6HC_SOUTH_DIV_EMMC>;
bus-width = <8>;
max-frequency = <200000000>;
mmc-ddr-1_8v;
sd-uhs-ddr50;
mmc-hs200-1_8v;
mmc-hs400-1_8v;
mmc-hs400-enhanced-strobe;
cdns,phy-input-delay-legacy = <4>;
cdns,phy-input-delay-mmc-highspeed = <2>;
cdns,phy-input-delay-mmc-ddr = <3>;
cdns,phy-dll-delay-sdclk = <32>;
cdns,phy-dll-delay-sdclk-hsmmc = <32>;
cdns,phy-dll-delay-strobe = <32>;
};
olb_south: system-controller@d8013000 {
compatible = "mobileye,eyeq6h-south-olb", "syscon";
reg = <0x0 0xd8013000 0x0 0x1000>;
arch/mips/boot/dts/qca/ar9132.dtsi
+9
View File
@@ -156,6 +156,15 @@
#address-cells = <1>;
#size-cells = <0>;
};
wifi: wifi@180c0000 {
compatible = "qca,ar9130-wifi";
reg = <0x180c0000 0x230000>;
interrupts = <2>;
status = "disabled";
};
};
usb_phy: usb-phy {
arch/mips/boot/dts/qca/ar9132_tl_wr1043nd_v1.dts
+4
View File
@@ -108,3 +108,7 @@
};
};
};
&wifi {
status = "okay";
};
arch/mips/boot/dts/qca/ar9331.dtsi
+9
View File
@@ -285,6 +285,15 @@
status = "disabled";
};
wifi: wifi@18100000 {
compatible = "qca,ar9330-wifi";
reg = <0x18100000 0x20000>;
interrupts = <2>;
status = "disabled";
};
};
usb_phy: usb-phy {
arch/mips/boot/dts/qca/ar9331_dpt_module.dts
+4
View File
@@ -97,3 +97,7 @@
&phy_port4 {
status = "okay";
};
&wifi {
status = "okay";
};
arch/mips/boot/dts/qca/ar9331_dragino_ms14.dts
+4
View File
@@ -98,3 +98,7 @@
reg = <0>;
};
};
&wifi {
status = "okay";
};
arch/mips/boot/dts/qca/ar9331_omega.dts
+4
View File
@@ -74,3 +74,7 @@
reg = <0>;
};
};
&wifi {
status = "okay";
};
arch/mips/boot/dts/qca/ar9331_openembed_som9331_board.dts
+4
View File
@@ -106,3 +106,7 @@
&phy_port4 {
status = "okay";
};
&wifi {
status = "okay";
};
arch/mips/boot/dts/qca/ar9331_tl_mr3020.dts
+4
View File
@@ -114,3 +114,7 @@
reg = <0>;
};
};
&wifi {
status = "okay";
};
arch/mips/boot/dts/ralink/gardena_smart_gateway_mt7688.dts
+1 -1
View File
@@ -56,7 +56,7 @@
led-power-green {
label = "smartgw:power:green";
gpios = <&gpio 19 GPIO_ACTIVE_HIGH>;
default-state = "off";
linux,default-trigger = "timer";
};
led-power-red {
arch/mips/boot/dts/ralink/mt7628a.dtsi
+3 -8
View File
@@ -33,7 +33,7 @@
#size-cells = <1>;
sysc: syscon@0 {
compatible = "ralink,mt7628-sysc", "syscon";
compatible = "ralink,mt7628-sysc", "ralink,mt7688-sysc", "syscon";
reg = <0x0 0x60>;
#clock-cells = <1>;
#reset-cells = <1>;
@@ -134,13 +134,8 @@
watchdog: watchdog@100 {
compatible = "mediatek,mt7621-wdt";
reg = <0x100 0x30>;
resets = <&sysc 8>;
reset-names = "wdt";
interrupt-parent = <&intc>;
interrupts = <24>;
reg = <0x100 0x100>;
mediatek,sysctl = <&sysc>;
status = "disabled";
};
arch/mips/boot/dts/realtek/cameo-rtl9302c-2x-rtl8224-2xge.dts
+96
View File
@@ -71,3 +71,99 @@
};
};
};
&mdio0 {
/* External RTL8224 */
phy0: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy1: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy2: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy3: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
&mdio1 {
/* External RTL8224 */
phy4: ethernet-phy@0 {
reg = <0>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy5: ethernet-phy@1 {
reg = <1>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy6: ethernet-phy@2 {
reg = <2>;
compatible = "ethernet-phy-ieee802.3-c45";
};
phy7: ethernet-phy@3 {
reg = <3>;
compatible = "ethernet-phy-ieee802.3-c45";
};
};
&switch0 {
ethernet-ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
phy-handle = <&phy0>;
phy-mode = "usxgmii";
};
port@1 {
reg = <1>;
phy-handle = <&phy1>;
phy-mode = "usxgmii";
};
port@2 {
reg = <2>;
phy-handle = <&phy2>;
phy-mode = "usxgmii";
};
port@3 {
reg = <3>;
phy-handle = <&phy3>;
phy-mode = "usxgmii";
};
port@16 {
reg = <16>;
phy-handle = <&phy4>;
phy-mode = "usxgmii";
};
port@17 {
reg = <17>;
phy-handle = <&phy5>;
phy-mode = "usxgmii";
};
port@18 {
reg = <18>;
phy-handle = <&phy6>;
phy-mode = "usxgmii";
};
port@19 {
reg = <19>;
phy-handle = <&phy7>;
phy-mode = "usxgmii";
};
port@24{
reg = <24>;
phy-mode = "10gbase-r";
};
port@25{
reg = <25>;
phy-mode = "10gbase-r";
};
};
};
arch/mips/boot/dts/realtek/rtl930x.dtsi
+31
View File
@@ -48,6 +48,10 @@
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
interrupts = <23>, <24>;
interrupt-names = "switch", "nic";
reboot@c {
compatible = "syscon-reboot";
reg = <0x0c 0x4>;
@@ -138,6 +142,33 @@
clocks = <&lx_clk>;
};
watchdog0: watchdog@3260 {
compatible = "realtek,rtl9300-wdt";
reg = <0x3260 0xc>;
realtek,reset-mode = "soc";
clocks = <&lx_clk>;
timeout-sec = <30>;
interrupt-parent = <&intc>;
interrupt-names = "phase1", "phase2";
interrupts = <5>, <6>;
};
gpio0: gpio@3300 {
compatible = "realtek,rtl9300-gpio", "realtek,otto-gpio";
reg = <0x3300 0x1c>, <0x3338 0x8>;
gpio-controller;
#gpio-cells = <2>;
ngpios = <24>;
interrupt-controller;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupts = <13>;
};
snand: spi@1a400 {
compatible = "realtek,rtl9301-snand";
reg = <0x1a400 0x44>;
arch/mips/configs/eyeq5_defconfig
+9 -3
View File
@@ -19,20 +19,18 @@ CONFIG_SCHED_AUTOGROUP=y
CONFIG_BLK_DEV_INITRD=y
CONFIG_EXPERT=y
CONFIG_EYEQ=y
CONFIG_MACH_EYEQ5=y
CONFIG_FIT_IMAGE_FDT_EPM5=y
CONFIG_PAGE_SIZE_16KB=y
CONFIG_MIPS_CPS=y
CONFIG_CPU_HAS_MSA=y
CONFIG_NR_CPUS=16
CONFIG_MIPS_RAW_APPENDED_DTB=y
CONFIG_JUMP_LABEL=y
CONFIG_PAGE_SIZE_16KB=y
CONFIG_COMPAT_32BIT_TIME=y
CONFIG_MODULES=y
CONFIG_MODULE_UNLOAD=y
CONFIG_TRIM_UNUSED_KSYMS=y
# CONFIG_COMPAT_BRK is not set
CONFIG_SPARSEMEM_MANUAL=y
CONFIG_USERFAULTFD=y
CONFIG_NET=y
CONFIG_PACKET=y
@@ -64,8 +62,14 @@ CONFIG_CAN_M_CAN=y
CONFIG_SERIAL_AMBA_PL011=y
CONFIG_SERIAL_AMBA_PL011_CONSOLE=y
CONFIG_HW_RANDOM=y
CONFIG_I2C=y
CONFIG_I2C_CHARDEV=y
CONFIG_I2C_NOMADIK=y
# CONFIG_PTP_1588_CLOCK is not set
CONFIG_PINCTRL=y
CONFIG_GPIOLIB=y
CONFIG_GPIO_NOMADIK=y
CONFIG_SENSORS_LM75=y
CONFIG_MFD_SYSCON=y
CONFIG_HID_A4TECH=y
CONFIG_HID_BELKIN=y
@@ -79,6 +83,8 @@ CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_CADENCE=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_RESET_CONTROLLER=y
# CONFIG_NVMEM is not set
arch/mips/configs/eyeq6_defconfig
+2
View File
@@ -82,6 +82,8 @@ CONFIG_HID_MICROSOFT=y
CONFIG_HID_MONTEREY=y
CONFIG_MMC=y
CONFIG_MMC_SDHCI=y
CONFIG_MMC_SDHCI_PLTFM=y
CONFIG_MMC_SDHCI_CADENCE=y
# CONFIG_IOMMU_SUPPORT is not set
CONFIG_RESET_CONTROLLER=y
# CONFIG_NVMEM is not set

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