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Merge tag 'pinctrl-v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Browse Source 
Pull pin control updates from Linus Walleij:
 "An especially linear and sparse improvement and new drivers release.
  Nothing exciting. The biggest change in Bartosz changes to make
  gpiochip set/get calls return error codes (something we should have
  fixed ages ago but is now finally getting fixed.)

  Core changes:

   - Add the devres devm_pinctrl_register_mappings() call that can
     register some pin control machine mappings and have them go away
     with the associated device

  New drivers:

   - Support for the Mediatek MT6893 and MT8196 SoCs

   - Support for the Renesas RZ/V2N SoC

   - Support for the NXP Freescale i.MX943 SoC

  Improvements:

   - Per-SoC suspend/resume callbacks in the Samsung drivers

   - Set all pins as input (High-Z) at probe in the MCP23S08 driver

   - Switch most GPIO chips to use the setters/getters with a return
     value

   - EGPIO support in the Qualcomm QCM2290 driver

   - Fix up the number of available GPIO lines in Qualcomm QCS8300 and
     QCS615"

* tag 'pinctrl-v6.16-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (82 commits)
  pinctrl: freescale: Add support for imx943 pinctrl
  pinctrl: core: add devm_pinctrl_register_mappings()
  pinctrl: remove extern specifier for functions in machine.h
  pinctrl: mediatek: eint: Fix invalid pointer dereference for v1 platforms
  pinctrl: freescale: Enable driver if platform is enabled.
  pinctrl: freescale: Depend imx-scu driver on OF
  pinctrl: armada-37xx: propagate error from armada_37xx_pmx_set_by_name()
  pinctrl: armada-37xx: propagate error from armada_37xx_gpio_get_direction()
  pinctrl: armada-37xx: propagate error from armada_37xx_pmx_gpio_set_direction()
  pinctrl: armada-37xx: propagate error from armada_37xx_gpio_get()
  pinctrl: armada-37xx: propagate error from armada_37xx_gpio_direction_output()
  pinctrl: armada-37xx: set GPIO output value before setting direction
  pinctrl: armada-37xx: use correct OUTPUT_VAL register for GPIOs > 31
  pinctrl: meson: Drop unused aml_pctl_find_group_by_name()
  pinctrl: at91: Fix possible out-of-boundary access
  pinctrl: add stubs for OF-specific pinconf functions
  pinctrl: qcom: correct the ngpios entry for QCS8300
  pinctrl: qcom: correct the ngpios entry for QCS615
  dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs8300
  dt-bindings: pinctrl: qcom: correct gpio-ranges in examples for qcs615
  ...
This commit is contained in:
Linus Torvalds
2025-05-30 09:46:28 -07:00
parent 9f32a03e3e 08dcbe30be
commit eafd95ea74
79 changed files with 9749 additions and 853 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/pinctrl/amlogic,pinctrl-a4.yaml
+6 -1
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@@ -14,7 +14,12 @@ allOf:
properties:
compatible:
const: amlogic,pinctrl-a4
oneOf:
- const: amlogic,pinctrl-a4
- items:
- enum:
- amlogic,pinctrl-a5
- const: amlogic,pinctrl-a4
"#address-cells":
const: 2
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-iomuxc1.yaml
+99
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@@ -0,0 +1,99 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx7ulp-iomuxc1.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale i.MX7ULP IOMUX Controller
description: |
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
ports and IOMUXC DDR for DDR interface.
Note: This binding doc is only for the IOMUXC1 support in A7 Domain and it
only supports generic pin config.
Please refer to fsl,imx-pinctrl.txt in this directory for common binding
part and usage.
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,imx7ulp-iomuxc1
reg:
maxItems: 1
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
Each entry consists of 5 integers which represents the mux
and config setting for one pin. The first 4 integers
<mux_conf_reg input_reg mux_mode input_val> are specified
using a PIN_FUNC_ID macro, which can be found in
imx7ulp-pinfunc.h in the device tree source folder.
The last integer CONFIG is the pad setting value like
pull-up on this pin.
Please refer to i.MX7ULP Reference Manual for detailed
CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"mux_conf_reg" indicates the offset of mux register.
- description: |
"input_reg" indicates the offset of select input register.
- description: |
"mux_mode" indicates the mux value to be applied.
- description: |
"input_val" indicates the select input value to be applied.
- description: |
CONFIG bits definition:
PAD_CTL_OBE (1 << 17)
PAD_CTL_IBE (1 << 16)
PAD_CTL_LK (1 << 16)
PAD_CTL_DSE_HI (1 << 6)
PAD_CTL_DSE_STD (0 << 6)
PAD_CTL_ODE (1 << 5)
PAD_CTL_PUSH_PULL (0 << 5)
PAD_CTL_SRE_SLOW (1 << 2)
PAD_CTL_SRE_STD (0 << 2)
PAD_CTL_PE (1 << 0)
required:
- fsl,pins
additionalProperties: false
required:
- compatible
- reg
allOf:
- $ref: pinctrl.yaml#
unevaluatedProperties: false
examples:
- |
pinctrl@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
lpuart4grp {
fsl,pins = <
0x000c 0x0248 0x4 0x1 0x1
0x0008 0x024c 0x4 0x1 0x1
>;
};
};
Documentation/devicetree/bindings/pinctrl/fsl,imx7ulp-pinctrl.txt
-53
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@@ -1,53 +0,0 @@
* Freescale i.MX7ULP IOMUX Controller
i.MX 7ULP has three IOMUXC instances: IOMUXC0 for M4 ports, IOMUXC1 for A7
ports and IOMUXC DDR for DDR interface.
Note:
This binding doc is only for the IOMUXC1 support in A7 Domain and it only
supports generic pin config.
Please refer to fsl,imx-pinctrl.txt in this directory for common binding
part and usage.
Required properties:
- compatible: "fsl,imx7ulp-iomuxc1".
- fsl,pins: Each entry consists of 5 integers which represents the mux
and config setting for one pin. The first 4 integers
<mux_conf_reg input_reg mux_mode input_val> are specified
using a PIN_FUNC_ID macro, which can be found in
imx7ulp-pinfunc.h in the device tree source folder.
The last integer CONFIG is the pad setting value like
pull-up on this pin.
Please refer to i.MX7ULP Reference Manual for detailed
CONFIG settings.
CONFIG bits definition:
PAD_CTL_OBE (1 << 17)
PAD_CTL_IBE (1 << 16)
PAD_CTL_LK (1 << 16)
PAD_CTL_DSE_HI (1 << 6)
PAD_CTL_DSE_STD (0 << 6)
PAD_CTL_ODE (1 << 5)
PAD_CTL_PUSH_PULL (0 << 5)
PAD_CTL_SRE_SLOW (1 << 2)
PAD_CTL_SRE_STD (0 << 2)
PAD_CTL_PE (1 << 0)
Examples:
#include "imx7ulp-pinfunc.h"
/* Pin Controller Node */
iomuxc1: pinctrl@40ac0000 {
compatible = "fsl,imx7ulp-iomuxc1";
reg = <0x40ac0000 0x1000>;
/* Pin Configuration Node */
pinctrl_lpuart4: lpuart4grp {
fsl,pins = <
IMX7ULP_PAD_PTC3__LPUART4_RX 0x1
IMX7ULP_PAD_PTC2__LPUART4_TX 0x1
>;
};
};
Documentation/devicetree/bindings/pinctrl/fsl,vf610-iomuxc.yaml
+83
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@@ -0,0 +1,83 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,vf610-iomuxc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale Vybrid VF610 IOMUX Controller
description:
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
maintainers:
- Frank Li <Frank.Li@nxp.com>
properties:
compatible:
const: fsl,vf610-iomuxc
reg:
maxItems: 1
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
two integers array, represents a group of pins mux and config setting.
The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is a pin
working on a specific function, CONFIG is the pad setting value such
as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
datasheet for the valid pad config settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description:
PIN_FUN_ID refer to vf610-pinfunc.h in device tree source folder
for all available PIN_FUNC_ID for Vybrid VF610.
- description: |
CONFIG bits definition is
PAD_CTL_SPEED_LOW (1 << 12)
PAD_CTL_SPEED_MED (2 << 12)
PAD_CTL_SPEED_HIGH (3 << 12)
PAD_CTL_SRE_FAST (1 << 11)
PAD_CTL_SRE_SLOW (0 << 11)
PAD_CTL_ODE (1 << 10)
PAD_CTL_HYS (1 << 9)
PAD_CTL_DSE_DISABLE (0 << 6)
PAD_CTL_DSE_150ohm (1 << 6)
PAD_CTL_DSE_75ohm (2 << 6)
PAD_CTL_DSE_50ohm (3 << 6)
PAD_CTL_DSE_37ohm (4 << 6)
PAD_CTL_DSE_30ohm (5 << 6)
PAD_CTL_DSE_25ohm (6 << 6)
PAD_CTL_DSE_20ohm (7 << 6)
PAD_CTL_PUS_100K_DOWN (0 << 4)
PAD_CTL_PUS_47K_UP (1 << 4)
PAD_CTL_PUS_100K_UP (2 << 4)
PAD_CTL_PUS_22K_UP (3 << 4)
PAD_CTL_PKE (1 << 3)
PAD_CTL_PUE (1 << 2)
PAD_CTL_OBE_ENABLE (1 << 1)
PAD_CTL_IBE_ENABLE (1 << 0)
PAD_CTL_OBE_IBE_ENABLE (3 << 0)
required:
- fsl,pins
additionalProperties: false
required:
- compatible
- reg
allOf:
- $ref: pinctrl.yaml#
unevaluatedProperties: false
Documentation/devicetree/bindings/pinctrl/fsl,vf610-pinctrl.txt
-41
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@@ -1,41 +0,0 @@
Freescale Vybrid VF610 IOMUX Controller
Please refer to fsl,imx-pinctrl.txt in this directory for common binding part
and usage.
Required properties:
- compatible: "fsl,vf610-iomuxc"
- fsl,pins: two integers array, represents a group of pins mux and config
setting. The format is fsl,pins = <PIN_FUNC_ID CONFIG>, PIN_FUNC_ID is
a pin working on a specific function, CONFIG is the pad setting value
such as pull-up, speed, ode for this pin. Please refer to Vybrid VF610
datasheet for the valid pad config settings.
CONFIG bits definition:
PAD_CTL_SPEED_LOW (1 << 12)
PAD_CTL_SPEED_MED (2 << 12)
PAD_CTL_SPEED_HIGH (3 << 12)
PAD_CTL_SRE_FAST (1 << 11)
PAD_CTL_SRE_SLOW (0 << 11)
PAD_CTL_ODE (1 << 10)
PAD_CTL_HYS (1 << 9)
PAD_CTL_DSE_DISABLE (0 << 6)
PAD_CTL_DSE_150ohm (1 << 6)
PAD_CTL_DSE_75ohm (2 << 6)
PAD_CTL_DSE_50ohm (3 << 6)
PAD_CTL_DSE_37ohm (4 << 6)
PAD_CTL_DSE_30ohm (5 << 6)
PAD_CTL_DSE_25ohm (6 << 6)
PAD_CTL_DSE_20ohm (7 << 6)
PAD_CTL_PUS_100K_DOWN (0 << 4)
PAD_CTL_PUS_47K_UP (1 << 4)
PAD_CTL_PUS_100K_UP (2 << 4)
PAD_CTL_PUS_22K_UP (3 << 4)
PAD_CTL_PKE (1 << 3)
PAD_CTL_PUE (1 << 2)
PAD_CTL_OBE_ENABLE (1 << 1)
PAD_CTL_IBE_ENABLE (1 << 0)
PAD_CTL_OBE_IBE_ENABLE (3 << 0)
Please refer to vf610-pinfunc.h in device tree source folder
for all available PIN_FUNC_ID for Vybrid VF610.
Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
+31 -62
View File
@@ -136,75 +136,44 @@ examples:
#address-cells = <2>;
#size-cells = <2>;
syscfg_pctl_a: syscfg-pctl-a@10005000 {
compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
reg = <0 0x10005000 0 0x1000>;
};
syscfg_pctl_b: syscfg-pctl-b@1020c020 {
compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
reg = <0 0x1020C020 0 0x1000>;
};
pinctrl@1c20800 {
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
compatible = "mediatek,mt8135-pinctrl";
reg = <0 0x1000B000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
i2c0_pins_a: i2c0-pins {
pins1 {
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
i2c1_pins_a: i2c1-pins {
pins {
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
i2c2_pins_a: i2c2-pins {
pins1 {
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
bias-pull-down;
i2c0_pins_a: i2c0-pins {
pins1 {
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
bias-disable;
};
};
pins2 {
pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
bias-pull-up;
};
};
i2c3_pins_a: i2c3-pins {
pins1 {
pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
i2c1_pins_a: i2c1-pins {
pins {
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
};
pins2 {
pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
<MT8135_PIN_36_SDA3__FUNC_SDA3>;
output-low;
bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
};
i2c2_pins_a: i2c2-pins {
pins1 {
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
bias-pull-down;
};
pins3 {
pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
<MT8135_PIN_60_JTDI__FUNC_JTDI>;
drive-strength = <32>;
pins2 {
pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
bias-pull-up;
};
};
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml
-5
View File
@@ -245,9 +245,4 @@ examples:
};
};
};
mmc0 {
pinctrl-0 = <&mmc0_pins_default>;
pinctrl-names = "default";
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt6893-pinctrl.yaml
+193
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@@ -0,0 +1,193 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6893-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT6893 Pin Controller
maintainers:
- AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
description:
The MediaTek's MT6893 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt6893-pinctrl
reg:
items:
- description: pin controller base
- description: rm group IO
- description: bm group IO
- description: lm group IO
- description: lb group IO
- description: rt group IO
- description: lt group IO
- description: tm group IO
- description: External Interrupt (EINT) controller base
reg-names:
items:
- const: base
- const: rm
- const: bm
- const: lm
- const: lb
- const: rt
- const: lt
- const: tm
- const: eint
gpio-controller: true
'#gpio-cells':
description:
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
the amount of cells must be specified as 2. See the below mentioned gpio
binding representation for description of particular cells.
const: 2
gpio-ranges:
maxItems: 1
gpio-line-names: true
interrupts:
description: The interrupt outputs to sysirq
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
# PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'^pins':
type: object
allOf:
- $ref: /schemas/pinctrl/pincfg-node.yaml
- $ref: /schemas/pinctrl/pinmux-node.yaml
description:
A pinctrl node should contain at least one subnodes representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
properties:
pinmux:
description:
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux are defined as macros in
arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h for this SoC.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
drive-strength-microamp:
enum: [125, 250, 500, 1000]
bias-pull-down:
oneOf:
- type: boolean
- enum: [75000, 5000]
description: Pull down RSEL type resistance values (in ohms)
description:
For normal pull down type there is no need to specify a resistance
value, hence this can be specified as a boolean property.
For RSEL pull down type a resistance value (in ohms) can be added.
bias-pull-up:
oneOf:
- type: boolean
- enum: [10000, 5000, 4000, 3000]
description: Pull up RSEL type resistance values (in ohms)
description:
For normal pull up type there is no need to specify a resistance
value, hence this can be specified as a boolean property.
For RSEL pull up type a resistance value (in ohms) can be added.
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
additionalProperties: false
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt65xx.h>
#define PINMUX_GPIO0__FUNC_GPIO0 (MTK_PIN_NO(0) | 0)
#define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1)
#define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
pio: pinctrl@10005000 {
compatible = "mediatek,mt6893-pinctrl";
reg = <0x10005000 0x1000>,
<0x11c20000 0x0200>,
<0x11d10000 0x0200>,
<0x11e20000 0x0200>,
<0x11e70000 0x0200>,
<0x11ea0000 0x0200>,
<0x11f20000 0x0200>,
<0x11f30000 0x0200>,
<0x1100b000 0x1000>;
reg-names = "base", "rm", "bm", "lm", "lb", "rt",
"lt", "tm", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 220>;
interrupt-controller;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
gpio-pins {
pins {
pinmux = <PINMUX_GPIO0__FUNC_GPIO0>;
bias-pull-up = <4000>;
drive-strength = <6>;
};
};
i2c0-pins {
pins-bus {
pinmux = <PINMUX_GPIO99__FUNC_SCL0>,
<PINMUX_GPIO100__FUNC_SDA0>;
bias-pull-down = <75000>;
drive-strength-microamp = <1000>;
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml
+24 -24
View File
@@ -366,34 +366,34 @@ examples:
#size-cells = <2>;
pio: pinctrl@10211000 {
compatible = "mediatek,mt7622-pinctrl";
reg = <0 0x10211000 0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
compatible = "mediatek,mt7622-pinctrl";
reg = <0 0x10211000 0 0x1000>;
gpio-controller;
#gpio-cells = <2>;
pinctrl_eth_default: eth-pins {
mux-mdio {
groups = "mdc_mdio";
function = "eth";
drive-strength = <12>;
};
pinctrl_eth_default: eth-pins {
mux-mdio {
groups = "mdc_mdio";
function = "eth";
drive-strength = <12>;
};
mux-gmac2 {
groups = "rgmii_via_gmac2";
function = "eth";
drive-strength = <12>;
};
mux-gmac2 {
groups = "rgmii_via_gmac2";
function = "eth";
drive-strength = <12>;
};
mux-esw {
groups = "esw";
function = "eth";
drive-strength = <8>;
};
mux-esw {
groups = "esw";
function = "eth";
drive-strength = <8>;
};
conf-mdio {
pins = "MDC";
bias-pull-up;
conf-mdio {
pins = "MDC";
bias-pull-up;
};
};
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml
+34 -34
View File
@@ -195,43 +195,43 @@ examples:
#size-cells = <2>;
pio: pinctrl@10005000 {
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11e80000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11e90000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11c50000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg1", "iocfg2",
"iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 192>;
interrupt-controller;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
compatible = "mediatek,mt8183-pinctrl";
reg = <0 0x10005000 0 0x1000>,
<0 0x11f20000 0 0x1000>,
<0 0x11e80000 0 0x1000>,
<0 0x11e70000 0 0x1000>,
<0 0x11e90000 0 0x1000>,
<0 0x11d30000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11c50000 0 0x1000>,
<0 0x11f30000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "iocfg0", "iocfg1", "iocfg2",
"iocfg3", "iocfg4", "iocfg5",
"iocfg6", "iocfg7", "iocfg8",
"eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 192>;
interrupt-controller;
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0_pins_a: i2c0-pins {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
drive-strength-microamp = <1000>;
i2c0_pins_a: i2c0-pins {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
mediatek,pull-up-adv = <3>;
drive-strength-microamp = <1000>;
};
};
};
i2c1_pins_a: i2c1-pins {
pins {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-down-adv = <2>;
i2c1_pins_a: i2c1-pins {
pins {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
mediatek,pull-down-adv = <2>;
};
};
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt8192-pinctrl.yaml
+38 -38
View File
@@ -142,43 +142,43 @@ additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pio: pinctrl@10005000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0x10005000 0x1000>,
<0x11c20000 0x1000>,
<0x11d10000 0x1000>,
<0x11d30000 0x1000>,
<0x11d40000 0x1000>,
<0x11e20000 0x1000>,
<0x11e70000 0x1000>,
<0x11ea0000 0x1000>,
<0x11f20000 0x1000>,
<0x11f30000 0x1000>,
<0x1000b000 0x1000>;
reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
"iocfg_bl", "iocfg_br", "iocfg_lm",
"iocfg_lb", "iocfg_rt", "iocfg_lt",
"iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 220>;
interrupt-controller;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
#include <dt-bindings/pinctrl/mt8192-pinfunc.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
pio: pinctrl@10005000 {
compatible = "mediatek,mt8192-pinctrl";
reg = <0x10005000 0x1000>,
<0x11c20000 0x1000>,
<0x11d10000 0x1000>,
<0x11d30000 0x1000>,
<0x11d40000 0x1000>,
<0x11e20000 0x1000>,
<0x11e70000 0x1000>,
<0x11ea0000 0x1000>,
<0x11f20000 0x1000>,
<0x11f30000 0x1000>,
<0x1000b000 0x1000>;
reg-names = "iocfg0", "iocfg_rm", "iocfg_bm",
"iocfg_bl", "iocfg_br", "iocfg_lm",
"iocfg_lb", "iocfg_rt", "iocfg_lt",
"iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 220>;
interrupt-controller;
interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
spi1-default-pins {
pins-cs-mosi-clk {
pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO159__FUNC_SPI1_A_MO>,
<PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
bias-disable;
};
pins-miso {
pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
bias-pull-down;
};
};
spi1-default-pins {
pins-cs-mosi-clk {
pinmux = <PINMUX_GPIO157__FUNC_SPI1_A_CSB>,
<PINMUX_GPIO159__FUNC_SPI1_A_MO>,
<PINMUX_GPIO156__FUNC_SPI1_A_CLK>;
bias-disable;
};
pins-miso {
pinmux = <PINMUX_GPIO158__FUNC_SPI1_A_MI>;
bias-pull-down;
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt8196-pinctrl.yaml
+236
View File
@@ -0,0 +1,236 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8196-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: MediaTek MT8196 Pin Controller
maintainers:
- Lei Xue <lei.xue@mediatek.com>
- Cathy Xu <ot_cathy.xu@mediatek.com>
description:
The MediaTek's MT8196 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8196-pinctrl
reg:
items:
- description: gpio base
- description: rt group IO
- description: rm1 group IO
- description: rm2 group IO
- description: rb group IO
- description: bm1 group IO
- description: bm2 group IO
- description: bm3 group IO
- description: lt group IO
- description: lm1 group IO
- description: lm2 group IO
- description: lb1 group IO
- description: lb2 group IO
- description: tm1 group IO
- description: tm2 group IO
- description: tm3 group IO
- description: eint0 group IO
- description: eint1 group IO
- description: eint2 group IO
- description: eint3 group IO
- description: eint4 group IO
reg-names:
items:
- const: base
- const: rt
- const: rm1
- const: rm2
- const: rb
- const: bm1
- const: bm2
- const: bm3
- const: lt
- const: lm1
- const: lm2
- const: lb1
- const: lb2
- const: tm1
- const: tm2
- const: tm3
- const: eint0
- const: eint1
- const: eint2
- const: eint3
- const: eint4
interrupts:
description: The interrupt outputs to sysirq.
maxItems: 1
interrupt-controller: true
'#interrupt-cells':
const: 2
gpio-controller: true
'#gpio-cells':
description:
Number of cells in GPIO specifier, should be two. The first cell is the
pin number, the second cell is used to specify optional parameters which
are defined in <dt-bindings/gpio/gpio.h>.
const: 2
gpio-ranges:
maxItems: 1
gpio-line-names: true
# PIN CONFIGURATION NODES
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'^pins':
type: object
$ref: /schemas/pinctrl/pincfg-node.yaml
additionalProperties: false
description:
A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
properties:
pinmux:
description:
Integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in arch/arm64/boot/dts/mediatek/mt8196-pinfunc.h
directly, for this SoC.
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
bias-pull-down:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt8196 pull down PUPD/R0/R1 type define value.
- enum: [75000, 5000]
description: mt8196 pull down RSEL type si unit value(ohm).
description: |
For pull down type is normal, it doesn't need add R1R0 define
and resistance value.
For pull down type is PUPD/R0/R1 type, it can add R1R0 define to
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
"MTK_PUPD_SET_R1R0_11" define in mt8196.
For pull down type is PD/RSEL, it can add resistance value(ohm)
to set different resistance by identifying property
"mediatek,rsel-resistance-in-si-unit". It can support resistance
value(ohm) "75000" & "5000" in mt8196.
bias-pull-up:
oneOf:
- type: boolean
- enum: [100, 101, 102, 103]
description: mt8196 pull up PUPD/R0/R1 type define value.
- enum: [1000, 1500, 2000, 3000, 4000, 5000, 75000]
description: mt8196 pull up RSEL type si unit value(ohm).
description: |
For pull up type is normal, it don't need add R1R0 define
and resistance value.
For pull up type is PUPD/R0/R1 type, it can add R1R0 define to
set different resistance. It can support "MTK_PUPD_SET_R1R0_00" &
"MTK_PUPD_SET_R1R0_01" & "MTK_PUPD_SET_R1R0_10" &
"MTK_PUPD_SET_R1R0_11" define in mt8196.
For pull up type is PU/RSEL, it can add resistance value(ohm)
to set different resistance by identifying property
"mediatek,rsel-resistance-in-si-unit". It can support resistance
value(ohm) "1000" & "1500" & "2000" & "3000" & "4000" & "5000" &
"75000" in mt8196.
bias-disable: true
output-high: true
output-low: true
input-enable: true
input-disable: true
input-schmitt-enable: true
input-schmitt-disable: true
required:
- pinmux
required:
- compatible
- reg
- interrupts
- interrupt-controller
- '#interrupt-cells'
- gpio-controller
- '#gpio-cells'
- gpio-ranges
additionalProperties: false
examples:
- |
#include <dt-bindings/pinctrl/mt65xx.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#define PINMUX_GPIO99__FUNC_SCL0 (MTK_PIN_NO(99) | 1)
#define PINMUX_GPIO100__FUNC_SDA0 (MTK_PIN_NO(100) | 1)
pio: pinctrl@1002d000 {
compatible = "mediatek,mt8196-pinctrl";
reg = <0x1002d000 0x1000>,
<0x12000000 0x1000>,
<0x12020000 0x1000>,
<0x12040000 0x1000>,
<0x12060000 0x1000>,
<0x12820000 0x1000>,
<0x12840000 0x1000>,
<0x12860000 0x1000>,
<0x13000000 0x1000>,
<0x13020000 0x1000>,
<0x13040000 0x1000>,
<0x130f0000 0x1000>,
<0x13110000 0x1000>,
<0x13800000 0x1000>,
<0x13820000 0x1000>,
<0x13860000 0x1000>,
<0x12080000 0x1000>,
<0x12880000 0x1000>,
<0x13080000 0x1000>,
<0x13880000 0x1000>,
<0x1c54a000 0x1000>;
reg-names = "base", "rt", "rm1", "rm2", "rb" , "bm1",
"bm2", "bm3", "lt", "lm1", "lm2", "lb1",
"lb2", "tm1", "tm2", "tm3", "eint0", "eint1",
"eint2", "eint3", "eint4";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 271>;
interrupt-controller;
interrupts = <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH 0>;
#interrupt-cells = <2>;
i2c0-pins {
pins {
pinmux = <PINMUX_GPIO99__FUNC_SCL0>,
<PINMUX_GPIO100__FUNC_SDA0>;
bias-disable;
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,qcs615-tlmm.yaml
+1 -1
View File
@@ -110,7 +110,7 @@ examples:
<0x03c00000 0x300000>;
reg-names = "east", "west", "south";
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-ranges = <&tlmm 0 0 123>;
gpio-ranges = <&tlmm 0 0 124>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
Documentation/devicetree/bindings/pinctrl/qcom,qcs8300-tlmm.yaml
+1 -1
View File
@@ -106,7 +106,7 @@ examples:
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 133>;
gpio-ranges = <&tlmm 0 0 134>;
interrupt-controller;
#interrupt-cells = <2>;
Documentation/devicetree/bindings/pinctrl/spacemit,k1-pinctrl.yaml
+18
View File
@@ -17,6 +17,19 @@ properties:
items:
- description: pinctrl io memory base
clocks:
items:
- description: Functional Clock
- description: Bus Clock
clock-names:
items:
- const: func
- const: bus
resets:
maxItems: 1
patternProperties:
'-cfg$':
type: object
@@ -94,6 +107,8 @@ patternProperties:
required:
- compatible
- reg
- clocks
- clock-names
additionalProperties: false
@@ -108,6 +123,9 @@ examples:
pinctrl@d401e000 {
compatible = "spacemit,k1-pinctrl";
reg = <0x0 0xd401e000 0x0 0x400>;
clocks = <&syscon_apbc 42>,
<&syscon_apbc 94>;
clock-names = "func", "bus";
uart0_2_cfg: uart0-2-cfg {
uart0-2-pins {
drivers/pinctrl/Kconfig
+1 -3
View File
@@ -103,12 +103,10 @@ config PINCTRL_AS3722
config PINCTRL_AT91
bool "AT91 pinctrl driver"
depends on OF
depends on ARCH_AT91
depends on (OF && ARCH_AT91) || COMPILE_TEST
select PINMUX
select PINCONF
select GPIOLIB
select OF_GPIO
select GPIOLIB_IRQCHIP
help
Say Y here to enable the at91 pinctrl driver
drivers/pinctrl/actions/pinctrl-owl.c
+5 -3
View File
@@ -598,7 +598,7 @@ static int owl_gpio_get(struct gpio_chip *chip, unsigned int offset)
return !!(val & BIT(offset));
}
static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
static int owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
{
struct owl_pinctrl *pctrl = gpiochip_get_data(chip);
const struct owl_gpio_port *port;
@@ -607,13 +607,15 @@ static void owl_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
port = owl_gpio_get_port(pctrl, &offset);
if (WARN_ON(port == NULL))
return;
return -ENODEV;
gpio_base = pctrl->base + port->offset;
raw_spin_lock_irqsave(&pctrl->lock, flags);
owl_gpio_update_reg(gpio_base + port->dat, offset, value);
raw_spin_unlock_irqrestore(&pctrl->lock, flags);
return 0;
}
static int owl_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
@@ -960,7 +962,7 @@ int owl_pinctrl_probe(struct platform_device *pdev,
pctrl->chip.direction_input = owl_gpio_direction_input;
pctrl->chip.direction_output = owl_gpio_direction_output;
pctrl->chip.get = owl_gpio_get;
pctrl->chip.set = owl_gpio_set;
pctrl->chip.set_rv = owl_gpio_set;
pctrl->chip.request = owl_gpio_request;
pctrl->chip.free = owl_gpio_free;
drivers/pinctrl/bcm/pinctrl-bcm2835.c
+6 -3
View File
@@ -356,11 +356,14 @@ static int bcm2835_gpio_get_direction(struct gpio_chip *chip, unsigned int offse
return GPIO_LINE_DIRECTION_IN;
}
static void bcm2835_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
static int bcm2835_gpio_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct bcm2835_pinctrl *pc = gpiochip_get_data(chip);
bcm2835_gpio_set_bit(pc, value ? GPSET0 : GPCLR0, offset);
return 0;
}
static int bcm2835_gpio_direction_output(struct gpio_chip *chip,
@@ -394,7 +397,7 @@ static const struct gpio_chip bcm2835_gpio_chip = {
.direction_output = bcm2835_gpio_direction_output,
.get_direction = bcm2835_gpio_get_direction,
.get = bcm2835_gpio_get,
.set = bcm2835_gpio_set,
.set_rv = bcm2835_gpio_set,
.set_config = gpiochip_generic_config,
.base = -1,
.ngpio = BCM2835_NUM_GPIOS,
@@ -411,7 +414,7 @@ static const struct gpio_chip bcm2711_gpio_chip = {
.direction_output = bcm2835_gpio_direction_output,
.get_direction = bcm2835_gpio_get_direction,
.get = bcm2835_gpio_get,
.set = bcm2835_gpio_set,
.set_rv = bcm2835_gpio_set,
.set_config = gpiochip_generic_config,
.base = -1,
.ngpio = BCM2711_NUM_GPIOS,
drivers/pinctrl/bcm/pinctrl-iproc-gpio.c
+4 -2
View File
@@ -390,7 +390,7 @@ static int iproc_gpio_get_direction(struct gpio_chip *gc, unsigned int gpio)
return GPIO_LINE_DIRECTION_IN;
}
static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
static int iproc_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct iproc_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
@@ -400,6 +400,8 @@ static void iproc_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
return 0;
}
static int iproc_gpio_get(struct gpio_chip *gc, unsigned gpio)
@@ -863,7 +865,7 @@ static int iproc_gpio_probe(struct platform_device *pdev)
gc->direction_input = iproc_gpio_direction_input;
gc->direction_output = iproc_gpio_direction_output;
gc->get_direction = iproc_gpio_get_direction;
gc->set = iproc_gpio_set;
gc->set_rv = iproc_gpio_set;
gc->get = iproc_gpio_get;
chip->pinmux_is_supported = of_property_read_bool(dev->of_node,
drivers/pinctrl/bcm/pinctrl-nsp-gpio.c
+4 -2
View File
@@ -310,7 +310,7 @@ static int nsp_gpio_get_direction(struct gpio_chip *gc, unsigned gpio)
return !val;
}
static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
static int nsp_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
{
struct nsp_gpio *chip = gpiochip_get_data(gc);
unsigned long flags;
@@ -320,6 +320,8 @@ static void nsp_gpio_set(struct gpio_chip *gc, unsigned gpio, int val)
raw_spin_unlock_irqrestore(&chip->lock, flags);
dev_dbg(chip->dev, "gpio:%u set, value:%d\n", gpio, val);
return 0;
}
static int nsp_gpio_get(struct gpio_chip *gc, unsigned gpio)
@@ -654,7 +656,7 @@ static int nsp_gpio_probe(struct platform_device *pdev)
gc->direction_input = nsp_gpio_direction_input;
gc->direction_output = nsp_gpio_direction_output;
gc->get_direction = nsp_gpio_get_direction;
gc->set = nsp_gpio_set;
gc->set_rv = nsp_gpio_set;
gc->get = nsp_gpio_get;
/* optional GPIO interrupt support */

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