mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'net-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net
Pull networking fixes from Jakub Kicinski:
"Including fixes from Netfilter.
Steady stream of fixes. Last two weeks feel comparable to the two
weeks before the merge window. Lots of AI-aided bug discovery. A newer
big source is Sashiko/Gemini (Roman Gushchin's system), which points
out issues in existing code during patch review (maybe 25% of fixes
here likely originating from Sashiko). Nice thing is these are often
fixed by the respective maintainers, not drive-bys.
Current release - new code bugs:
- kconfig: MDIO_PIC64HPSC should depend on ARCH_MICROCHIP
Previous releases - regressions:
- add async ndo_set_rx_mode and switch drivers which we promised to
be called under the per-netdev mutex to it
- dsa: remove duplicate netdev_lock_ops() for conduit ethtool ops
- hv_sock: report EOF instead of -EIO for FIN
- vsock/virtio: fix MSG_PEEK calculation on bytes to copy
Previous releases - always broken:
- ipv6: fix possible UAF in icmpv6_rcv()
- icmp: validate reply type before using icmp_pointers
- af_unix: drop all SCM attributes for SOCKMAP
- netfilter: fix a number of bugs in the osf (OS fingerprinting)
- eth: intel: fix timestamp interrupt configuration for E825C
Misc:
- bunch of data-race annotations"
* tag 'net-7.1-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/netdev/net: (148 commits)
rxrpc: Fix error handling in rxgk_extract_token()
rxrpc: Fix re-decryption of RESPONSE packets
rxrpc: Fix rxrpc_input_call_event() to only unshare DATA packets
rxrpc: Fix missing validation of ticket length in non-XDR key preparsing
rxgk: Fix potential integer overflow in length check
rxrpc: Fix conn-level packet handling to unshare RESPONSE packets
rxrpc: Fix potential UAF after skb_unshare() failure
rxrpc: Fix rxkad crypto unalignment handling
rxrpc: Fix memory leaks in rxkad_verify_response()
net: rds: fix MR cleanup on copy error
m68k: mvme147: Make me the maintainer
net: txgbe: fix firmware version check
selftests/bpf: check epoll readiness during reuseport migration
tcp: call sk_data_ready() after listener migration
vhost_net: fix sleeping with preempt-disabled in vhost_net_busy_poll()
ipv6: Cap TLV scan in ip6_tnl_parse_tlv_enc_lim
tipc: fix double-free in tipc_buf_append()
llc: Return -EINPROGRESS from llc_ui_connect()
ipv4: icmp: validate reply type before using icmp_pointers
selftests/net: packetdrill: cover RFC 5961 5.2 challenge ACK on both edges
...
This commit is contained in:
@@ -289,6 +289,19 @@ ndo_tx_timeout:
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ndo_set_rx_mode:
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Synchronization: netif_addr_lock spinlock.
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Context: BHs disabled
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Notes: Deprecated in favor of ndo_set_rx_mode_async which runs
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in process context.
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ndo_set_rx_mode_async:
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Synchronization: rtnl_lock() semaphore. In addition, netdev instance
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lock if the driver implements queue management or shaper API.
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Context: process (from a work queue)
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Notes: Async version of ndo_set_rx_mode which runs in process
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context. Receives snapshots of the unicast and multicast address lists.
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ndo_change_rx_flags:
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Synchronization: rtnl_lock() semaphore. In addition, netdev instance
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lock if the driver implements queue management or shaper API.
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ndo_setup_tc:
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``TC_SETUP_BLOCK`` and ``TC_SETUP_FT`` are running under NFT locks
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@@ -528,7 +528,7 @@ The exact rules a driver must follow to acquire the ``Supported`` status:
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status will be withdrawn.
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5. Test failures due to bugs either in the driver or the test itself,
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or lack of support for the feature the test is targgeting are
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or lack of support for the feature the test is targeting are
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*not* a basis for losing the ``Supported`` status.
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netdev CI will maintain an official page of supported devices, listing their
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@@ -15337,6 +15337,13 @@ S: Maintained
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W: http://www.tazenda.demon.co.uk/phil/linux-hp
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F: arch/m68k/hp300/
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M68K ON MVME147
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M: Daniel Palmer <daniel@thingy.jp>
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S: Maintained
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F: arch/m68k/mvme147/
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F: drivers/net/ethernet/amd/mvme147.c
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F: drivers/scsi/mvme147.*
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M88DS3103 MEDIA DRIVER
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L: linux-media@vger.kernel.org
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S: Orphan
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@@ -216,7 +216,7 @@
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(_extint) == 2 ? RTL8365MB_DIGITAL_INTERFACE_SELECT_REG1 : \
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0x0)
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#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_MASK(_extint) \
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(0xF << (((_extint) % 2)))
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(0xF << (((_extint) % 2) * 4))
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#define RTL8365MB_DIGITAL_INTERFACE_SELECT_MODE_OFFSET(_extint) \
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(((_extint) % 2) * 4)
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+4
-2
@@ -47,7 +47,9 @@
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static int numdummies = 1;
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/* fake multicast ability */
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static void set_multicast_list(struct net_device *dev)
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static void set_multicast_list(struct net_device *dev,
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struct netdev_hw_addr_list *uc,
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struct netdev_hw_addr_list *mc)
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{
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}
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@@ -87,7 +89,7 @@ static const struct net_device_ops dummy_netdev_ops = {
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.ndo_init = dummy_dev_init,
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.ndo_start_xmit = dummy_xmit,
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.ndo_validate_addr = eth_validate_addr,
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.ndo_set_rx_mode = set_multicast_list,
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.ndo_set_rx_mode_async = set_multicast_list,
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.ndo_set_mac_address = eth_mac_addr,
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.ndo_get_stats64 = dummy_get_stats64,
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.ndo_change_carrier = dummy_change_carrier,
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@@ -745,14 +745,18 @@ static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
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dma_addr_t dma_addr;
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q->buf_size = PAGE_SIZE / 2;
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q->ndesc = ndesc;
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q->qdma = qdma;
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q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry),
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q->entry = devm_kzalloc(eth->dev, ndesc * sizeof(*q->entry),
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GFP_KERNEL);
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if (!q->entry)
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return -ENOMEM;
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q->desc = dmam_alloc_coherent(eth->dev, ndesc * sizeof(*q->desc),
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&dma_addr, GFP_KERNEL);
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if (!q->desc)
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return -ENOMEM;
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q->page_pool = page_pool_create(&pp_params);
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if (IS_ERR(q->page_pool)) {
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int err = PTR_ERR(q->page_pool);
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@@ -761,11 +765,7 @@ static int airoha_qdma_init_rx_queue(struct airoha_queue *q,
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return err;
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}
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q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc),
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&dma_addr, GFP_KERNEL);
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if (!q->desc)
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return -ENOMEM;
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q->ndesc = ndesc;
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netif_napi_add(eth->napi_dev, &q->napi, airoha_qdma_rx_napi_poll);
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airoha_qdma_wr(qdma, REG_RX_RING_BASE(qid), dma_addr);
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@@ -843,6 +843,21 @@ static int airoha_qdma_init_rx(struct airoha_qdma *qdma)
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return 0;
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}
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static void airoha_qdma_wake_netdev_txqs(struct airoha_queue *q)
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{
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struct airoha_qdma *qdma = q->qdma;
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struct airoha_eth *eth = qdma->eth;
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int i;
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for (i = 0; i < ARRAY_SIZE(eth->ports); i++) {
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struct airoha_gdm_port *port = eth->ports[i];
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if (port && port->qdma == qdma)
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netif_tx_wake_all_queues(port->dev);
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}
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q->txq_stopped = false;
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}
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static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget)
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{
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struct airoha_tx_irq_queue *irq_q;
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@@ -919,12 +934,21 @@ static int airoha_qdma_tx_napi_poll(struct napi_struct *napi, int budget)
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txq = netdev_get_tx_queue(skb->dev, queue);
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netdev_tx_completed_queue(txq, 1, skb->len);
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if (netif_tx_queue_stopped(txq) &&
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q->ndesc - q->queued >= q->free_thr)
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netif_tx_wake_queue(txq);
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dev_kfree_skb_any(skb);
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}
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if (q->txq_stopped && q->ndesc - q->queued >= q->free_thr) {
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/* Since multiple net_device TX queues can share the
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* same hw QDMA TX queue, there is no guarantee we have
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* inflight packets queued in hw belonging to a
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* net_device TX queue stopped in the xmit path.
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* In order to avoid any potential net_device TX queue
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* stall, we need to wake all the net_device TX queues
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* feeding the same hw QDMA TX queue.
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*/
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airoha_qdma_wake_netdev_txqs(q);
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}
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unlock:
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spin_unlock_bh(&q->lock);
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}
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@@ -954,27 +978,27 @@ static int airoha_qdma_init_tx_queue(struct airoha_queue *q,
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dma_addr_t dma_addr;
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spin_lock_init(&q->lock);
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q->ndesc = size;
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q->qdma = qdma;
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q->free_thr = 1 + MAX_SKB_FRAGS;
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INIT_LIST_HEAD(&q->tx_list);
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q->entry = devm_kzalloc(eth->dev, q->ndesc * sizeof(*q->entry),
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q->entry = devm_kzalloc(eth->dev, size * sizeof(*q->entry),
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GFP_KERNEL);
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if (!q->entry)
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return -ENOMEM;
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q->desc = dmam_alloc_coherent(eth->dev, q->ndesc * sizeof(*q->desc),
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q->desc = dmam_alloc_coherent(eth->dev, size * sizeof(*q->desc),
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&dma_addr, GFP_KERNEL);
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if (!q->desc)
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return -ENOMEM;
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for (i = 0; i < q->ndesc; i++) {
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for (i = 0; i < size; i++) {
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u32 val = FIELD_PREP(QDMA_DESC_DONE_MASK, 1);
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list_add_tail(&q->entry[i].list, &q->tx_list);
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WRITE_ONCE(q->desc[i].ctrl, cpu_to_le32(val));
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}
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q->ndesc = size;
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/* xmit ring drop default setting */
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airoha_qdma_set(qdma, REG_TX_RING_BLOCKING(qid),
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@@ -996,8 +1020,6 @@ static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q,
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struct airoha_eth *eth = qdma->eth;
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dma_addr_t dma_addr;
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netif_napi_add_tx(eth->napi_dev, &irq_q->napi,
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airoha_qdma_tx_napi_poll);
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irq_q->q = dmam_alloc_coherent(eth->dev, size * sizeof(u32),
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&dma_addr, GFP_KERNEL);
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if (!irq_q->q)
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@@ -1007,6 +1029,9 @@ static int airoha_qdma_tx_irq_init(struct airoha_tx_irq_queue *irq_q,
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irq_q->size = size;
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irq_q->qdma = qdma;
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netif_napi_add_tx(eth->napi_dev, &irq_q->napi,
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airoha_qdma_tx_napi_poll);
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airoha_qdma_wr(qdma, REG_TX_IRQ_BASE(id), dma_addr);
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airoha_qdma_rmw(qdma, REG_TX_IRQ_CFG(id), TX_IRQ_DEPTH_MASK,
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FIELD_PREP(TX_IRQ_DEPTH_MASK, size));
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@@ -1039,12 +1064,15 @@ static int airoha_qdma_init_tx(struct airoha_qdma *qdma)
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static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
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{
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struct airoha_eth *eth = q->qdma->eth;
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int i;
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struct airoha_qdma *qdma = q->qdma;
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struct airoha_eth *eth = qdma->eth;
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int i, qid = q - &qdma->q_tx[0];
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u16 index = 0;
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spin_lock_bh(&q->lock);
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for (i = 0; i < q->ndesc; i++) {
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struct airoha_queue_entry *e = &q->entry[i];
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struct airoha_qdma_desc *desc = &q->desc[i];
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if (!e->dma_addr)
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continue;
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@@ -1055,8 +1083,33 @@ static void airoha_qdma_cleanup_tx_queue(struct airoha_queue *q)
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e->dma_addr = 0;
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e->skb = NULL;
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list_add_tail(&e->list, &q->tx_list);
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/* Reset DMA descriptor */
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WRITE_ONCE(desc->ctrl, 0);
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WRITE_ONCE(desc->addr, 0);
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WRITE_ONCE(desc->data, 0);
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WRITE_ONCE(desc->msg0, 0);
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WRITE_ONCE(desc->msg1, 0);
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WRITE_ONCE(desc->msg2, 0);
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q->queued--;
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}
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if (!list_empty(&q->tx_list)) {
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struct airoha_queue_entry *e;
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e = list_first_entry(&q->tx_list, struct airoha_queue_entry,
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list);
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index = e - q->entry;
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}
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/* Set TX_DMA_IDX to TX_CPU_IDX to notify the hw the QDMA TX ring is
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* empty.
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*/
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airoha_qdma_rmw(qdma, REG_TX_CPU_IDX(qid), TX_RING_CPU_IDX_MASK,
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FIELD_PREP(TX_RING_CPU_IDX_MASK, index));
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airoha_qdma_rmw(qdma, REG_TX_DMA_IDX(qid), TX_RING_DMA_IDX_MASK,
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FIELD_PREP(TX_RING_DMA_IDX_MASK, index));
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spin_unlock_bh(&q->lock);
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}
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@@ -1398,8 +1451,12 @@ static void airoha_qdma_cleanup(struct airoha_qdma *qdma)
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}
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}
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for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++)
|
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for (i = 0; i < ARRAY_SIZE(qdma->q_tx_irq); i++) {
|
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if (!qdma->q_tx_irq[i].size)
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continue;
|
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|
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netif_napi_del(&qdma->q_tx_irq[i].napi);
|
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}
|
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|
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for (i = 0; i < ARRAY_SIZE(qdma->q_tx); i++) {
|
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if (!qdma->q_tx[i].ndesc)
|
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@@ -1727,7 +1784,7 @@ static int airoha_set_gdm2_loopback(struct airoha_gdm_port *port)
|
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{
|
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struct airoha_eth *eth = port->qdma->eth;
|
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u32 val, pse_port, chan;
|
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int src_port;
|
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int i, src_port;
|
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|
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/* Forward the traffic to the proper GDM port */
|
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pse_port = port->id == AIROHA_GDM3_IDX ? FE_PSE_PORT_GDM3
|
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@@ -1769,6 +1826,9 @@ static int airoha_set_gdm2_loopback(struct airoha_gdm_port *port)
|
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SP_CPORT_MASK(val),
|
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__field_prep(SP_CPORT_MASK(val), FE_PSE_PORT_CDM2));
|
||||
|
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for (i = 0; i < eth->soc->num_ppe; i++)
|
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airoha_ppe_set_cpu_port(port, i, AIROHA_GDM2_IDX);
|
||||
|
||||
if (port->id == AIROHA_GDM4_IDX && airoha_is_7581(eth)) {
|
||||
u32 mask = FC_ID_OF_SRC_PORT_MASK(port->nbq);
|
||||
|
||||
@@ -1807,7 +1867,8 @@ static int airoha_dev_init(struct net_device *dev)
|
||||
}
|
||||
|
||||
for (i = 0; i < eth->soc->num_ppe; i++)
|
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airoha_ppe_set_cpu_port(port, i);
|
||||
airoha_ppe_set_cpu_port(port, i,
|
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airoha_get_fe_port(port));
|
||||
|
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return 0;
|
||||
}
|
||||
@@ -1984,6 +2045,7 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
|
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if (q->queued + nr_frags >= q->ndesc) {
|
||||
/* not enough space in the queue */
|
||||
netif_tx_stop_queue(txq);
|
||||
q->txq_stopped = true;
|
||||
spin_unlock_bh(&q->lock);
|
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return NETDEV_TX_BUSY;
|
||||
}
|
||||
@@ -2039,8 +2101,10 @@ static netdev_tx_t airoha_dev_xmit(struct sk_buff *skb,
|
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TX_RING_CPU_IDX_MASK,
|
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FIELD_PREP(TX_RING_CPU_IDX_MASK, index));
|
||||
|
||||
if (q->ndesc - q->queued < q->free_thr)
|
||||
if (q->ndesc - q->queued < q->free_thr) {
|
||||
netif_tx_stop_queue(txq);
|
||||
q->txq_stopped = true;
|
||||
}
|
||||
|
||||
spin_unlock_bh(&q->lock);
|
||||
|
||||
|
||||
@@ -193,6 +193,7 @@ struct airoha_queue {
|
||||
int ndesc;
|
||||
int free_thr;
|
||||
int buf_size;
|
||||
bool txq_stopped;
|
||||
|
||||
struct napi_struct napi;
|
||||
struct page_pool *page_pool;
|
||||
@@ -653,7 +654,8 @@ int airoha_get_fe_port(struct airoha_gdm_port *port);
|
||||
bool airoha_is_valid_gdm_port(struct airoha_eth *eth,
|
||||
struct airoha_gdm_port *port);
|
||||
|
||||
void airoha_ppe_set_cpu_port(struct airoha_gdm_port *port, u8 ppe_id);
|
||||
void airoha_ppe_set_cpu_port(struct airoha_gdm_port *port, u8 ppe_id,
|
||||
u8 fport);
|
||||
bool airoha_ppe_is_enabled(struct airoha_eth *eth, int index);
|
||||
void airoha_ppe_check_skb(struct airoha_ppe_dev *dev, struct sk_buff *skb,
|
||||
u16 hash, bool rx_wlan);
|
||||
|
||||
@@ -85,10 +85,9 @@ static u32 airoha_ppe_get_timestamp(struct airoha_ppe *ppe)
|
||||
return FIELD_GET(AIROHA_FOE_IB1_BIND_TIMESTAMP, timestamp);
|
||||
}
|
||||
|
||||
void airoha_ppe_set_cpu_port(struct airoha_gdm_port *port, u8 ppe_id)
|
||||
void airoha_ppe_set_cpu_port(struct airoha_gdm_port *port, u8 ppe_id, u8 fport)
|
||||
{
|
||||
struct airoha_qdma *qdma = port->qdma;
|
||||
u8 fport = airoha_get_fe_port(port);
|
||||
struct airoha_eth *eth = qdma->eth;
|
||||
u8 qdma_id = qdma - ð->qdma[0];
|
||||
u32 fe_cpu_port;
|
||||
@@ -182,7 +181,8 @@ static void airoha_ppe_hw_init(struct airoha_ppe *ppe)
|
||||
if (!port)
|
||||
continue;
|
||||
|
||||
airoha_ppe_set_cpu_port(port, i);
|
||||
airoha_ppe_set_cpu_port(port, i,
|
||||
airoha_get_fe_port(port));
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -1356,6 +1356,29 @@ static struct airoha_npu *airoha_ppe_npu_get(struct airoha_eth *eth)
|
||||
return npu;
|
||||
}
|
||||
|
||||
static int airoha_ppe_wait_for_npu_init(struct airoha_eth *eth)
|
||||
{
|
||||
int err;
|
||||
u32 val;
|
||||
|
||||
/* PPE_FLOW_CFG default register value is 0. Since we reset FE
|
||||
* during the device probe we can just check the configured value
|
||||
* is not 0 here.
|
||||
*/
|
||||
err = read_poll_timeout(airoha_fe_rr, val, val, USEC_PER_MSEC,
|
||||
100 * USEC_PER_MSEC, false, eth,
|
||||
REG_PPE_PPE_FLOW_CFG(0));
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
if (airoha_ppe_is_enabled(eth, 1))
|
||||
err = read_poll_timeout(airoha_fe_rr, val, val, USEC_PER_MSEC,
|
||||
100 * USEC_PER_MSEC, false, eth,
|
||||
REG_PPE_PPE_FLOW_CFG(1));
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int airoha_ppe_offload_setup(struct airoha_eth *eth)
|
||||
{
|
||||
struct airoha_npu *npu = airoha_ppe_npu_get(eth);
|
||||
@@ -1369,6 +1392,11 @@ static int airoha_ppe_offload_setup(struct airoha_eth *eth)
|
||||
if (err)
|
||||
goto error_npu_put;
|
||||
|
||||
/* Wait for NPU PPE configuration to complete */
|
||||
err = airoha_ppe_wait_for_npu_init(eth);
|
||||
if (err)
|
||||
goto error_npu_put;
|
||||
|
||||
ppe_num_stats_entries = airoha_ppe_get_total_num_stats_entries(ppe);
|
||||
if (ppe_num_stats_entries > 0) {
|
||||
err = npu->ops.ppe_init_stats(npu, ppe->foe_stats_dma,
|
||||
|
||||
@@ -74,6 +74,13 @@ static int bnge_func_qcaps(struct bnge_dev *bd)
|
||||
return rc;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int bnge_func_qrcaps_qcfg(struct bnge_dev *bd)
|
||||
{
|
||||
int rc;
|
||||
|
||||
rc = bnge_hwrm_func_resc_qcaps(bd);
|
||||
if (rc) {
|
||||
dev_err(bd->dev, "query resc caps failure rc: %d\n", rc);
|
||||
@@ -133,23 +140,28 @@ static int bnge_fw_register_dev(struct bnge_dev *bd)
|
||||
|
||||
bnge_hwrm_fw_set_time(bd);
|
||||
|
||||
rc = bnge_hwrm_func_drv_rgtr(bd);
|
||||
/* Get the resources and configuration from firmware */
|
||||
rc = bnge_func_qcaps(bd);
|
||||
if (rc) {
|
||||
dev_err(bd->dev, "Failed to rgtr with firmware rc: %d\n", rc);
|
||||
dev_err(bd->dev, "Failed querying caps rc: %d\n", rc);
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = bnge_alloc_ctx_mem(bd);
|
||||
if (rc) {
|
||||
dev_err(bd->dev, "Failed to allocate ctx mem rc: %d\n", rc);
|
||||
goto err_func_unrgtr;
|
||||
goto err_free_ctx_mem;
|
||||
}
|
||||
|
||||
/* Get the resources and configuration from firmware */
|
||||
rc = bnge_func_qcaps(bd);
|
||||
rc = bnge_hwrm_func_drv_rgtr(bd);
|
||||
if (rc) {
|
||||
dev_err(bd->dev, "Failed initial configuration rc: %d\n", rc);
|
||||
rc = -ENODEV;
|
||||
dev_err(bd->dev, "Failed to rgtr with firmware rc: %d\n", rc);
|
||||
goto err_free_ctx_mem;
|
||||
}
|
||||
|
||||
rc = bnge_func_qrcaps_qcfg(bd);
|
||||
if (rc) {
|
||||
dev_err(bd->dev, "Failed querying resources rc: %d\n", rc);
|
||||
goto err_func_unrgtr;
|
||||
}
|
||||
|
||||
@@ -158,7 +170,9 @@ static int bnge_fw_register_dev(struct bnge_dev *bd)
|
||||
return 0;
|
||||
|
||||
err_func_unrgtr:
|
||||
bnge_fw_unregister_dev(bd);
|
||||
bnge_hwrm_func_drv_unrgtr(bd);
|
||||
err_free_ctx_mem:
|
||||
bnge_free_ctx_mem(bd);
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
@@ -324,7 +324,6 @@ int bnge_alloc_ctx_mem(struct bnge_dev *bd)
|
||||
u32 l2_qps, qp1_qps, max_qps;
|
||||
u32 ena, entries_sp, entries;
|
||||
u32 srqs, max_srqs, min;
|
||||
u32 num_mr, num_ah;
|
||||
u32 extra_srqs = 0;
|
||||
u32 extra_qps = 0;
|
||||
u32 fast_qpmd_qps;
|
||||
@@ -390,21 +389,6 @@ int bnge_alloc_ctx_mem(struct bnge_dev *bd)
|
||||
if (!bnge_is_roce_en(bd))
|
||||
goto skip_rdma;
|
||||
|
||||
ctxm = &ctx->ctx_arr[BNGE_CTX_MRAV];
|
||||
/* 128K extra is needed to accommodate static AH context
|
||||
* allocation by f/w.
|
||||
*/
|
||||
num_mr = min_t(u32, ctxm->max_entries / 2, 1024 * 256);
|
||||
num_ah = min_t(u32, num_mr, 1024 * 128);
|
||||
ctxm->split_entry_cnt = BNGE_CTX_MRAV_AV_SPLIT_ENTRY + 1;
|
||||
if (!ctxm->mrav_av_entries || ctxm->mrav_av_entries > num_ah)
|
||||
ctxm->mrav_av_entries = num_ah;
|
||||
|
||||
rc = bnge_setup_ctxm_pg_tbls(bd, ctxm, num_mr + num_ah, 2);
|
||||
if (rc)
|
||||
return rc;
|
||||
ena |= FUNC_BACKING_STORE_CFG_REQ_ENABLES_MRAV;
|
||||
|
||||
ctxm = &ctx->ctx_arr[BNGE_CTX_TIM];
|
||||
rc = bnge_setup_ctxm_pg_tbls(bd, ctxm, l2_qps + qp1_qps + extra_qps, 1);
|
||||
if (rc)
|
||||
|
||||
@@ -11132,8 +11132,9 @@ static int bnxt_setup_nitroa0_vnic(struct bnxt *bp)
|
||||
return rc;
|
||||
}
|
||||
|
||||
static int bnxt_cfg_rx_mode(struct bnxt *);
|
||||
static bool bnxt_mc_list_updated(struct bnxt *, u32 *);
|
||||
static int bnxt_cfg_rx_mode(struct bnxt *, struct netdev_hw_addr_list *, bool);
|
||||
static bool bnxt_mc_list_updated(struct bnxt *, u32 *,
|
||||
const struct netdev_hw_addr_list *);
|
||||
|
||||
static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
|
||||
{
|
||||
@@ -11223,11 +11224,11 @@ static int bnxt_init_chip(struct bnxt *bp, bool irq_re_init)
|
||||
} else if (bp->dev->flags & IFF_MULTICAST) {
|
||||
u32 mask = 0;
|
||||
|
||||
bnxt_mc_list_updated(bp, &mask);
|
||||
bnxt_mc_list_updated(bp, &mask, &bp->dev->mc);
|
||||
vnic->rx_mask |= mask;
|
||||
}
|
||||
|
||||
rc = bnxt_cfg_rx_mode(bp);
|
||||
rc = bnxt_cfg_rx_mode(bp, &bp->dev->uc, true);
|
||||
if (rc)
|
||||
goto err_out;
|
||||
|
||||
@@ -13622,17 +13623,17 @@ void bnxt_get_ring_drv_stats(struct bnxt *bp,
|
||||
bnxt_get_one_ring_drv_stats(bp, stats, &bp->bnapi[i]->cp_ring);
|
||||
}
|
||||
|
||||
static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
|
||||
static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask,
|
||||
const struct netdev_hw_addr_list *mc)
|
||||
{
|
||||
struct bnxt_vnic_info *vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
|
||||
struct net_device *dev = bp->dev;
|
||||
struct netdev_hw_addr *ha;
|
||||
u8 *haddr;
|
||||
int mc_count = 0;
|
||||
bool update = false;
|
||||
int off = 0;
|
||||
|
||||
netdev_for_each_mc_addr(ha, dev) {
|
||||
netdev_hw_addr_list_for_each(ha, mc) {
|
||||
if (mc_count >= BNXT_MAX_MC_ADDRS) {
|
||||
*rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
|
||||
vnic->mc_list_count = 0;
|
||||
@@ -13656,17 +13657,17 @@ static bool bnxt_mc_list_updated(struct bnxt *bp, u32 *rx_mask)
|
||||
return update;
|
||||
}
|
||||
|
||||
static bool bnxt_uc_list_updated(struct bnxt *bp)
|
||||
static bool bnxt_uc_list_updated(struct bnxt *bp,
|
||||
const struct netdev_hw_addr_list *uc)
|
||||
{
|
||||
struct net_device *dev = bp->dev;
|
||||
struct bnxt_vnic_info *vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
|
||||
struct netdev_hw_addr *ha;
|
||||
int off = 0;
|
||||
|
||||
if (netdev_uc_count(dev) != (vnic->uc_filter_count - 1))
|
||||
if (netdev_hw_addr_list_count(uc) != (vnic->uc_filter_count - 1))
|
||||
return true;
|
||||
|
||||
netdev_for_each_uc_addr(ha, dev) {
|
||||
netdev_hw_addr_list_for_each(ha, uc) {
|
||||
if (!ether_addr_equal(ha->addr, vnic->uc_list + off))
|
||||
return true;
|
||||
|
||||
@@ -13675,7 +13676,9 @@ static bool bnxt_uc_list_updated(struct bnxt *bp)
|
||||
return false;
|
||||
}
|
||||
|
||||
static void bnxt_set_rx_mode(struct net_device *dev)
|
||||
static void bnxt_set_rx_mode(struct net_device *dev,
|
||||
struct netdev_hw_addr_list *uc,
|
||||
struct netdev_hw_addr_list *mc)
|
||||
{
|
||||
struct bnxt *bp = netdev_priv(dev);
|
||||
struct bnxt_vnic_info *vnic;
|
||||
@@ -13696,7 +13699,7 @@ static void bnxt_set_rx_mode(struct net_device *dev)
|
||||
if (dev->flags & IFF_PROMISC)
|
||||
mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
|
||||
|
||||
uc_update = bnxt_uc_list_updated(bp);
|
||||
uc_update = bnxt_uc_list_updated(bp, uc);
|
||||
|
||||
if (dev->flags & IFF_BROADCAST)
|
||||
mask |= CFA_L2_SET_RX_MASK_REQ_MASK_BCAST;
|
||||
@@ -13704,27 +13707,23 @@ static void bnxt_set_rx_mode(struct net_device *dev)
|
||||
mask |= CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST;
|
||||
vnic->mc_list_count = 0;
|
||||
} else if (dev->flags & IFF_MULTICAST) {
|
||||
mc_update = bnxt_mc_list_updated(bp, &mask);
|
||||
mc_update = bnxt_mc_list_updated(bp, &mask, mc);
|
||||
}
|
||||
|
||||
if (mask != vnic->rx_mask || uc_update || mc_update) {
|
||||
vnic->rx_mask = mask;
|
||||
|
||||
bnxt_queue_sp_work(bp, BNXT_RX_MASK_SP_EVENT);
|
||||
bnxt_cfg_rx_mode(bp, uc, uc_update);
|
||||
}
|
||||
}
|
||||
|
||||
static int bnxt_cfg_rx_mode(struct bnxt *bp)
|
||||
static int bnxt_cfg_rx_mode(struct bnxt *bp, struct netdev_hw_addr_list *uc,
|
||||
bool uc_update)
|
||||
{
|
||||
struct net_device *dev = bp->dev;
|
||||
struct bnxt_vnic_info *vnic = &bp->vnic_info[BNXT_VNIC_DEFAULT];
|
||||
struct netdev_hw_addr *ha;
|
||||
int i, off = 0, rc;
|
||||
bool uc_update;
|
||||
|
||||
netif_addr_lock_bh(dev);
|
||||
uc_update = bnxt_uc_list_updated(bp);
|
||||
netif_addr_unlock_bh(dev);
|
||||
|
||||
if (!uc_update)
|
||||
goto skip_uc;
|
||||
@@ -13739,10 +13738,10 @@ static int bnxt_cfg_rx_mode(struct bnxt *bp)
|
||||
vnic->uc_filter_count = 1;
|
||||
|
||||
netif_addr_lock_bh(dev);
|
||||
if (netdev_uc_count(dev) > (BNXT_MAX_UC_ADDRS - 1)) {
|
||||
if (netdev_hw_addr_list_count(uc) > (BNXT_MAX_UC_ADDRS - 1)) {
|
||||
vnic->rx_mask |= CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS;
|
||||
} else {
|
||||
netdev_for_each_uc_addr(ha, dev) {
|
||||
netdev_hw_addr_list_for_each(ha, uc) {
|
||||
memcpy(vnic->uc_list + off, ha->addr, ETH_ALEN);
|
||||
off += ETH_ALEN;
|
||||
vnic->uc_filter_count++;
|
||||
@@ -14708,6 +14707,7 @@ static void bnxt_ulp_restart(struct bnxt *bp)
|
||||
static void bnxt_sp_task(struct work_struct *work)
|
||||
{
|
||||
struct bnxt *bp = container_of(work, struct bnxt, sp_task);
|
||||
struct net_device *dev = bp->dev;
|
||||
|
||||
set_bit(BNXT_STATE_IN_SP_TASK, &bp->state);
|
||||
smp_mb__after_atomic();
|
||||
@@ -14721,9 +14721,6 @@ static void bnxt_sp_task(struct work_struct *work)
|
||||
bnxt_reenable_sriov(bp);
|
||||
}
|
||||
|
||||
if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event))
|
||||
bnxt_cfg_rx_mode(bp);
|
||||
|
||||
if (test_and_clear_bit(BNXT_RX_NTP_FLTR_SP_EVENT, &bp->sp_event))
|
||||
bnxt_cfg_ntp_filters(bp);
|
||||
if (test_and_clear_bit(BNXT_HWRM_EXEC_FWD_REQ_SP_EVENT, &bp->sp_event))
|
||||
@@ -14788,6 +14785,13 @@ static void bnxt_sp_task(struct work_struct *work)
|
||||
/* These functions below will clear BNXT_STATE_IN_SP_TASK. They
|
||||
* must be the last functions to be called before exiting.
|
||||
*/
|
||||
if (test_and_clear_bit(BNXT_RX_MASK_SP_EVENT, &bp->sp_event)) {
|
||||
bnxt_lock_sp(bp);
|
||||
if (test_bit(BNXT_STATE_OPEN, &bp->state))
|
||||
bnxt_cfg_rx_mode(bp, &dev->uc, true);
|
||||
bnxt_unlock_sp(bp);
|
||||
}
|
||||
|
||||
if (test_and_clear_bit(BNXT_RESET_TASK_SP_EVENT, &bp->sp_event))
|
||||
bnxt_reset(bp, false);
|
||||
|
||||
@@ -15989,7 +15993,7 @@ static const struct net_device_ops bnxt_netdev_ops = {
|
||||
.ndo_start_xmit = bnxt_start_xmit,
|
||||
.ndo_stop = bnxt_close,
|
||||
.ndo_get_stats64 = bnxt_get_stats64,
|
||||
.ndo_set_rx_mode = bnxt_set_rx_mode,
|
||||
.ndo_set_rx_mode_async = bnxt_set_rx_mode,
|
||||
.ndo_eth_ioctl = bnxt_ioctl,
|
||||
.ndo_validate_addr = eth_validate_addr,
|
||||
.ndo_set_mac_address = bnxt_change_mac_addr,
|
||||
|
||||
@@ -7,6 +7,7 @@
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/fsl/netc_global.h>
|
||||
#include <linux/iopoll.h>
|
||||
#include <linux/vmalloc.h>
|
||||
|
||||
#include "ntmp_private.h"
|
||||
|
||||
@@ -42,6 +43,12 @@ int ntmp_init_cbdr(struct netc_cbdr *cbdr, struct device *dev,
|
||||
if (!cbdr->addr_base)
|
||||
return -ENOMEM;
|
||||
|
||||
cbdr->swcbd = vcalloc(cbd_num, sizeof(struct netc_swcbd));
|
||||
if (!cbdr->swcbd) {
|
||||
dma_free_coherent(dev, size, cbdr->addr_base, cbdr->dma_base);
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
cbdr->dma_size = size;
|
||||
cbdr->bd_num = cbd_num;
|
||||
cbdr->regs = *regs;
|
||||
@@ -52,10 +59,10 @@ int ntmp_init_cbdr(struct netc_cbdr *cbdr, struct device *dev,
|
||||
cbdr->addr_base_align = PTR_ALIGN(cbdr->addr_base,
|
||||
NTMP_BASE_ADDR_ALIGN);
|
||||
|
||||
spin_lock_init(&cbdr->ring_lock);
|
||||
mutex_init(&cbdr->ring_lock);
|
||||
|
||||
cbdr->next_to_use = netc_read(cbdr->regs.pir);
|
||||
cbdr->next_to_clean = netc_read(cbdr->regs.cir);
|
||||
cbdr->next_to_clean = netc_read(cbdr->regs.cir) & NETC_CBDRCIR_INDEX;
|
||||
|
||||
/* Step 1: Configure the base address of the Control BD Ring */
|
||||
netc_write(cbdr->regs.bar0, lower_32_bits(cbdr->dma_base_align));
|
||||
@@ -71,10 +78,24 @@ int ntmp_init_cbdr(struct netc_cbdr *cbdr, struct device *dev,
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(ntmp_init_cbdr);
|
||||
|
||||
static void ntmp_free_data_mem(struct device *dev, struct netc_swcbd *swcbd)
|
||||
{
|
||||
if (unlikely(!swcbd->buf))
|
||||
return;
|
||||
|
||||
dma_free_coherent(dev, swcbd->size + NTMP_DATA_ADDR_ALIGN,
|
||||
swcbd->buf, swcbd->dma);
|
||||
}
|
||||
|
||||
void ntmp_free_cbdr(struct netc_cbdr *cbdr)
|
||||
{
|
||||
/* Disable the Control BD Ring */
|
||||
netc_write(cbdr->regs.mr, 0);
|
||||
|
||||
for (int i = 0; i < cbdr->bd_num; i++)
|
||||
ntmp_free_data_mem(cbdr->dev, &cbdr->swcbd[i]);
|
||||
|
||||
vfree(cbdr->swcbd);
|
||||
dma_free_coherent(cbdr->dev, cbdr->dma_size, cbdr->addr_base,
|
||||
cbdr->dma_base);
|
||||
memset(cbdr, 0, sizeof(*cbdr));
|
||||
@@ -94,40 +115,59 @@ static union netc_cbd *ntmp_get_cbd(struct netc_cbdr *cbdr, int index)
|
||||
|
||||
static void ntmp_clean_cbdr(struct netc_cbdr *cbdr)
|
||||
{
|
||||
union netc_cbd *cbd;
|
||||
int i;
|
||||
int i = cbdr->next_to_clean;
|
||||
|
||||
i = cbdr->next_to_clean;
|
||||
while (netc_read(cbdr->regs.cir) != i) {
|
||||
cbd = ntmp_get_cbd(cbdr, i);
|
||||
while ((netc_read(cbdr->regs.cir) & NETC_CBDRCIR_INDEX) != i) {
|
||||
union netc_cbd *cbd = ntmp_get_cbd(cbdr, i);
|
||||
struct netc_swcbd *swcbd = &cbdr->swcbd[i];
|
||||
|
||||
ntmp_free_data_mem(cbdr->dev, swcbd);
|
||||
memset(swcbd, 0, sizeof(*swcbd));
|
||||
memset(cbd, 0, sizeof(*cbd));
|
||||
i = (i + 1) % cbdr->bd_num;
|
||||
}
|
||||
|
||||
dma_wmb();
|
||||
cbdr->next_to_clean = i;
|
||||
}
|
||||
|
||||
static int netc_xmit_ntmp_cmd(struct ntmp_user *user, union netc_cbd *cbd)
|
||||
static void ntmp_select_and_lock_cbdr(struct ntmp_user *user,
|
||||
struct netc_cbdr **cbdr)
|
||||
{
|
||||
/* Currently only ENETC is supported, and it has only one command
|
||||
* BD ring.
|
||||
*/
|
||||
*cbdr = &user->ring[0];
|
||||
|
||||
mutex_lock(&(*cbdr)->ring_lock);
|
||||
}
|
||||
|
||||
static void ntmp_unlock_cbdr(struct netc_cbdr *cbdr)
|
||||
{
|
||||
mutex_unlock(&cbdr->ring_lock);
|
||||
}
|
||||
|
||||
static int netc_xmit_ntmp_cmd(struct netc_cbdr *cbdr, union netc_cbd *cbd,
|
||||
struct netc_swcbd *swcbd)
|
||||
{
|
||||
union netc_cbd *cur_cbd;
|
||||
struct netc_cbdr *cbdr;
|
||||
int i, err;
|
||||
int i, err, used_bds;
|
||||
u16 status;
|
||||
u32 val;
|
||||
|
||||
/* Currently only i.MX95 ENETC is supported, and it only has one
|
||||
* command BD ring
|
||||
*/
|
||||
cbdr = &user->ring[0];
|
||||
|
||||
spin_lock_bh(&cbdr->ring_lock);
|
||||
|
||||
if (unlikely(!ntmp_get_free_cbd_num(cbdr)))
|
||||
used_bds = cbdr->bd_num - ntmp_get_free_cbd_num(cbdr);
|
||||
if (unlikely(used_bds >= NETC_CBDR_CLEAN_WORK)) {
|
||||
ntmp_clean_cbdr(cbdr);
|
||||
if (unlikely(!ntmp_get_free_cbd_num(cbdr))) {
|
||||
ntmp_free_data_mem(cbdr->dev, swcbd);
|
||||
return -EBUSY;
|
||||
}
|
||||
}
|
||||
|
||||
i = cbdr->next_to_use;
|
||||
cur_cbd = ntmp_get_cbd(cbdr, i);
|
||||
*cur_cbd = *cbd;
|
||||
cbdr->swcbd[i] = *swcbd;
|
||||
dma_wmb();
|
||||
|
||||
/* Update producer index of both software and hardware */
|
||||
@@ -135,11 +175,17 @@ static int netc_xmit_ntmp_cmd(struct ntmp_user *user, union netc_cbd *cbd)
|
||||
cbdr->next_to_use = i;
|
||||
netc_write(cbdr->regs.pir, i);
|
||||
|
||||
err = read_poll_timeout_atomic(netc_read, val, val == i,
|
||||
NETC_CBDR_DELAY_US, NETC_CBDR_TIMEOUT,
|
||||
true, cbdr->regs.cir);
|
||||
err = read_poll_timeout(netc_read, val,
|
||||
(val & NETC_CBDRCIR_INDEX) == i,
|
||||
NETC_CBDR_DELAY_US, NETC_CBDR_TIMEOUT,
|
||||
true, cbdr->regs.cir);
|
||||
if (unlikely(err))
|
||||
goto cbdr_unlock;
|
||||
return err;
|
||||
|
||||
if (unlikely(val & NETC_CBDRCIR_SBE)) {
|
||||
dev_err(cbdr->dev, "Command BD system bus error\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
dma_rmb();
|
||||
/* Get the writeback command BD, because the caller may need
|
||||
@@ -150,38 +196,27 @@ static int netc_xmit_ntmp_cmd(struct ntmp_user *user, union netc_cbd *cbd)
|
||||
/* Check the writeback error status */
|
||||
status = le16_to_cpu(cbd->resp_hdr.error_rr) & NTMP_RESP_ERROR;
|
||||
if (unlikely(status)) {
|
||||
err = -EIO;
|
||||
dev_err(user->dev, "Command BD error: 0x%04x\n", status);
|
||||
dev_err(cbdr->dev, "Command BD error: 0x%04x\n", status);
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
ntmp_clean_cbdr(cbdr);
|
||||
dma_wmb();
|
||||
|
||||
cbdr_unlock:
|
||||
spin_unlock_bh(&cbdr->ring_lock);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int ntmp_alloc_data_mem(struct ntmp_dma_buf *data, void **buf_align)
|
||||
{
|
||||
void *buf;
|
||||
|
||||
buf = dma_alloc_coherent(data->dev, data->size + NTMP_DATA_ADDR_ALIGN,
|
||||
&data->dma, GFP_KERNEL);
|
||||
if (!buf)
|
||||
return -ENOMEM;
|
||||
|
||||
data->buf = buf;
|
||||
*buf_align = PTR_ALIGN(buf, NTMP_DATA_ADDR_ALIGN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ntmp_free_data_mem(struct ntmp_dma_buf *data)
|
||||
static int ntmp_alloc_data_mem(struct device *dev, struct netc_swcbd *swcbd,
|
||||
void **buf_align)
|
||||
{
|
||||
dma_free_coherent(data->dev, data->size + NTMP_DATA_ADDR_ALIGN,
|
||||
data->buf, data->dma);
|
||||
void *buf;
|
||||
|
||||
buf = dma_alloc_coherent(dev, swcbd->size + NTMP_DATA_ADDR_ALIGN,
|
||||
&swcbd->dma, GFP_KERNEL);
|
||||
if (!buf)
|
||||
return -ENOMEM;
|
||||
|
||||
swcbd->buf = buf;
|
||||
*buf_align = PTR_ALIGN(buf, NTMP_DATA_ADDR_ALIGN);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static void ntmp_fill_request_hdr(union netc_cbd *cbd, dma_addr_t dma,
|
||||
@@ -234,37 +269,39 @@ static int ntmp_delete_entry_by_id(struct ntmp_user *user, int tbl_id,
|
||||
u8 tbl_ver, u32 entry_id, u32 req_len,
|
||||
u32 resp_len)
|
||||
{
|
||||
struct ntmp_dma_buf data = {
|
||||
.dev = user->dev,
|
||||
struct netc_swcbd swcbd = {
|
||||
.size = max(req_len, resp_len),
|
||||
};
|
||||
struct ntmp_req_by_eid *req;
|
||||
struct netc_cbdr *cbdr;
|
||||
union netc_cbd cbd;
|
||||
int err;
|
||||
|
||||
err = ntmp_alloc_data_mem(&data, (void **)&req);
|
||||
err = ntmp_alloc_data_mem(user->dev, &swcbd, (void **)&req);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
ntmp_fill_crd_eid(req, tbl_ver, 0, 0, entry_id);
|
||||
ntmp_fill_request_hdr(&cbd, data.dma, NTMP_LEN(req_len, resp_len),
|
||||
ntmp_fill_request_hdr(&cbd, swcbd.dma, NTMP_LEN(req_len, resp_len),
|
||||
tbl_id, NTMP_CMD_DELETE, NTMP_AM_ENTRY_ID);
|
||||
|
||||
err = netc_xmit_ntmp_cmd(user, &cbd);
|
||||
ntmp_select_and_lock_cbdr(user, &cbdr);
|
||||
err = netc_xmit_ntmp_cmd(cbdr, &cbd, &swcbd);
|
||||
if (err)
|
||||
dev_err(user->dev,
|
||||
"Failed to delete entry 0x%x of %s, err: %pe",
|
||||
entry_id, ntmp_table_name(tbl_id), ERR_PTR(err));
|
||||
|
||||
ntmp_free_data_mem(&data);
|
||||
ntmp_unlock_cbdr(cbdr);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int ntmp_query_entry_by_id(struct ntmp_user *user, int tbl_id,
|
||||
u32 len, struct ntmp_req_by_eid *req,
|
||||
dma_addr_t dma, bool compare_eid)
|
||||
static int ntmp_query_entry_by_id(struct netc_cbdr *cbdr, int tbl_id,
|
||||
struct ntmp_req_by_eid *req,
|
||||
struct netc_swcbd *swcbd,
|
||||
bool compare_eid)
|
||||
{
|
||||
u32 len = NTMP_LEN(sizeof(*req), swcbd->size);
|
||||
struct ntmp_cmn_resp_query *resp;
|
||||
int cmd = NTMP_CMD_QUERY;
|
||||
union netc_cbd cbd;
|
||||
@@ -276,10 +313,11 @@ static int ntmp_query_entry_by_id(struct ntmp_user *user, int tbl_id,
|
||||
cmd = NTMP_CMD_QU;
|
||||
|
||||
/* Request header */
|
||||
ntmp_fill_request_hdr(&cbd, dma, len, tbl_id, cmd, NTMP_AM_ENTRY_ID);
|
||||
err = netc_xmit_ntmp_cmd(user, &cbd);
|
||||
ntmp_fill_request_hdr(&cbd, swcbd->dma, len, tbl_id, cmd,
|
||||
NTMP_AM_ENTRY_ID);
|
||||
err = netc_xmit_ntmp_cmd(cbdr, &cbd, swcbd);
|
||||
if (err) {
|
||||
dev_err(user->dev,
|
||||
dev_err(cbdr->dev,
|
||||
"Failed to query entry 0x%x of %s, err: %pe\n",
|
||||
entry_id, ntmp_table_name(tbl_id), ERR_PTR(err));
|
||||
return err;
|
||||
@@ -293,7 +331,7 @@ static int ntmp_query_entry_by_id(struct ntmp_user *user, int tbl_id,
|
||||
|
||||
resp = (struct ntmp_cmn_resp_query *)req;
|
||||
if (unlikely(le32_to_cpu(resp->entry_id) != entry_id)) {
|
||||
dev_err(user->dev,
|
||||
dev_err(cbdr->dev,
|
||||
"%s: query EID 0x%x doesn't match response EID 0x%x\n",
|
||||
ntmp_table_name(tbl_id), entry_id, le32_to_cpu(resp->entry_id));
|
||||
return -EIO;
|
||||
@@ -305,15 +343,15 @@ static int ntmp_query_entry_by_id(struct ntmp_user *user, int tbl_id,
|
||||
int ntmp_maft_add_entry(struct ntmp_user *user, u32 entry_id,
|
||||
struct maft_entry_data *maft)
|
||||
{
|
||||
struct ntmp_dma_buf data = {
|
||||
.dev = user->dev,
|
||||
struct netc_swcbd swcbd = {
|
||||
.size = sizeof(struct maft_req_add),
|
||||
};
|
||||
struct maft_req_add *req;
|
||||
struct netc_cbdr *cbdr;
|
||||
union netc_cbd cbd;
|
||||
int err;
|
||||
|
||||
err = ntmp_alloc_data_mem(&data, (void **)&req);
|
||||
err = ntmp_alloc_data_mem(user->dev, &swcbd, (void **)&req);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@@ -322,14 +360,15 @@ int ntmp_maft_add_entry(struct ntmp_user *user, u32 entry_id,
|
||||
req->keye = maft->keye;
|
||||
req->cfge = maft->cfge;
|
||||
|
||||
ntmp_fill_request_hdr(&cbd, data.dma, NTMP_LEN(data.size, 0),
|
||||
ntmp_fill_request_hdr(&cbd, swcbd.dma, NTMP_LEN(swcbd.size, 0),
|
||||
NTMP_MAFT_ID, NTMP_CMD_ADD, NTMP_AM_ENTRY_ID);
|
||||
err = netc_xmit_ntmp_cmd(user, &cbd);
|
||||
|
||||
ntmp_select_and_lock_cbdr(user, &cbdr);
|
||||
err = netc_xmit_ntmp_cmd(cbdr, &cbd, &swcbd);
|
||||
if (err)
|
||||
dev_err(user->dev, "Failed to add MAFT entry 0x%x, err: %pe\n",
|
||||
entry_id, ERR_PTR(err));
|
||||
|
||||
ntmp_free_data_mem(&data);
|
||||
ntmp_unlock_cbdr(cbdr);
|
||||
|
||||
return err;
|
||||
}
|
||||
@@ -338,31 +377,31 @@ EXPORT_SYMBOL_GPL(ntmp_maft_add_entry);
|
||||
int ntmp_maft_query_entry(struct ntmp_user *user, u32 entry_id,
|
||||
struct maft_entry_data *maft)
|
||||
{
|
||||
struct ntmp_dma_buf data = {
|
||||
.dev = user->dev,
|
||||
struct netc_swcbd swcbd = {
|
||||
.size = sizeof(struct maft_resp_query),
|
||||
};
|
||||
struct maft_resp_query *resp;
|
||||
struct ntmp_req_by_eid *req;
|
||||
struct netc_cbdr *cbdr;
|
||||
int err;
|
||||
|
||||
err = ntmp_alloc_data_mem(&data, (void **)&req);
|
||||
err = ntmp_alloc_data_mem(user->dev, &swcbd, (void **)&req);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
ntmp_fill_crd_eid(req, user->tbl.maft_ver, 0, 0, entry_id);
|
||||
err = ntmp_query_entry_by_id(user, NTMP_MAFT_ID,
|
||||
NTMP_LEN(sizeof(*req), data.size),
|
||||
req, data.dma, true);
|
||||
|
||||
ntmp_select_and_lock_cbdr(user, &cbdr);
|
||||
err = ntmp_query_entry_by_id(cbdr, NTMP_MAFT_ID, req, &swcbd, true);
|
||||
if (err)
|
||||
goto end;
|
||||
goto unlock_cbdr;
|
||||
|
||||
resp = (struct maft_resp_query *)req;
|
||||
maft->keye = resp->keye;
|
||||
maft->cfge = resp->cfge;
|
||||
|
||||
end:
|
||||
ntmp_free_data_mem(&data);
|
||||
unlock_cbdr:
|
||||
ntmp_unlock_cbdr(cbdr);
|
||||
|
||||
return err;
|
||||
}
|
||||
@@ -378,8 +417,9 @@ EXPORT_SYMBOL_GPL(ntmp_maft_delete_entry);
|
||||
int ntmp_rsst_update_entry(struct ntmp_user *user, const u32 *table,
|
||||
int count)
|
||||
{
|
||||
struct ntmp_dma_buf data = {.dev = user->dev};
|
||||
struct rsst_req_update *req;
|
||||
struct netc_swcbd swcbd;
|
||||
struct netc_cbdr *cbdr;
|
||||
union netc_cbd cbd;
|
||||
int err, i;
|
||||
|
||||
@@ -387,8 +427,8 @@ int ntmp_rsst_update_entry(struct ntmp_user *user, const u32 *table,
|
||||
/* HW only takes in a full 64 entry table */
|
||||
return -EINVAL;
|
||||
|
||||
data.size = struct_size(req, groups, count);
|
||||
err = ntmp_alloc_data_mem(&data, (void **)&req);
|
||||
swcbd.size = struct_size(req, groups, count);
|
||||
err = ntmp_alloc_data_mem(user->dev, &swcbd, (void **)&req);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
@@ -398,15 +438,15 @@ int ntmp_rsst_update_entry(struct ntmp_user *user, const u32 *table,
|
||||
for (i = 0; i < count; i++)
|
||||
req->groups[i] = (u8)(table[i]);
|
||||
|
||||
ntmp_fill_request_hdr(&cbd, data.dma, NTMP_LEN(data.size, 0),
|
||||
ntmp_fill_request_hdr(&cbd, swcbd.dma, NTMP_LEN(swcbd.size, 0),
|
||||
NTMP_RSST_ID, NTMP_CMD_UPDATE, NTMP_AM_ENTRY_ID);
|
||||
|
||||
err = netc_xmit_ntmp_cmd(user, &cbd);
|
||||
ntmp_select_and_lock_cbdr(user, &cbdr);
|
||||
err = netc_xmit_ntmp_cmd(cbdr, &cbd, &swcbd);
|
||||
if (err)
|
||||
dev_err(user->dev, "Failed to update RSST entry, err: %pe\n",
|
||||
ERR_PTR(err));
|
||||
|
||||
ntmp_free_data_mem(&data);
|
||||
ntmp_unlock_cbdr(cbdr);
|
||||
|
||||
return err;
|
||||
}
|
||||
@@ -414,8 +454,9 @@ EXPORT_SYMBOL_GPL(ntmp_rsst_update_entry);
|
||||
|
||||
int ntmp_rsst_query_entry(struct ntmp_user *user, u32 *table, int count)
|
||||
{
|
||||
struct ntmp_dma_buf data = {.dev = user->dev};
|
||||
struct ntmp_req_by_eid *req;
|
||||
struct netc_swcbd swcbd;
|
||||
struct netc_cbdr *cbdr;
|
||||
union netc_cbd cbd;
|
||||
int err, i;
|
||||
u8 *group;
|
||||
@@ -424,21 +465,23 @@ int ntmp_rsst_query_entry(struct ntmp_user *user, u32 *table, int count)
|
||||
/* HW only takes in a full 64 entry table */
|
||||
return -EINVAL;
|
||||
|
||||
data.size = NTMP_ENTRY_ID_SIZE + RSST_STSE_DATA_SIZE(count) +
|
||||
RSST_CFGE_DATA_SIZE(count);
|
||||
err = ntmp_alloc_data_mem(&data, (void **)&req);
|
||||
swcbd.size = NTMP_ENTRY_ID_SIZE + RSST_STSE_DATA_SIZE(count) +
|
||||
RSST_CFGE_DATA_SIZE(count);
|
||||
err = ntmp_alloc_data_mem(user->dev, &swcbd, (void **)&req);
|
||||
if (err)
|
||||
return err;
|
||||
|
||||
/* Set the request data buffer */
|
||||
ntmp_fill_crd_eid(req, user->tbl.rsst_ver, 0, 0, 0);
|
||||
ntmp_fill_request_hdr(&cbd, data.dma, NTMP_LEN(sizeof(*req), data.size),
|
||||
ntmp_fill_request_hdr(&cbd, swcbd.dma, NTMP_LEN(sizeof(*req), swcbd.size),
|
||||
NTMP_RSST_ID, NTMP_CMD_QUERY, NTMP_AM_ENTRY_ID);
|
||||
err = netc_xmit_ntmp_cmd(user, &cbd);
|
||||
|
||||
ntmp_select_and_lock_cbdr(user, &cbdr);
|
||||
err = netc_xmit_ntmp_cmd(cbdr, &cbd, &swcbd);
|
||||
if (err) {
|
||||
dev_err(user->dev, "Failed to query RSST entry, err: %pe\n",
|
||||
ERR_PTR(err));
|
||||
goto end;
|
||||
goto unlock_cbdr;
|
||||
}
|
||||
|
||||
group = (u8 *)req;
|
||||
@@ -446,8 +489,8 @@ int ntmp_rsst_query_entry(struct ntmp_user *user, u32 *table, int count)
|
||||
for (i = 0; i < count; i++)
|
||||
table[i] = group[i];
|
||||
|
||||
end:
|
||||
ntmp_free_data_mem(&data);
|
||||
unlock_cbdr:
|
||||
ntmp_unlock_cbdr(cbdr);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
@@ -12,6 +12,9 @@
|
||||
|
||||
#define NTMP_EID_REQ_LEN 8
|
||||
#define NETC_CBDR_BD_NUM 256
|
||||
#define NETC_CBDRCIR_INDEX GENMASK(9, 0)
|
||||
#define NETC_CBDRCIR_SBE BIT(31)
|
||||
#define NETC_CBDR_CLEAN_WORK 16
|
||||
|
||||
union netc_cbd {
|
||||
struct {
|
||||
@@ -54,13 +57,6 @@ union netc_cbd {
|
||||
} resp_hdr; /* NTMP Response Message Header Format */
|
||||
};
|
||||
|
||||
struct ntmp_dma_buf {
|
||||
struct device *dev;
|
||||
size_t size;
|
||||
void *buf;
|
||||
dma_addr_t dma;
|
||||
};
|
||||
|
||||
struct ntmp_cmn_req_data {
|
||||
__le16 update_act;
|
||||
u8 dbg_opt;
|
||||
|
||||
@@ -7706,6 +7706,7 @@ static int e1000_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
||||
err_register:
|
||||
if (!(adapter->flags & FLAG_HAS_AMT))
|
||||
e1000e_release_hw_control(adapter);
|
||||
e1000e_ptp_remove(adapter);
|
||||
err_eeprom:
|
||||
if (hw->phy.ops.check_reset_block && !hw->phy.ops.check_reset_block(hw))
|
||||
e1000_phy_hw_reset(&adapter->hw);
|
||||
|
||||
@@ -13783,7 +13783,6 @@ static int i40e_config_netdev(struct i40e_vsi *vsi)
|
||||
netdev->neigh_priv_len = sizeof(u32) * 4;
|
||||
|
||||
netdev->priv_flags |= IFF_UNICAST_FLT;
|
||||
netdev->priv_flags |= IFF_SUPP_NOFCS;
|
||||
/* Setup netdev TC information */
|
||||
i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
|
||||
|
||||
|
||||
@@ -1150,14 +1150,18 @@ bool iavf_promiscuous_mode_changed(struct iavf_adapter *adapter)
|
||||
/**
|
||||
* iavf_set_rx_mode - NDO callback to set the netdev filters
|
||||
* @netdev: network interface device structure
|
||||
* @uc: snapshot of uc address list
|
||||
* @mc: snapshot of mc address list
|
||||
**/
|
||||
static void iavf_set_rx_mode(struct net_device *netdev)
|
||||
static void iavf_set_rx_mode(struct net_device *netdev,
|
||||
struct netdev_hw_addr_list *uc,
|
||||
struct netdev_hw_addr_list *mc)
|
||||
{
|
||||
struct iavf_adapter *adapter = netdev_priv(netdev);
|
||||
|
||||
spin_lock_bh(&adapter->mac_vlan_list_lock);
|
||||
__dev_uc_sync(netdev, iavf_addr_sync, iavf_addr_unsync);
|
||||
__dev_mc_sync(netdev, iavf_addr_sync, iavf_addr_unsync);
|
||||
__hw_addr_sync_dev(uc, netdev, iavf_addr_sync, iavf_addr_unsync);
|
||||
__hw_addr_sync_dev(mc, netdev, iavf_addr_sync, iavf_addr_unsync);
|
||||
spin_unlock_bh(&adapter->mac_vlan_list_lock);
|
||||
|
||||
spin_lock_bh(&adapter->current_netdev_promisc_flags_lock);
|
||||
@@ -1210,7 +1214,9 @@ static void iavf_configure(struct iavf_adapter *adapter)
|
||||
struct net_device *netdev = adapter->netdev;
|
||||
int i;
|
||||
|
||||
iavf_set_rx_mode(netdev);
|
||||
netif_addr_lock_bh(netdev);
|
||||
iavf_set_rx_mode(netdev, &netdev->uc, &netdev->mc);
|
||||
netif_addr_unlock_bh(netdev);
|
||||
|
||||
iavf_configure_tx(adapter);
|
||||
iavf_configure_rx(adapter);
|
||||
@@ -5153,7 +5159,7 @@ static const struct net_device_ops iavf_netdev_ops = {
|
||||
.ndo_open = iavf_open,
|
||||
.ndo_stop = iavf_close,
|
||||
.ndo_start_xmit = iavf_xmit_frame,
|
||||
.ndo_set_rx_mode = iavf_set_rx_mode,
|
||||
.ndo_set_rx_mode_async = iavf_set_rx_mode,
|
||||
.ndo_validate_addr = eth_validate_addr,
|
||||
.ndo_set_mac_address = iavf_set_mac,
|
||||
.ndo_change_mtu = iavf_change_mtu,
|
||||
|
||||
@@ -277,7 +277,7 @@ struct iavf_rx_desc {
|
||||
/* L2 Tag 2 Presence */
|
||||
#define IAVF_RXD_LEGACY_L2TAG2P_M BIT(0)
|
||||
/* Stripped S-TAG VLAN from the receive packet */
|
||||
#define IAVF_RXD_LEGACY_L2TAG2_M GENMASK_ULL(63, 32)
|
||||
#define IAVF_RXD_LEGACY_L2TAG2_M GENMASK_ULL(63, 48)
|
||||
/* Stripped S-TAG VLAN from the receive packet */
|
||||
#define IAVF_RXD_FLEX_L2TAG2_2_M GENMASK_ULL(63, 48)
|
||||
/* The packet is a UDP tunneled packet */
|
||||
|
||||
@@ -753,7 +753,7 @@ static inline bool ice_is_xdp_ena_vsi(struct ice_vsi *vsi)
|
||||
|
||||
static inline void ice_set_ring_xdp(struct ice_tx_ring *ring)
|
||||
{
|
||||
ring->flags |= ICE_TX_FLAGS_RING_XDP;
|
||||
set_bit(ICE_TX_RING_FLAGS_XDP, ring->flags);
|
||||
}
|
||||
|
||||
/**
|
||||
@@ -778,7 +778,7 @@ static inline bool ice_is_txtime_ena(const struct ice_tx_ring *ring)
|
||||
*/
|
||||
static inline bool ice_is_txtime_cfg(const struct ice_tx_ring *ring)
|
||||
{
|
||||
return !!(ring->flags & ICE_TX_FLAGS_TXTIME);
|
||||
return test_bit(ICE_TX_RING_FLAGS_TXTIME, ring->flags);
|
||||
}
|
||||
|
||||
/**
|
||||
|
||||
@@ -1252,7 +1252,7 @@ struct ice_aqc_get_link_status_data {
|
||||
#define ICE_AQ_LINK_PWR_QSFP_CLASS_3 2
|
||||
#define ICE_AQ_LINK_PWR_QSFP_CLASS_4 3
|
||||
__le16 link_speed;
|
||||
#define ICE_AQ_LINK_SPEED_M 0x7FF
|
||||
#define ICE_AQ_LINK_SPEED_M GENMASK(11, 0)
|
||||
#define ICE_AQ_LINK_SPEED_10MB BIT(0)
|
||||
#define ICE_AQ_LINK_SPEED_100MB BIT(1)
|
||||
#define ICE_AQ_LINK_SPEED_1000MB BIT(2)
|
||||
|
||||
@@ -943,7 +943,7 @@ ice_tx_prepare_vlan_flags_dcb(struct ice_tx_ring *tx_ring,
|
||||
/* if this is not already set it means a VLAN 0 + priority needs
|
||||
* to be offloaded
|
||||
*/
|
||||
if (tx_ring->flags & ICE_TX_FLAGS_RING_VLAN_L2TAG2)
|
||||
if (test_bit(ICE_TX_RING_FLAGS_VLAN_L2TAG2, tx_ring->flags))
|
||||
first->tx_flags |= ICE_TX_FLAGS_HW_OUTER_SINGLE_VLAN;
|
||||
else
|
||||
first->tx_flags |= ICE_TX_FLAGS_HW_VLAN;
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user