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Merge tag 'drm-misc-next-2025-11-05-1' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next

Browse Source 
drm-misc-next for v6.19-rc1:

UAPI Changes:
- Add userptr support to ivpu.
- Add IOCTL's for resource and telemetry data in amdxdna.

Core Changes:
- Improve some atomic state checking handling.
- drm/client updates.
- Use forward declarations instead of including drm_print.h
- RUse allocation flags in ttm_pool/device_init and allow specifying max
  useful pool size and propagate ENOSPC.
- Updates and fixes to scheduler and bridge code.
- Add support for quirking DisplayID checksum errors.

Driver Changes:
- Assorted cleanups and fixes in rcar-du, accel/ivpu, panel/nv3052cf,
  sti, imxm, accel/qaic, accel/amdxdna, imagination, tidss, sti,
  panthor, vkms.
- Add Samsung S6E3FC2X01 DDIC/AMS641RW, Synaptics TDDI series DSI,
  TL121BVMS07-00 (IL79900A) panels.
- Add mali MediaTek MT8196 SoC gpu support.
- Add etnaviv GC8000 Nano Ultra VIP r6205 support.
- Document powervr ge7800 support in the devicetree.

Signed-off-by: Dave Airlie <airlied@redhat.com>

From: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>
Link: https://patch.msgid.link/5afae707-c9aa-4a47-b726-5e1f1aa7a106@linux.intel.com
This commit is contained in:
Dave Airlie
2025-11-07 12:41:26 +10:00
parent 8f037e11d0 6126a7f27f
commit e237dfe708
479 changed files with 3826 additions and 1463 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/accel/qaic/qaic.rst
+4 -4
View File
@@ -36,7 +36,7 @@ polling mode and reenables the IRQ line.
This mitigation in QAIC is very effective. The same lprnet usecase that
generates 100k IRQs per second (per /proc/interrupts) is reduced to roughly 64
IRQs over 5 minutes while keeping the host system stable, and having the same
workload throughput performance (within run to run noise variation).
workload throughput performance (within run-to-run noise variation).
Single MSI Mode
---------------
@@ -49,7 +49,7 @@ useful to be able to fall back to a single MSI when needed.
To support this fallback, we allow the case where only one MSI is able to be
allocated, and share that one MSI between MHI and the DBCs. The device detects
when only one MSI has been configured and directs the interrupts for the DBCs
to the interrupt normally used for MHI. Unfortunately this means that the
to the interrupt normally used for MHI. Unfortunately, this means that the
interrupt handlers for every DBC and MHI wake up for every interrupt that
arrives; however, the DBC threaded irq handlers only are started when work to be
done is detected (MHI will always start its threaded handler).
@@ -62,9 +62,9 @@ never disabled, allowing each new entry to the FIFO to trigger a new interrupt.
Neural Network Control (NNC) Protocol
=====================================
The implementation of NNC is split between the KMD (QAIC) and UMD. In general
The implementation of NNC is split between the KMD (QAIC) and UMD. In general,
QAIC understands how to encode/decode NNC wire protocol, and elements of the
protocol which require kernel space knowledge to process (for example, mapping
protocol which requires kernel space knowledge to process (for example, mapping
host memory to device IOVAs). QAIC understands the structure of a message, and
all of the transactions. QAIC does not understand commands (the payload of a
passthrough transaction).
Documentation/devicetree/bindings/display/bridge/renesas,dsi-csi2-tx.yaml
+2 -1
View File
@@ -157,7 +157,8 @@ examples:
panel@0 {
reg = <0>;
compatible = "raspberrypi,dsi-7inch";
compatible = "raspberrypi,dsi-7inch", "ilitek,ili9881c";
power-supply = <&vcc_lcd_reg>;
port {
panel_in: endpoint {
Documentation/devicetree/bindings/display/panel/ilitek,il79900a.yaml
+68
View File
@@ -0,0 +1,68 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/ilitek,il79900a.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Ilitek IL79900a based MIPI-DSI panels
maintainers:
- Langyan Ye <yelangyan@huaqin.corp-partner.google.com>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
- enum:
- tianma,tl121bvms07-00
- const: ilitek,il79900a
reg:
maxItems: 1
description: DSI virtual channel used by the panel
enable-gpios:
maxItems: 1
description: GPIO specifier for the enable pin
avdd-supply:
description: Positive analog voltage supply (AVDD)
avee-supply:
description: Negative analog voltage supply (AVEE)
pp1800-supply:
description: 1.8V logic voltage supply
backlight: true
required:
- compatible
- reg
- enable-gpios
- avdd-supply
- avee-supply
- pp1800-supply
additionalProperties: false
examples:
- |
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "tianma,tl121bvms07-00", "ilitek,il79900a";
reg = <0>;
enable-gpios = <&pio 25 0>;
avdd-supply = <&reg_avdd>;
avee-supply = <&reg_avee>;
pp1800-supply = <&reg_pp1800>;
backlight = <&backlight>;
};
};
...
Documentation/devicetree/bindings/display/panel/panel-simple-dsi.yaml
-3
View File
@@ -56,8 +56,6 @@ properties:
- panasonic,vvx10f034n00
# Samsung s6e3fa7 1080x2220 based AMS559NK06 AMOLED panel
- samsung,s6e3fa7-ams559nk06
# Samsung s6e3fc2x01 1080x2340 AMOLED panel
- samsung,s6e3fc2x01
# Samsung sofef00 1080x2280 AMOLED panel
- samsung,sofef00
# Shangai Top Display Optoelectronics 7" TL070WSH30 1024x600 TFT LCD panel
@@ -80,7 +78,6 @@ allOf:
properties:
compatible:
enum:
- samsung,s6e3fc2x01
- samsung,sofef00
then:
properties:
Documentation/devicetree/bindings/display/panel/samsung,atna33xc20.yaml
+2
View File
@@ -33,6 +33,8 @@ properties:
- samsung,atna45dc02
# Samsung 15.6" 3K (2880x1620 pixels) eDP AMOLED panel
- samsung,atna56ac03
# Samsung 16.0" 3K (2880x1800 pixels) eDP AMOLED panel
- samsung,atna60cl08
- const: samsung,atna33xc20
enable-gpios: true
Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml
+81
View File
@@ -0,0 +1,81 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/samsung,s6e3fc2x01.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Samsung S6E3FC2X01 AMOLED DDIC
description: The S6E3FC2X01 is display driver IC with connected panel.
maintainers:
- David Heidelberg <david@ixit.cz>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
items:
- enum:
# Samsung 6.41 inch, 1080x2340 pixels, 19.5:9 ratio
- samsung,s6e3fc2x01-ams641rw
- const: samsung,s6e3fc2x01
reg:
maxItems: 1
reset-gpios: true
port: true
vddio-supply:
description: VDD regulator
vci-supply:
description: VCI regulator
poc-supply:
description: POC regulator
required:
- compatible
- reset-gpios
- vddio-supply
- vci-supply
- poc-supply
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "samsung,s6e3fc2x01-ams641rw", "samsung,s6e3fc2x01";
reg = <0>;
vddio-supply = <&vreg_l14a_1p88>;
vci-supply = <&s2dos05_buck1>;
poc-supply = <&s2dos05_ldo1>;
te-gpios = <&tlmm 10 GPIO_ACTIVE_HIGH>;
reset-gpios = <&tlmm 6 GPIO_ACTIVE_HIGH>;
pinctrl-0 = <&sde_dsi_active &sde_te_active_sleep>;
pinctrl-1 = <&sde_dsi_suspend &sde_te_active_sleep>;
pinctrl-names = "default", "sleep";
port {
panel_in: endpoint {
remote-endpoint = <&mdss_dsi0_out>;
};
};
};
};
...
Documentation/devicetree/bindings/display/panel/synaptics,td4300-panel.yaml
+89
View File
@@ -0,0 +1,89 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/display/panel/synaptics,td4300-panel.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Synaptics TDDI Display Panel Controller
maintainers:
- Kaustabh Chakraborty <kauschluss@disroot.org>
allOf:
- $ref: panel-common.yaml#
properties:
compatible:
enum:
- syna,td4101-panel
- syna,td4300-panel
reg:
maxItems: 1
vio-supply:
description: core I/O voltage supply
vsn-supply:
description: negative voltage supply for analog circuits
vsp-supply:
description: positive voltage supply for analog circuits
backlight-gpios:
maxItems: 1
description: backlight enable GPIO
reset-gpios: true
width-mm: true
height-mm: true
panel-timing: true
required:
- compatible
- reg
- width-mm
- height-mm
- panel-timing
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
dsi {
#address-cells = <1>;
#size-cells = <0>;
panel@0 {
compatible = "syna,td4300-panel";
reg = <0>;
vio-supply = <&panel_vio_reg>;
vsn-supply = <&panel_vsn_reg>;
vsp-supply = <&panel_vsp_reg>;
backlight-gpios = <&gpd3 5 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpd3 4 GPIO_ACTIVE_LOW>;
width-mm = <68>;
height-mm = <121>;
panel-timing {
clock-frequency = <144389520>;
hactive = <1080>;
hsync-len = <4>;
hfront-porch = <120>;
hback-porch = <32>;
vactive = <1920>;
vsync-len = <2>;
vfront-porch = <21>;
vback-porch = <4>;
};
};
};
...
Documentation/devicetree/bindings/gpu/arm,mali-valhall-csf.yaml
+37 -1
View File
@@ -19,6 +19,7 @@ properties:
- items:
- enum:
- mediatek,mt8196-mali
- nxp,imx95-mali # G310
- rockchip,rk3588-mali
- const: arm,mali-valhall-csf # Mali Valhall GPU model/revision is fully discoverable
@@ -45,7 +46,9 @@ properties:
minItems: 1
items:
- const: core
- const: coregroup
- enum:
- coregroup
- stacks
- const: stacks
mali-supply: true
@@ -110,6 +113,27 @@ allOf:
power-domain-names: false
required:
- mali-supply
- if:
properties:
compatible:
contains:
const: mediatek,mt8196-mali
then:
properties:
mali-supply: false
sram-supply: false
operating-points-v2: false
power-domains:
maxItems: 1
power-domain-names: false
clocks:
maxItems: 2
clock-names:
items:
- const: core
- const: stacks
required:
- power-domains
examples:
- |
@@ -145,5 +169,17 @@ examples:
};
};
};
- |
gpu@48000000 {
compatible = "mediatek,mt8196-mali", "arm,mali-valhall-csf";
reg = <0x48000000 0x480000>;
clocks = <&gpufreq 0>, <&gpufreq 1>;
clock-names = "core", "stacks";
interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH 0>,
<GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH 0>;
interrupt-names = "job", "mmu", "gpu";
power-domains = <&gpufreq>;
};
...
Documentation/devicetree/bindings/gpu/img,powervr-rogue.yaml
+7 -2
View File
@@ -19,6 +19,10 @@ properties:
- renesas,r8a77961-gpu
- const: img,img-gx6250
- const: img,img-rogue
- items:
- const: renesas,r8a77965-gpu
- const: img,img-ge7800
- const: img,img-rogue
- items:
- enum:
- ti,am62-gpu
@@ -100,12 +104,12 @@ allOf:
clocks:
maxItems: 1
- if:
properties:
compatible:
contains:
enum:
- img,img-ge7800
- img,img-gx6250
- thead,th1520-gpu
then:
@@ -135,8 +139,9 @@ allOf:
compatible:
contains:
enum:
- img,img-gx6250
- img,img-bxs-4-64
- img,img-ge7800
- img,img-gx6250
then:
properties:
power-domains:
Documentation/gpu/vkms.rst
+8 -11
View File
@@ -159,26 +159,23 @@ To return to graphical mode, do::
sudo systemctl isolate graphical.target
Once you are in text only mode, you can run tests using the --device switch
or IGT_DEVICE variable to specify the device filter for the driver we want
to test. IGT_DEVICE can also be used with the run-test.sh script to run the
Once you are in text only mode, you can run tests using the IGT_FORCE_DRIVER
variable to specify the device filter for the driver we want to test.
IGT_FORCE_DRIVER can also be used with the run-tests.sh script to run the
tests for a specific driver::
sudo ./build/tests/<name of test> --device "sys:/sys/devices/platform/vkms"
sudo IGT_DEVICE="sys:/sys/devices/platform/vkms" ./build/tests/<name of test>
sudo IGT_DEVICE="sys:/sys/devices/platform/vkms" ./scripts/run-tests.sh -t <name of test>
sudo IGT_FORCE_DRIVER="vkms" ./build/tests/<name of test>
sudo IGT_FORCE_DRIVER="vkms" ./scripts/run-tests.sh -t <name of test>
For example, to test the functionality of the writeback library,
we can run the kms_writeback test::
sudo ./build/tests/kms_writeback --device "sys:/sys/devices/platform/vkms"
sudo IGT_DEVICE="sys:/sys/devices/platform/vkms" ./build/tests/kms_writeback
sudo IGT_DEVICE="sys:/sys/devices/platform/vkms" ./scripts/run-tests.sh -t kms_writeback
sudo IGT_FORCE_DRIVER="vkms" ./build/tests/kms_writeback
sudo IGT_FORCE_DRIVER="vkms" ./scripts/run-tests.sh -t kms_writeback
You can also run subtests if you do not want to run the entire test::
sudo ./build/tests/kms_flip --run-subtest basic-plain-flip --device "sys:/sys/devices/platform/vkms"
sudo IGT_DEVICE="sys:/sys/devices/platform/vkms" ./build/tests/kms_flip --run-subtest basic-plain-flip
sudo IGT_FORCE_DRIVER="vkms" ./build/tests/kms_flip --run-subtest basic-plain-flip
Testing With KUnit
==================
MAINTAINERS
+6
View File
@@ -8068,6 +8068,12 @@ S: Maintained
F: Documentation/devicetree/bindings/display/panel/samsung,s6d7aa0.yaml
F: drivers/gpu/drm/panel/panel-samsung-s6d7aa0.c
DRM DRIVER FOR SAMSUNG S6E3FC2X01 DDIC
M: David Heidelberg <david@ixit.cz>
S: Maintained
F: Documentation/devicetree/bindings/display/panel/samsung,s6e3fc2x01.yaml
F: drivers/gpu/drm/panel/panel-samsung-s6e3fc2x01.c
DRM DRIVER FOR SAMSUNG S6E3HA8 PANELS
M: Dzmitry Sankouski <dsankouski@gmail.com>
S: Maintained
arch/arm/boot/dts/st/stih410.dtsi
+187 -129
View File
@@ -34,6 +34,41 @@
status = "disabled";
};
display-subsystem {
compatible = "st,sti-display-subsystem";
ports = <&compositor>, <&hqvdp>, <&tvout>, <&sti_hdmi>;
assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_flexgen CLK_COMPO_DVP>,
<&clk_s_c0_flexgen CLK_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
<&clk_s_d2_flexgen CLK_PIX_GDP1>,
<&clk_s_d2_flexgen CLK_PIX_GDP2>,
<&clk_s_d2_flexgen CLK_PIX_GDP3>,
<&clk_s_d2_flexgen CLK_PIX_GDP4>;
assigned-clock-parents = <0>,
<0>,
<0>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_pll1 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>;
assigned-clock-rates = <297000000>,
<297000000>,
<0>,
<400000000>,
<400000000>;
};
soc {
ohci0: usb@9a03c00 {
compatible = "st,st-ohci-300x";
@@ -99,153 +134,176 @@
status = "disabled";
};
sti-display-subsystem@0 {
compatible = "st,sti-display-subsystem";
#address-cells = <1>;
#size-cells = <1>;
compositor: display-controller@9d11000 {
compatible = "st,stih407-compositor";
reg = <0x9d11000 0x1000>;
reg = <0 0>;
assigned-clocks = <&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_flexgen CLK_COMPO_DVP>,
<&clk_s_c0_flexgen CLK_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
<&clk_s_d2_flexgen CLK_PIX_GDP1>,
<&clk_s_d2_flexgen CLK_PIX_GDP2>,
<&clk_s_d2_flexgen CLK_PIX_GDP3>,
<&clk_s_d2_flexgen CLK_PIX_GDP4>;
clock-names = "compo_main",
"compo_aux",
"pix_main",
"pix_aux",
"pix_gdp1",
"pix_gdp2",
"pix_gdp3",
"pix_gdp4",
"main_parent",
"aux_parent";
assigned-clock-parents = <0>,
<0>,
<0>,
<&clk_s_c0_pll1 0>,
<&clk_s_c0_pll1 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>,
<&clk_s_d2_quadfs 0>,
clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
<&clk_s_c0_flexgen CLK_COMPO_DVP>,
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
<&clk_s_d2_flexgen CLK_PIX_GDP1>,
<&clk_s_d2_flexgen CLK_PIX_GDP2>,
<&clk_s_d2_flexgen CLK_PIX_GDP3>,
<&clk_s_d2_flexgen CLK_PIX_GDP4>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>;
reset-names = "compo-main", "compo-aux";
resets = <&softreset STIH407_COMPO_SOFTRESET>,
<&softreset STIH407_COMPO_SOFTRESET>;
st,vtg = <&vtg_main>, <&vtg_aux>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
compo_main_out: endpoint {
remote-endpoint = <&tvout_in0>;
};
};
port@1 {
reg = <1>;
compo_aux_out: endpoint {
remote-endpoint = <&tvout_in1>;
};
};
};
};
tvout: encoder@8d08000 {
compatible = "st,stih407-tvout";
reg = <0x8d08000 0x1000>;
reg-names = "tvout-reg";
reset-names = "tvout";
resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
<&clk_s_d0_flexgen CLK_PCM_0>,
<&clk_s_d2_flexgen CLK_PIX_HDDAC>,
<&clk_s_d2_flexgen CLK_HDDAC>;
assigned-clock-parents = <&clk_s_d2_quadfs 0>,
<&clk_tmdsout_hdmi>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d0_quadfs 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>;
assigned-clock-rates = <297000000>,
<297000000>,
<0>,
<400000000>,
<400000000>;
ranges;
sti-compositor@9d11000 {
compatible = "st,stih407-compositor";
reg = <0x9d11000 0x1000>;
clock-names = "compo_main",
"compo_aux",
"pix_main",
"pix_aux",
"pix_gdp1",
"pix_gdp2",
"pix_gdp3",
"pix_gdp4",
"main_parent",
"aux_parent";
clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>,
<&clk_s_c0_flexgen CLK_COMPO_DVP>,
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_AUX_DISP>,
<&clk_s_d2_flexgen CLK_PIX_GDP1>,
<&clk_s_d2_flexgen CLK_PIX_GDP2>,
<&clk_s_d2_flexgen CLK_PIX_GDP3>,
<&clk_s_d2_flexgen CLK_PIX_GDP4>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>;
reset-names = "compo-main", "compo-aux";
resets = <&softreset STIH407_COMPO_SOFTRESET>,
<&softreset STIH407_COMPO_SOFTRESET>;
st,vtg = <&vtg_main>, <&vtg_aux>;
};
sti-tvout@8d08000 {
compatible = "st,stih407-tvout";
reg = <0x8d08000 0x1000>;
reg-names = "tvout-reg";
reset-names = "tvout";
resets = <&softreset STIH407_HDTVOUT_SOFTRESET>;
ports {
#address-cells = <1>;
#size-cells = <1>;
assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
<&clk_s_d0_flexgen CLK_PCM_0>,
<&clk_s_d2_flexgen CLK_PIX_HDDAC>,
<&clk_s_d2_flexgen CLK_HDDAC>;
#size-cells = <0>;
assigned-clock-parents = <&clk_s_d2_quadfs 0>,
<&clk_tmdsout_hdmi>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d0_quadfs 0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 0>;
port@0 {
reg = <0>;
tvout_in0: endpoint {
remote-endpoint = <&compo_main_out>;
};
};
port@1 {
reg = <1>;
tvout_in1: endpoint {
remote-endpoint = <&compo_aux_out>;
};
};
port@2 {
reg = <2>;
tvout_out0: endpoint {
remote-endpoint = <&hdmi_in>;
};
};
port@3 {
reg = <3>;
tvout_out1: endpoint {
remote-endpoint = <&hda_in>;
};
};
};
};
sti_hdmi: sti-hdmi@8d04000 {
compatible = "st,stih407-hdmi";
reg = <0x8d04000 0x1000>;
reg-names = "hdmi-reg";
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq";
clock-names = "pix",
"tmds",
"phy",
"audio",
"main_parent",
"aux_parent";
sti_hdmi: hdmi@8d04000 {
compatible = "st,stih407-hdmi";
reg = <0x8d04000 0x1000>;
reg-names = "hdmi-reg";
#sound-dai-cells = <0>;
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "irq";
clock-names = "pix",
"tmds",
"phy",
"audio",
"main_parent",
"aux_parent";
clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
<&clk_s_d0_flexgen CLK_PCM_0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>;
clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>,
<&clk_s_d2_flexgen CLK_TMDS_HDMI>,
<&clk_s_d2_flexgen CLK_REF_HDMIPHY>,
<&clk_s_d0_flexgen CLK_PCM_0>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>;
hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
reset-names = "hdmi";
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
ddc = <&hdmiddc>;
hdmi,hpd-gpio = <&pio5 3 GPIO_ACTIVE_LOW>;
reset-names = "hdmi";
resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>;
ddc = <&hdmiddc>;
port {
hdmi_in: endpoint {
remote-endpoint = <&tvout_out0>;
};
};
};
sti-hda@8d02000 {
compatible = "st,stih407-hda";
status = "disabled";
reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
reg-names = "hda-reg", "video-dacs-ctrl";
clock-names = "pix",
"hddac",
"main_parent",
"aux_parent";
clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
<&clk_s_d2_flexgen CLK_HDDAC>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>;
};
analog@8d02000 {
compatible = "st,stih407-hda";
status = "disabled";
reg = <0x8d02000 0x400>, <0x92b0120 0x4>;
reg-names = "hda-reg", "video-dacs-ctrl";
clock-names = "pix",
"hddac",
"main_parent",
"aux_parent";
clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>,
<&clk_s_d2_flexgen CLK_HDDAC>,
<&clk_s_d2_quadfs 0>,
<&clk_s_d2_quadfs 1>;
sti-hqvdp@9c00000 {
compatible = "st,stih407-hqvdp";
reg = <0x9C00000 0x100000>;
clock-names = "hqvdp", "pix_main";
clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
reset-names = "hqvdp";
resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
st,vtg = <&vtg_main>;
port {
hda_in: endpoint {
remote-endpoint = <&tvout_out1>;
};
};
};
hqvdp: plane@9c00000 {
compatible = "st,stih407-hqvdp";
reg = <0x9C00000 0x100000>;
clock-names = "hqvdp", "pix_main";
clocks = <&clk_s_c0_flexgen CLK_MAIN_DISP>,
<&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>;
reset-names = "hqvdp";
resets = <&softreset STIH407_HDQVDP_SOFTRESET>;
st,vtg = <&vtg_main>;
};
bdisp0:bdisp@9f10000 {
compatible = "st,stih407-bdisp";
reg = <0x9f10000 0x1000>;
arch/arm64/boot/dts/freescale/imx95.dtsi
+37
View File
@@ -250,6 +250,28 @@
clock-output-names = "dummy";
};
gpu_opp_table: opp-table {
compatible = "operating-points-v2";
opp-500000000 {
opp-hz = /bits/ 64 <500000000>;
opp-hz-real = /bits/ 64 <500000000>;
opp-microvolt = <920000>;
};
opp-800000000 {
opp-hz = /bits/ 64 <800000000>;
opp-hz-real = /bits/ 64 <800000000>;
opp-microvolt = <920000>;
};
opp-1000000000 {
opp-hz = /bits/ 64 <1000000000>;
opp-hz-real = /bits/ 64 <1000000000>;
opp-microvolt = <920000>;
};
};
clk_ext1: clock-ext1 {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -2138,6 +2160,21 @@
};
};
gpu: gpu@4d900000 {
compatible = "nxp,imx95-mali", "arm,mali-valhall-csf";
reg = <0 0x4d900000 0 0x480000>;
clocks = <&scmi_clk IMX95_CLK_GPU>, <&scmi_clk IMX95_CLK_GPUAPB>;
clock-names = "core", "coregroup";
interrupts = <GIC_SPI 289 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 290 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 288 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "job", "mmu", "gpu";
operating-points-v2 = <&gpu_opp_table>;
power-domains = <&scmi_devpd IMX95_PD_GPU>;
#cooling-cells = <2>;
dynamic-power-coefficient = <1013>;
};
ddr-pmu@4e090dc0 {
compatible = "fsl,imx95-ddr-pmu", "fsl,imx93-ddr-pmu";
reg = <0x0 0x4e090dc0 0x0 0x200>;
drivers/accel/amdxdna/aie2_ctx.c
+13 -8
View File
@@ -204,10 +204,13 @@ aie2_sched_resp_handler(void *handle, void __iomem *data, size_t size)
cmd_abo = job->cmd_bo;
if (unlikely(!data))
if (unlikely(job->job_timeout)) {
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_TIMEOUT);
ret = -EINVAL;
goto out;
}
if (unlikely(size != sizeof(u32))) {
if (unlikely(!data) || unlikely(size != sizeof(u32))) {
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ABORT);
ret = -EINVAL;
goto out;
@@ -258,6 +261,13 @@ aie2_sched_cmdlist_resp_handler(void *handle, void __iomem *data, size_t size)
int ret = 0;
cmd_abo = job->cmd_bo;
if (unlikely(job->job_timeout)) {
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_TIMEOUT);
ret = -EINVAL;
goto out;
}
if (unlikely(!data) || unlikely(size != sizeof(u32) * 3)) {
amdxdna_cmd_set_state(cmd_abo, ERT_CMD_STATE_ABORT);
ret = -EINVAL;
@@ -370,6 +380,7 @@ aie2_sched_job_timedout(struct drm_sched_job *sched_job)
xdna = hwctx->client->xdna;
trace_xdna_job(sched_job, hwctx->name, "job timedout", job->seq);
job->job_timeout = true;
mutex_lock(&xdna->dev_lock);
aie2_hwctx_stop(xdna, hwctx, sched_job);
@@ -545,7 +556,6 @@ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx)
struct drm_gpu_scheduler *sched;
struct amdxdna_hwctx_priv *priv;
struct amdxdna_gem_obj *heap;
struct amdxdna_dev_hdl *ndev;
int i, ret;
priv = kzalloc(sizeof(*hwctx->priv), GFP_KERNEL);
@@ -643,8 +653,6 @@ int aie2_hwctx_init(struct amdxdna_hwctx *hwctx)
amdxdna_pm_suspend_put(xdna);
hwctx->status = HWCTX_STAT_INIT;
ndev = xdna->dev_handle;
ndev->hwctx_num++;
init_waitqueue_head(&priv->job_free_wq);
XDNA_DBG(xdna, "hwctx %s init completed", hwctx->name);
@@ -677,13 +685,10 @@ free_priv:
void aie2_hwctx_fini(struct amdxdna_hwctx *hwctx)
{
struct amdxdna_dev_hdl *ndev;
struct amdxdna_dev *xdna;
int idx;
xdna = hwctx->client->xdna;
ndev = xdna->dev_handle;
ndev->hwctx_num--;
XDNA_DBG(xdna, "%s sequence number %lld", hwctx->name, hwctx->priv->seq);
drm_sched_entity_destroy(&hwctx->priv->entity);
drivers/accel/amdxdna/aie2_message.c
+380 -205
View File
File diff suppressed because it is too large Load Diff
drivers/accel/amdxdna/aie2_msg_priv.h
+63 -4
View File
@@ -9,7 +9,8 @@
enum aie2_msg_opcode {
MSG_OP_CREATE_CONTEXT = 0x2,
MSG_OP_DESTROY_CONTEXT = 0x3,
MSG_OP_SYNC_BO = 0x7,
MSG_OP_GET_TELEMETRY = 0x4,
MSG_OP_SYNC_BO = 0x7,
MSG_OP_EXECUTE_BUFFER_CF = 0xC,
MSG_OP_QUERY_COL_STATUS = 0xD,
MSG_OP_QUERY_AIE_TILE_INFO = 0xE,
@@ -19,6 +20,7 @@ enum aie2_msg_opcode {
MSG_OP_CHAIN_EXEC_BUFFER_CF = 0x12,
MSG_OP_CHAIN_EXEC_DPU = 0x13,
MSG_OP_CONFIG_DEBUG_BO = 0x14,
MSG_OP_CHAIN_EXEC_NPU = 0x18,
MSG_OP_MAX_XRT_OPCODE,
MSG_OP_SUSPEND = 0x101,
MSG_OP_RESUME = 0x102,
@@ -136,6 +138,28 @@ struct destroy_ctx_resp {
enum aie2_msg_status status;
} __packed;
enum telemetry_type {
TELEMETRY_TYPE_DISABLED,
TELEMETRY_TYPE_HEALTH,
TELEMETRY_TYPE_ERROR_INFO,
TELEMETRY_TYPE_PROFILING,
TELEMETRY_TYPE_DEBUG,
MAX_TELEMETRY_TYPE
};
struct get_telemetry_req {
enum telemetry_type type;
__u64 buf_addr;
__u32 buf_size;
} __packed;
struct get_telemetry_resp {
__u32 major;
__u32 minor;
__u32 size;
enum aie2_msg_status status;
} __packed;
struct execute_buffer_req {
__u32 cu_idx;
__u32 payload[19];
@@ -149,6 +173,16 @@ struct exec_dpu_req {
__u32 payload[35];
} __packed;
enum exec_npu_type {
EXEC_NPU_TYPE_NON_ELF = 0x1,
EXEC_NPU_TYPE_PARTIAL_ELF = 0x2,
};
union exec_req {
struct execute_buffer_req ebuf;
struct exec_dpu_req dpu_req;
};
struct execute_buffer_resp {
enum aie2_msg_status status;
} __packed;
@@ -320,9 +354,6 @@ struct async_event_msg_resp {
} __packed;
#define MAX_CHAIN_CMDBUF_SIZE SZ_4K
#define slot_has_space(slot, offset, payload_size) \
(MAX_CHAIN_CMDBUF_SIZE >= (offset) + (payload_size) + \
sizeof(typeof(slot)))
struct cmd_chain_slot_execbuf_cf {
__u32 cu_idx;
@@ -340,12 +371,40 @@ struct cmd_chain_slot_dpu {
__u32 args[] __counted_by(arg_cnt);
};
#define MAX_NPU_ARGS_SIZE (26 * sizeof(__u32))
struct cmd_chain_slot_npu {
enum exec_npu_type type;
u64 inst_buf_addr;
u64 save_buf_addr;
u64 restore_buf_addr;
u32 inst_size;
u32 save_size;
u32 restore_size;
u32 inst_prop_cnt;
u32 cu_idx;
u32 arg_cnt;
u32 args[] __counted_by(arg_cnt);
} __packed;
struct cmd_chain_req {
__u64 buf_addr;
__u32 buf_size;
__u32 count;
} __packed;
struct cmd_chain_npu_req {
u32 flags;
u32 reserved;
u64 buf_addr;
u32 buf_size;
u32 count;
} __packed;
union exec_chain_req {
struct cmd_chain_npu_req npu_req;
struct cmd_chain_req req;
};
struct cmd_chain_resp {
enum aie2_msg_status status;
__u32 fail_cmd_idx;
drivers/accel/amdxdna/aie2_pci.c
+113
View File
@@ -55,6 +55,7 @@ struct mgmt_mbox_chann_info {
static int aie2_check_protocol(struct amdxdna_dev_hdl *ndev, u32 fw_major, u32 fw_minor)
{
const struct aie2_fw_feature_tbl *feature;
struct amdxdna_dev *xdna = ndev->xdna;
/*
@@ -78,6 +79,17 @@ static int aie2_check_protocol(struct amdxdna_dev_hdl *ndev, u32 fw_major, u32 f
XDNA_ERR(xdna, "Firmware minor version smaller than supported");
return -EINVAL;
}
for (feature = ndev->priv->fw_feature_tbl; feature && feature->min_minor;
feature++) {
if (fw_minor < feature->min_minor)
continue;
if (feature->max_minor > 0 && fw_minor > feature->max_minor)
continue;
set_bit(feature->feature, &ndev->feature_mask);
}
return 0;
}
@@ -587,6 +599,7 @@ static int aie2_init(struct amdxdna_dev *xdna)
}
release_firmware(fw);
aie2_msg_init(ndev);
amdxdna_pm_init(xdna);
return 0;
@@ -825,6 +838,100 @@ static int aie2_get_hwctx_status(struct amdxdna_client *client,
return 0;
}
static int aie2_query_resource_info(struct amdxdna_client *client,
struct amdxdna_drm_get_info *args)
{
struct amdxdna_drm_get_resource_info res_info;
const struct amdxdna_dev_priv *priv;
struct amdxdna_dev_hdl *ndev;
struct amdxdna_dev *xdna;
xdna = client->xdna;
ndev = xdna->dev_handle;
priv = ndev->priv;
res_info.npu_clk_max = priv->dpm_clk_tbl[ndev->max_dpm_level].hclk;
res_info.npu_tops_max = ndev->max_tops;
res_info.npu_task_max = priv->hwctx_limit;
res_info.npu_tops_curr = ndev->curr_tops;
res_info.npu_task_curr = ndev->hwctx_num;
if (copy_to_user(u64_to_user_ptr(args->buffer), &res_info, sizeof(res_info)))
return -EFAULT;
return 0;
}
static int aie2_fill_hwctx_map(struct amdxdna_hwctx *hwctx, void *arg)
{
struct amdxdna_dev *xdna = hwctx->client->xdna;
u32 *map = arg;
if (hwctx->fw_ctx_id >= xdna->dev_handle->priv->hwctx_limit) {
XDNA_ERR(xdna, "Invalid fw ctx id %d/%d ", hwctx->fw_ctx_id,
xdna->dev_handle->priv->hwctx_limit);
return -EINVAL;
}
map[hwctx->fw_ctx_id] = hwctx->id;
return 0;
}
static int aie2_get_telemetry(struct amdxdna_client *client,
struct amdxdna_drm_get_info *args)
{
struct amdxdna_drm_query_telemetry_header *header __free(kfree) = NULL;
u32 telemetry_data_sz, header_sz, elem_num;
struct amdxdna_dev *xdna = client->xdna;
struct amdxdna_client *tmp_client;
int ret;
elem_num = xdna->dev_handle->priv->hwctx_limit;
header_sz = struct_size(header, map, elem_num);
if (args->buffer_size <= header_sz) {
XDNA_ERR(xdna, "Invalid buffer size");
return -EINVAL;
}
telemetry_data_sz = args->buffer_size - header_sz;
if (telemetry_data_sz > SZ_4M) {
XDNA_ERR(xdna, "Buffer size is too big, %d", telemetry_data_sz);
return -EINVAL;
}
header = kzalloc(header_sz, GFP_KERNEL);
if (!header)
return -ENOMEM;
if (copy_from_user(header, u64_to_user_ptr(args->buffer), sizeof(*header))) {
XDNA_ERR(xdna, "Failed to copy telemetry header from user");
return -EFAULT;
}
header->map_num_elements = elem_num;
list_for_each_entry(tmp_client, &xdna->client_list, node) {
ret = amdxdna_hwctx_walk(tmp_client, &header->map,
aie2_fill_hwctx_map);
if (ret)
return ret;
}
ret = aie2_query_telemetry(xdna->dev_handle,
u64_to_user_ptr(args->buffer + header_sz),
telemetry_data_sz, header);
if (ret) {
XDNA_ERR(xdna, "Query telemetry failed ret %d", ret);
return ret;
}
if (copy_to_user(u64_to_user_ptr(args->buffer), header, header_sz)) {
XDNA_ERR(xdna, "Copy header failed");
return -EFAULT;
}
return 0;
}
static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_info *args)
{
struct amdxdna_dev *xdna = client->xdna;
@@ -859,6 +966,12 @@ static int aie2_get_info(struct amdxdna_client *client, struct amdxdna_drm_get_i
case DRM_AMDXDNA_GET_POWER_MODE:
ret = aie2_get_power_mode(client, args);
break;
case DRM_AMDXDNA_QUERY_TELEMETRY:
ret = aie2_get_telemetry(client, args);
break;
case DRM_AMDXDNA_QUERY_RESOURCE_INFO:
ret = aie2_query_resource_info(client, args);
break;
default:
XDNA_ERR(xdna, "Not supported request parameter %u", args->param);
ret = -EOPNOTSUPP;
drivers/accel/amdxdna/aie2_pci.h
+35
View File
@@ -156,6 +156,17 @@ enum aie2_dev_status {
AIE2_DEV_START,
};
struct aie2_exec_msg_ops {
int (*init_cu_req)(struct amdxdna_gem_obj *cmd_bo, void *req,
size_t *size, u32 *msg_op);
int (*init_dpu_req)(struct amdxdna_gem_obj *cmd_bo, void *req,
size_t *size, u32 *msg_op);
void (*init_chain_req)(void *req, u64 slot_addr, size_t size, u32 cmd_cnt);
int (*fill_cf_slot)(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size);
int (*fill_dpu_slot)(struct amdxdna_gem_obj *cmd_bo, void *slot, size_t *size);
u32 (*get_chain_msg_op)(u32 cmd_op);
};
struct amdxdna_dev_hdl {
struct amdxdna_dev *xdna;
const struct amdxdna_dev_priv *priv;
@@ -173,6 +184,8 @@ struct amdxdna_dev_hdl {
u32 total_col;
struct aie_version version;
struct aie_metadata metadata;
unsigned long feature_mask;
struct aie2_exec_msg_ops *exec_msg_ops;
/* power management and clock*/
enum amdxdna_power_mode_type pw_mode;
@@ -182,6 +195,8 @@ struct amdxdna_dev_hdl {
u32 clk_gating;
u32 npuclk_freq;
u32 hclk_freq;
u32 max_tops;
u32 curr_tops;
/* Mailbox and the management channel */
struct mailbox *mbox;
@@ -206,12 +221,26 @@ struct aie2_hw_ops {
int (*set_dpm)(struct amdxdna_dev_hdl *ndev, u32 dpm_level);
};
enum aie2_fw_feature {
AIE2_NPU_COMMAND,
AIE2_FEATURE_MAX
};
struct aie2_fw_feature_tbl {
enum aie2_fw_feature feature;
u32 max_minor;
u32 min_minor;
};
#define AIE2_FEATURE_ON(ndev, feature) test_bit(feature, &(ndev)->feature_mask)
struct amdxdna_dev_priv {
const char *fw_path;
u64 protocol_major;
u64 protocol_minor;
const struct rt_config *rt_config;
const struct dpm_clk_freq *dpm_clk_tbl;
const struct aie2_fw_feature_tbl *fw_feature_tbl;
#define COL_ALIGN_NONE 0
#define COL_ALIGN_NATURE 1
@@ -219,6 +248,7 @@ struct amdxdna_dev_priv {
u32 mbox_dev_addr;
/* If mbox_size is 0, use BAR size. See MBOX_SIZE macro */
u32 mbox_size;
u32 hwctx_limit;
u32 sram_dev_addr;
struct aie2_bar_off_pair sram_offs[SRAM_MAX_INDEX];
struct aie2_bar_off_pair psp_regs_off[PSP_MAX_REGS];
@@ -236,6 +266,7 @@ extern const struct dpm_clk_freq npu1_dpm_clk_table[];
extern const struct dpm_clk_freq npu4_dpm_clk_table[];
extern const struct rt_config npu1_default_rt_cfg[];
extern const struct rt_config npu4_default_rt_cfg[];
extern const struct aie2_fw_feature_tbl npu4_fw_feature_table[];
/* aie2_smu.c */
int aie2_smu_init(struct amdxdna_dev_hdl *ndev);
@@ -260,6 +291,7 @@ int aie2_get_array_async_error(struct amdxdna_dev_hdl *ndev,
struct amdxdna_drm_get_array *args);
/* aie2_message.c */
void aie2_msg_init(struct amdxdna_dev_hdl *ndev);
int aie2_suspend_fw(struct amdxdna_dev_hdl *ndev);
int aie2_resume_fw(struct amdxdna_dev_hdl *ndev);
int aie2_set_runtime_cfg(struct amdxdna_dev_hdl *ndev, u32 type, u64 value);
@@ -273,6 +305,9 @@ int aie2_create_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwct
int aie2_destroy_context(struct amdxdna_dev_hdl *ndev, struct amdxdna_hwctx *hwctx);
int aie2_map_host_buf(struct amdxdna_dev_hdl *ndev, u32 context_id, u64 addr, u64 size);
int aie2_query_status(struct amdxdna_dev_hdl *ndev, char __user *buf, u32 size, u32 *cols_filled);
int aie2_query_telemetry(struct amdxdna_dev_hdl *ndev,
char __user *buf, u32 size,
struct amdxdna_drm_query_telemetry_header *header);
int aie2_register_asyn_event_msg(struct amdxdna_dev_hdl *ndev, dma_addr_t addr, u32 size,
void *handle, int (*cb)(void*, void __iomem *, size_t));
int aie2_config_cu(struct amdxdna_hwctx *hwctx,
drivers/accel/amdxdna/aie2_smu.c
+11
View File
@@ -23,6 +23,13 @@
#define AIE2_SMU_SET_SOFT_DPMLEVEL 0x7
#define AIE2_SMU_SET_HARD_DPMLEVEL 0x8
#define NPU4_DPM_TOPS(ndev, dpm_level) \
({ \
typeof(ndev) _ndev = ndev; \
(4096 * (_ndev)->total_col * \
(_ndev)->priv->dpm_clk_tbl[dpm_level].hclk / 1000000); \
})
static int aie2_smu_exec(struct amdxdna_dev_hdl *ndev, u32 reg_cmd,
u32 reg_arg, u32 *out)
{
@@ -84,6 +91,8 @@ int npu1_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
amdxdna_pm_suspend_put(ndev->xdna);
ndev->hclk_freq = freq;
ndev->dpm_level = dpm_level;
ndev->max_tops = 2 * ndev->total_col;
ndev->curr_tops = ndev->max_tops * freq / 1028;
XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",
ndev->npuclk_freq, ndev->hclk_freq);
@@ -121,6 +130,8 @@ int npu4_set_dpm(struct amdxdna_dev_hdl *ndev, u32 dpm_level)
ndev->npuclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].npuclk;
ndev->hclk_freq = ndev->priv->dpm_clk_tbl[dpm_level].hclk;
ndev->dpm_level = dpm_level;
ndev->max_tops = NPU4_DPM_TOPS(ndev, ndev->max_dpm_level);
ndev->curr_tops = NPU4_DPM_TOPS(ndev, dpm_level);
XDNA_DBG(ndev->xdna, "MP-NPU clock %d, H clock %d\n",
ndev->npuclk_freq, ndev->hclk_freq);
drivers/accel/amdxdna/amdxdna_ctx.c
+3 -3
View File
@@ -113,14 +113,14 @@ void *amdxdna_cmd_get_payload(struct amdxdna_gem_obj *abo, u32 *size)
return &cmd->data[num_masks];
}
int amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo)
u32 amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo)
{
struct amdxdna_cmd *cmd = abo->mem.kva;
u32 num_masks, i;
u32 *cu_mask;
if (amdxdna_cmd_get_op(abo) == ERT_CMD_CHAIN)
return -1;
return INVALID_CU_IDX;
num_masks = 1 + FIELD_GET(AMDXDNA_CMD_EXTRA_CU_MASK, cmd->header);
cu_mask = cmd->data;
@@ -129,7 +129,7 @@ int amdxdna_cmd_get_cu_idx(struct amdxdna_gem_obj *abo)
return ffs(cu_mask[i]) - 1;
}
return -1;
return INVALID_CU_IDX;
}
/*

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