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dt-bindings: clock: dispcc-sm6350: Add MDSS_CORE & MDSS_RSCC resets
Add the indexes for two resets inside the dispcc on SM6350 SoC. Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250919-sm6350-mdss-reset-v1-1-48dcac917c73@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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@@ -42,6 +42,10 @@
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#define DISP_CC_SLEEP_CLK 31
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#define DISP_CC_XO_CLK 32
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/* Resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_RSCC_BCR 1
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/* GDSCs */
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#define MDSS_GDSC 0
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