mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'mtd/for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux
Pull mtd updates from Miquel Raynal:
"MTD core changes:
- Spelling
- http to https updates
NAND core changes:
- Drop useless 'depends on' in Kconfig
- Add an extra level in the Kconfig hierarchy
- Trivial spellings
- Dynamic allocation of the interface configurations
- Dropping the default ONFI timing mode
- Various cleanup (types, structures, naming, comments)
- Hide the chip->data_interface indirection
- Add the generic rb-gpios property
- Add the ->choose_interface_config() hook
- Introduce nand_choose_best_sdr_timings()
- Use default values for tPROG_max and tBERS_max
- Avoid redefining tR_max and tCCS_min
- Add a helper to find the closest ONFI mode
- bcm63xx MTD parsers: simplify CFE detection
Raw NAND controller drivers changes:
- fsl-upm: Deprecation of specific DT properties
- fsl_upm: Driver rework and cleanup in favor of ->exec_op()
- Ingenic: Cleanup ARRAY_SIZE() vs sizeof() use
- brcmnand: ECC error handling on EDU transfers
- brcmnand: Don't default to EDU transfers
- qcom: Set BAM mode only if not set already
- qcom: Avoid write to unavailable register
- gpio: Driver rework in favor of ->exec_op()
- tango: ->exec_op() conversion
- mtk: ->exec_op() conversion
Raw NAND chip drivers changes:
- toshiba: Implement ->choose_interface_config() for TH58NVG2S3HBAI4,
TC58NVG0S3E, and TC58TEG5DCLTA00
- hynix: Implement ->choose_interface_config() for H27UCG8T2ATR-BC
SPI NOR core changes:
- Disable Quad Mode in spi_nor_restore().
- Don't abort BFPT parsing when QER reserved value is used.
- Add support/update capabilities for few flashes.
- Drop s70fl01gs flash: it does not support RDSR(05h) which is
critical for erase/write.
- Merge the SPIMEM DTR bits in spi-nor/next to avoid conflicts during
the release cycle.
SPI NOR controller drivers changes:
- Move the cadence-quadspi driver to spi-mem. The series was taken
through the SPI tree. Merge it also in spi-nor/next to avoid
conflicts during the release cycle.
- intel-spi:
- Add new PCI IDs.
- Ignore the Write Disable command, the controller doesn't support
it.
- Fix performance regression"
* tag 'mtd/for-5.9' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (79 commits)
MTD: pfow.h: drop a duplicated word
MTD: mtd-abi.h: drop a duplicated word
mtd: rawnand: omap_elm: Replace HTTP links with HTTPS ones
mtd: Replace HTTP links with HTTPS ones
mtd: hyperbus: Replace HTTP links with HTTPS ones
mtd: revert "spi-nor: intel: provide a range for poll_timout"
mtd: spi-nor: update read capabilities for w25q64 and s25fl064k
mtd: spi-nor: micron: Add SPI_NOR_DUAL_READ flag on mt25qu02g
mtd: spi-nor: macronix: Add support for mx66u2g45g
mtd: spi-nor: intel-spi: Simulate WRDI command
mtd: spi-nor: Disable the flash quad mode in spi_nor_restore()
mtd: spi-nor: Add capability to disable flash quad mode
mtd: spi-nor: spansion: Remove s70fl01gs from flash_info
mtd: spi-nor: sfdp: do not make invalid quad enable fatal
dt-bindings: mtd: fsl-upm-nand: Deprecate chip-delay and fsl, upm-wait-flags
mtd: rawnand: stm32_fmc2: get resources from parent node
mtd: rawnand: stm32_fmc2: use regmap APIs
memory: stm32-fmc2-ebi: add STM32 FMC2 EBI controller driver
dt-bindings: memory-controller: add STM32 FMC2 EBI controller documentation
dt-bindings: mtd: update STM32 FMC2 NAND controller documentation
...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,252 @@
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/memory-controllers/st,stm32-fmc2-ebi.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
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description: |
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The FMC2 functional block makes the interface with: synchronous and
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asynchronous static devices (such as PSNOR, PSRAM or other memory-mapped
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peripherals) and NAND flash memories.
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Its main purposes are:
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- to translate AXI transactions into the appropriate external device
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protocol
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- to meet the access time requirements of the external devices
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All external devices share the addresses, data and control signals with the
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controller. Each external device is accessed by means of a unique Chip
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Select. The FMC2 performs only one access at a time to an external device.
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maintainers:
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- Christophe Kerello <christophe.kerello@st.com>
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properties:
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compatible:
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const: st,stm32mp1-fmc2-ebi
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reg:
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maxItems: 1
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clocks:
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maxItems: 1
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resets:
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maxItems: 1
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"#address-cells":
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const: 2
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"#size-cells":
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const: 1
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ranges:
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description: |
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Reflects the memory layout with four integer values per bank. Format:
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<bank-number> 0 <address of the bank> <size>
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patternProperties:
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"^.*@[0-4],[a-f0-9]+$":
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type: object
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properties:
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reg:
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description: Bank number, base address and size of the device.
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st,fmc2-ebi-cs-transaction-type:
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description: |
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Select one of the transactions type supported
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0: Asynchronous mode 1 SRAM/FRAM.
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1: Asynchronous mode 1 PSRAM.
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2: Asynchronous mode A SRAM/FRAM.
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3: Asynchronous mode A PSRAM.
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4: Asynchronous mode 2 NOR.
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5: Asynchronous mode B NOR.
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6: Asynchronous mode C NOR.
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7: Asynchronous mode D NOR.
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8: Synchronous read synchronous write PSRAM.
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9: Synchronous read asynchronous write PSRAM.
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10: Synchronous read synchronous write NOR.
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11: Synchronous read asynchronous write NOR.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 11
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st,fmc2-ebi-cs-cclk-enable:
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description: Continuous clock enable (first bank must be configured
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in synchronous mode). The FMC_CLK is generated continuously
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during asynchronous and synchronous access. By default, the
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FMC_CLK is only generated during synchronous access.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-mux-enable:
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description: Address/Data multiplexed on databus (valid only with
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NOR and PSRAM transactions type). By default, Address/Data
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are not multiplexed.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-buswidth:
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description: Data bus width
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 8, 16 ]
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default: 16
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st,fmc2-ebi-cs-waitpol-high:
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description: Wait signal polarity (NWAIT signal active high).
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By default, NWAIT is active low.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-waitcfg-enable:
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description: The NWAIT signal indicates wheither the data from the
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device are valid or if a wait state must be inserted when accessing
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the device in synchronous mode. By default, the NWAIT signal is
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active one data cycle before wait state.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-wait-enable:
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description: The NWAIT signal is enabled (its level is taken into
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account after the programmed latency period to insert wait states
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if asserted). By default, the NWAIT signal is disabled.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-asyncwait-enable:
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description: The NWAIT signal is taken into account during asynchronous
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transactions. By default, the NWAIT signal is not taken into account
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during asynchronous transactions.
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$ref: /schemas/types.yaml#/definitions/flag
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st,fmc2-ebi-cs-cpsize:
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description: CRAM page size. The controller splits the burst access
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when the memory page is reached. By default, no burst split when
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crossing page boundary.
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [ 0, 128, 256, 512, 1024 ]
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default: 0
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st,fmc2-ebi-cs-byte-lane-setup-ns:
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description: This property configures the byte lane setup timing
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defined in nanoseconds from NBLx low to Chip Select NEx low.
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st,fmc2-ebi-cs-address-setup-ns:
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description: This property defines the duration of the address setup
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phase in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-address-hold-ns:
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description: This property defines the duration of the address hold
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phase in nanoseconds used for asynchronous multiplexed read/write
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transactions.
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st,fmc2-ebi-cs-data-setup-ns:
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description: This property defines the duration of the data setup phase
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in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-bus-turnaround-ns:
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description: This property defines the delay in nanoseconds between the
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end of current read/write transaction and the next transaction.
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st,fmc2-ebi-cs-data-hold-ns:
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description: This property defines the duration of the data hold phase
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in nanoseconds used for asynchronous read/write transactions.
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st,fmc2-ebi-cs-clk-period-ns:
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description: This property defines the FMC_CLK output signal period in
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nanoseconds.
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st,fmc2-ebi-cs-data-latency-ns:
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description: This property defines the data latency before reading or
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writing the first data in nanoseconds.
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st,fmc2_ebi-cs-write-address-setup-ns:
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description: This property defines the duration of the address setup
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phase in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-write-address-hold-ns:
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description: This property defines the duration of the address hold
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phase in nanoseconds used for asynchronous multiplexed write
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transactions.
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st,fmc2-ebi-cs-write-data-setup-ns:
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description: This property defines the duration of the data setup
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phase in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-write-bus-turnaround-ns:
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description: This property defines the delay between the end of current
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write transaction and the next transaction in nanoseconds.
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st,fmc2-ebi-cs-write-data-hold-ns:
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description: This property defines the duration of the data hold phase
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in nanoseconds used for asynchronous write transactions.
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st,fmc2-ebi-cs-max-low-pulse-ns:
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description: This property defines the maximum chip select low pulse
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duration in nanoseconds for synchronous transactions. When this timing
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reaches 0, the controller splits the current access, toggles NE to
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allow device refresh and restarts a new access.
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required:
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- reg
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required:
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- "#address-cells"
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- "#size-cells"
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- compatible
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- reg
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- clocks
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- ranges
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/clock/stm32mp1-clks.h>
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#include <dt-bindings/reset/stm32mp1-resets.h>
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memory-controller@58002000 {
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#address-cells = <2>;
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#size-cells = <1>;
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compatible = "st,stm32mp1-fmc2-ebi";
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reg = <0x58002000 0x1000>;
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clocks = <&rcc FMC_K>;
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resets = <&rcc FMC_R>;
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ranges = <0 0 0x60000000 0x04000000>, /* EBI CS 1 */
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<1 0 0x64000000 0x04000000>, /* EBI CS 2 */
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<2 0 0x68000000 0x04000000>, /* EBI CS 3 */
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<3 0 0x6c000000 0x04000000>, /* EBI CS 4 */
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<4 0 0x80000000 0x10000000>; /* NAND */
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psram@0,0 {
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compatible = "mtd-ram";
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reg = <0 0x00000000 0x100000>;
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bank-width = <2>;
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st,fmc2-ebi-cs-transaction-type = <1>;
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st,fmc2-ebi-cs-address-setup-ns = <60>;
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st,fmc2-ebi-cs-data-setup-ns = <30>;
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st,fmc2-ebi-cs-bus-turnaround-ns = <5>;
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};
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nand-controller@4,0 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "st,stm32mp1-fmc2-nfc";
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reg = <4 0x00000000 0x1000>,
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<4 0x08010000 0x1000>,
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<4 0x08020000 0x1000>,
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<4 0x01000000 0x1000>,
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<4 0x09010000 0x1000>,
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<4 0x09020000 0x1000>;
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
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<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
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<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
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dma-names = "tx", "rx", "ecc";
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nand@0 {
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reg = <0>;
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nand-on-flash-bbt;
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#address-cells = <1>;
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#size-cells = <1>;
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};
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};
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};
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...
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@@ -4,8 +4,8 @@ This file provides information, what the device node for the davinci/keystone
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NAND interface contains.
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Documentation:
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Davinci DM646x - http://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
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Kestone - http://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
|
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Davinci DM646x - https://www.ti.com/lit/ug/sprueq7c/sprueq7c.pdf
|
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Kestone - https://www.ti.com/lit/ug/sprugz3a/sprugz3a.pdf
|
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Required properties:
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|
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@@ -7,14 +7,16 @@ Required properties:
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- fsl,upm-cmd-offset : UPM pattern offset for the command latch.
|
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Optional properties:
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- fsl,upm-wait-flags : add chip-dependent short delays after running the
|
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UPM pattern (0x1), after writing a data byte (0x2) or after
|
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writing out a buffer (0x4).
|
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- fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
|
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The corresponding address lines are used to select the chip.
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- gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
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(R/B#). For multi-chip devices, "n" GPIO definitions are required
|
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according to the number of chips.
|
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|
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Deprecated properties:
|
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- fsl,upm-wait-flags : add chip-dependent short delays after running the
|
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UPM pattern (0x1), after writing a data byte (0x2) or after
|
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writing out a buffer (0x4).
|
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- chip-delay : chip dependent delay for transferring data from array to
|
||||
read registers (tR). Required if property "gpios" is not used
|
||||
(R/B# pins not connected).
|
||||
@@ -52,8 +54,6 @@ upm@3,0 {
|
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fsl,upm-cmd-offset = <0x08>;
|
||||
/* Multi-chip NAND device */
|
||||
fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
|
||||
fsl,upm-wait-flags = <0x5>;
|
||||
chip-delay = <25>; // in micro-seconds
|
||||
|
||||
nand@0 {
|
||||
#address-cells = <1>;
|
||||
|
||||
@@ -114,6 +114,13 @@ patternProperties:
|
||||
description:
|
||||
Contains the native Ready/Busy IDs.
|
||||
|
||||
rb-gpios:
|
||||
description:
|
||||
Contains one or more GPIO descriptor (the numper of descriptor
|
||||
depends on the number of R/B pins exposed by the flash) for the
|
||||
Ready/Busy pins. Active state refers to the NAND ready state and
|
||||
should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
|
||||
|
||||
required:
|
||||
- reg
|
||||
|
||||
|
||||
@@ -9,32 +9,19 @@ title: STMicroelectronics Flexible Memory Controller 2 (FMC2) Bindings
|
||||
maintainers:
|
||||
- Christophe Kerello <christophe.kerello@st.com>
|
||||
|
||||
allOf:
|
||||
- $ref: "nand-controller.yaml#"
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: st,stm32mp15-fmc2
|
||||
enum:
|
||||
- st,stm32mp15-fmc2
|
||||
- st,stm32mp1-fmc2-nfc
|
||||
|
||||
reg:
|
||||
items:
|
||||
- description: Registers
|
||||
- description: Chip select 0 data
|
||||
- description: Chip select 0 command
|
||||
- description: Chip select 0 address space
|
||||
- description: Chip select 1 data
|
||||
- description: Chip select 1 command
|
||||
- description: Chip select 1 address space
|
||||
minItems: 6
|
||||
maxItems: 7
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
dmas:
|
||||
items:
|
||||
- description: tx DMA channel
|
||||
@@ -57,11 +44,55 @@ patternProperties:
|
||||
nand-ecc-strength:
|
||||
enum: [1, 4 ,8 ]
|
||||
|
||||
allOf:
|
||||
- $ref: "nand-controller.yaml#"
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: st,stm32mp15-fmc2
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Registers
|
||||
- description: Chip select 0 data
|
||||
- description: Chip select 0 command
|
||||
- description: Chip select 0 address space
|
||||
- description: Chip select 1 data
|
||||
- description: Chip select 1 command
|
||||
- description: Chip select 1 address space
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- clocks
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: st,stm32mp1-fmc2-nfc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: Chip select 0 data
|
||||
- description: Chip select 0 command
|
||||
- description: Chip select 0 address space
|
||||
- description: Chip select 1 data
|
||||
- description: Chip select 1 command
|
||||
- description: Chip select 1 address space
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- clocks
|
||||
|
||||
examples:
|
||||
- |
|
||||
@@ -77,13 +108,13 @@ examples:
|
||||
<0x81000000 0x1000>,
|
||||
<0x89010000 0x1000>,
|
||||
<0x89020000 0x1000>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&mdma1 20 0x10 0x12000a02 0x0 0x0>,
|
||||
<&mdma1 20 0x10 0x12000a08 0x0 0x0>,
|
||||
<&mdma1 21 0x10 0x12000a0a 0x0 0x0>;
|
||||
dma-names = "tx", "rx", "ecc";
|
||||
clocks = <&rcc FMC_K>;
|
||||
resets = <&rcc FMC_R>;
|
||||
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
||||
dmas = <&mdma1 20 0x2 0x12000a02 0x0 0x0>,
|
||||
<&mdma1 20 0x2 0x12000a08 0x0 0x0>,
|
||||
<&mdma1 21 0x2 0x12000a0a 0x0 0x0>;
|
||||
dma-names = "tx", "rx", "ecc";
|
||||
clocks = <&rcc FMC_K>;
|
||||
resets = <&rcc FMC_R>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
|
||||
@@ -188,6 +188,16 @@ config RENESAS_RPCIF
|
||||
host or HyperFlash. You'll have to select individual components
|
||||
under the corresponding menu.
|
||||
|
||||
config STM32_FMC2_EBI
|
||||
tristate "Support for FMC2 External Bus Interface on STM32MP SoCs"
|
||||
depends on MACH_STM32MP157 || COMPILE_TEST
|
||||
select MFD_SYSCON
|
||||
help
|
||||
Select this option to enable the STM32 FMC2 External Bus Interface
|
||||
controller. This driver configures the transactions with external
|
||||
devices (like SRAM, ethernet adapters, FPGAs, LCD displays, ...) on
|
||||
SOCs containing the FMC2 External Bus Interface.
|
||||
|
||||
source "drivers/memory/samsung/Kconfig"
|
||||
source "drivers/memory/tegra/Kconfig"
|
||||
|
||||
|
||||
@@ -23,6 +23,7 @@ obj-$(CONFIG_MTK_SMI) += mtk-smi.o
|
||||
obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o
|
||||
obj-$(CONFIG_PL353_SMC) += pl353-smc.o
|
||||
obj-$(CONFIG_RENESAS_RPCIF) += renesas-rpc-if.o
|
||||
obj-$(CONFIG_STM32_FMC2_EBI) += stm32-fmc2-ebi.o
|
||||
|
||||
obj-$(CONFIG_SAMSUNG_MC) += samsung/
|
||||
obj-$(CONFIG_TEGRA_MC) += tegra/
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -11,7 +11,7 @@ config MTD_CFI
|
||||
AMD and other flash manufactures that provides a universal method
|
||||
for probing the capabilities of flash devices. If you wish to
|
||||
support any device that is CFI-compliant, you need to enable this
|
||||
option. Visit <http://www.amd.com/products/nvd/overview/cfi.html>
|
||||
option. Visit <https://www.amd.com/products/nvd/overview/cfi.html>
|
||||
for more information on CFI.
|
||||
|
||||
config MTD_JEDECPROBE
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
//
|
||||
// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
// Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
|
||||
// Author: Vignesh Raghavendra <vigneshr@ti.com>
|
||||
|
||||
#include <linux/err.h>
|
||||
|
||||
@@ -1,6 +1,6 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
//
|
||||
// Copyright (C) 2019 Texas Instruments Incorporated - http://www.ti.com/
|
||||
// Copyright (C) 2019 Texas Instruments Incorporated - https://www.ti.com/
|
||||
// Author: Vignesh Raghavendra <vigneshr@ti.com>
|
||||
|
||||
#include <linux/err.h>
|
||||
|
||||
@@ -310,7 +310,7 @@ config MTD_DC21285
|
||||
help
|
||||
This provides a driver for the flash accessed using Intel's
|
||||
21285 bridge used with Intel's StrongARM processors. More info at
|
||||
<http://www.intel.com/design/bridge/docs/21285_documentation.htm>.
|
||||
<https://www.intel.com/design/bridge/docs/21285_documentation.htm>.
|
||||
|
||||
config MTD_IXP4XX
|
||||
tristate "CFI Flash device mapped on Intel IXP4xx based systems"
|
||||
|
||||
@@ -6,7 +6,7 @@
|
||||
* The SC520CDP is an evaluation board for the Elan SC520 processor available
|
||||
* from AMD. It has two banks of 32-bit Flash ROM, each 8 Megabytes in size,
|
||||
* and up to 512 KiB of 8-bit DIL Flash ROM.
|
||||
* For details see http://www.amd.com/products/epd/desiging/evalboards/18.elansc520/520_cdp_brief/index.html
|
||||
* For details see https://www.amd.com/products/epd/desiging/evalboards/18.elansc520/520_cdp_brief/index.html
|
||||
*/
|
||||
|
||||
#include <linux/module.h>
|
||||
|
||||
@@ -1,7 +1,12 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
menu "NAND"
|
||||
|
||||
config MTD_NAND_CORE
|
||||
tristate
|
||||
|
||||
source "drivers/mtd/nand/onenand/Kconfig"
|
||||
source "drivers/mtd/nand/raw/Kconfig"
|
||||
source "drivers/mtd/nand/spi/Kconfig"
|
||||
|
||||
endmenu
|
||||
|
||||
@@ -1,7 +1,6 @@
|
||||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
menuconfig MTD_ONENAND
|
||||
tristate "OneNAND Device Support"
|
||||
depends on MTD
|
||||
depends on HAS_IOMEM
|
||||
help
|
||||
This enables support for accessing all type of OneNAND flash
|
||||
|
||||
@@ -12,7 +12,6 @@ config MTD_NAND_ECC_SW_HAMMING_SMC
|
||||
|
||||
menuconfig MTD_RAW_NAND
|
||||
tristate "Raw/Parallel NAND Device Support"
|
||||
depends on MTD
|
||||
select MTD_NAND_CORE
|
||||
select MTD_NAND_ECC_SW_HAMMING
|
||||
help
|
||||
@@ -415,6 +414,7 @@ config MTD_NAND_TEGRA
|
||||
config MTD_NAND_STM32_FMC2
|
||||
tristate "Support for NAND controller on STM32MP SoCs"
|
||||
depends on MACH_STM32MP157 || COMPILE_TEST
|
||||
select MFD_SYSCON
|
||||
help
|
||||
Enables support for NAND Flash chips on SoCs containing the FMC2
|
||||
NAND controller. This controller is found on STM32MP SoCs.
|
||||
|
||||
@@ -191,8 +191,8 @@ static int gpio_nand_exec_op(struct nand_chip *this,
|
||||
return ret;
|
||||
}
|
||||
|
||||
static int gpio_nand_setup_data_interface(struct nand_chip *this, int csline,
|
||||
const struct nand_data_interface *cf)
|
||||
static int gpio_nand_setup_interface(struct nand_chip *this, int csline,
|
||||
const struct nand_interface_config *cf)
|
||||
{
|
||||
struct gpio_nand *priv = nand_get_controller_data(this);
|
||||
const struct nand_sdr_timings *sdr = nand_get_sdr_timings(cf);
|
||||
@@ -217,7 +217,7 @@ static int gpio_nand_setup_data_interface(struct nand_chip *this, int csline,
|
||||
|
||||
static const struct nand_controller_ops gpio_nand_ops = {
|
||||
.exec_op = gpio_nand_exec_op,
|
||||
.setup_data_interface = gpio_nand_setup_data_interface,
|
||||
.setup_interface = gpio_nand_setup_interface,
|
||||
};
|
||||
|
||||
/*
|
||||
|
||||
@@ -854,8 +854,8 @@ static int anfc_exec_op(struct nand_chip *chip,
|
||||
return nand_op_parser_exec_op(chip, &anfc_op_parser, op, check_only);
|
||||
}
|
||||
|
||||
static int anfc_setup_data_interface(struct nand_chip *chip, int target,
|
||||
const struct nand_data_interface *conf)
|
||||
static int anfc_setup_interface(struct nand_chip *chip, int target,
|
||||
const struct nand_interface_config *conf)
|
||||
{
|
||||
struct anand *anand = to_anand(chip);
|
||||
struct arasan_nfc *nfc = to_anfc(chip->controller);
|
||||
@@ -1083,7 +1083,7 @@ static void anfc_detach_chip(struct nand_chip *chip)
|
||||
|
||||
static const struct nand_controller_ops anfc_ops = {
|
||||
.exec_op = anfc_exec_op,
|
||||
.setup_data_interface = anfc_setup_data_interface,
|
||||
.setup_interface = anfc_setup_interface,
|
||||
.attach_chip = anfc_attach_chip,
|
||||
.detach_chip = anfc_detach_chip,
|
||||
};
|
||||
|
||||
@@ -200,8 +200,8 @@ struct atmel_nand_controller_ops {
|
||||
void (*nand_init)(struct atmel_nand_controller *nc,
|
||||
struct atmel_nand *nand);
|
||||
int (*ecc_init)(struct nand_chip *chip);
|
||||
int (*setup_data_interface)(struct atmel_nand *nand, int csline,
|
||||
const struct nand_data_interface *conf);
|
||||
int (*setup_interface)(struct atmel_nand *nand, int csline,
|
||||
const struct nand_interface_config *conf);
|
||||
};
|
||||
|
||||
struct atmel_nand_controller_caps {
|
||||
@@ -1168,7 +1168,7 @@ static int atmel_hsmc_nand_ecc_init(struct nand_chip *chip)
|
||||
}
|
||||
|
||||
static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
|
||||
const struct nand_data_interface *conf,
|
||||
const struct nand_interface_config *conf,
|
||||
struct atmel_smc_cs_conf *smcconf)
|
||||
{
|
||||
u32 ncycles, totalcycles, timeps, mckperiodps;
|
||||
@@ -1397,9 +1397,9 @@ static int atmel_smc_nand_prepare_smcconf(struct atmel_nand *nand,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
|
||||
static int atmel_smc_nand_setup_interface(struct atmel_nand *nand,
|
||||
int csline,
|
||||
const struct nand_data_interface *conf)
|
||||
const struct nand_interface_config *conf)
|
||||
{
|
||||
struct atmel_nand_controller *nc;
|
||||
struct atmel_smc_cs_conf smcconf;
|
||||
@@ -1422,9 +1422,9 @@ static int atmel_smc_nand_setup_data_interface(struct atmel_nand *nand,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
|
||||
static int atmel_hsmc_nand_setup_interface(struct atmel_nand *nand,
|
||||
int csline,
|
||||
const struct nand_data_interface *conf)
|
||||
const struct nand_interface_config *conf)
|
||||
{
|
||||
struct atmel_hsmc_nand_controller *nc;
|
||||
struct atmel_smc_cs_conf smcconf;
|
||||
@@ -1452,8 +1452,8 @@ static int atmel_hsmc_nand_setup_data_interface(struct atmel_nand *nand,
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int atmel_nand_setup_data_interface(struct nand_chip *chip, int csline,
|
||||
const struct nand_data_interface *conf)
|
||||
static int atmel_nand_setup_interface(struct nand_chip *chip, int csline,
|
||||
const struct nand_interface_config *conf)
|
||||
{
|
||||
struct atmel_nand *nand = to_atmel_nand(chip);
|
||||
struct atmel_nand_controller *nc;
|
||||
@@ -1464,7 +1464,7 @@ static int atmel_nand_setup_data_interface(struct nand_chip *chip, int csline,
|
||||
(csline < 0 && csline != NAND_DATA_IFACE_CHECK_ONLY))
|
||||
return -EINVAL;
|
||||
|
||||
return nc->caps->ops->setup_data_interface(nand, csline, conf);
|
||||
return nc->caps->ops->setup_interface(nand, csline, conf);
|
||||
}
|
||||
|
||||
static void atmel_nand_init(struct atmel_nand_controller *nc,
|
||||
@@ -1483,7 +1483,7 @@ static void atmel_nand_init(struct atmel_nand_controller *nc,
|
||||
chip->legacy.write_buf = atmel_nand_write_buf;
|
||||
chip->legacy.select_chip = atmel_nand_select_chip;
|
||||
|
||||
if (!nc->mck || !nc->caps->ops->setup_data_interface)
|
||||
if (!nc->mck || !nc->caps->ops->setup_interface)
|
||||
chip->options |= NAND_KEEP_TIMINGS;
|
||||
|
||||
/* Some NANDs require a longer delay than the default one (20us). */
|
||||
@@ -1956,7 +1956,7 @@ static int atmel_nand_attach_chip(struct nand_chip *chip)
|
||||
|
||||
static const struct nand_controller_ops atmel_nand_controller_ops = {
|
||||
.attach_chip = atmel_nand_attach_chip,
|
||||
.setup_data_interface = atmel_nand_setup_data_interface,
|
||||
.setup_interface = atmel_nand_setup_interface,
|
||||
};
|
||||
|
||||
static int atmel_nand_controller_init(struct atmel_nand_controller *nc,
|
||||
@@ -2318,7 +2318,7 @@ static const struct atmel_nand_controller_ops atmel_hsmc_nc_ops = {
|
||||
.remove = atmel_hsmc_nand_controller_remove,
|
||||
.ecc_init = atmel_hsmc_nand_ecc_init,
|
||||
.nand_init = atmel_hsmc_nand_init,
|
||||
.setup_data_interface = atmel_hsmc_nand_setup_data_interface,
|
||||
.setup_interface = atmel_hsmc_nand_setup_interface,
|
||||
};
|
||||
|
||||
static const struct atmel_nand_controller_caps atmel_sama5_nc_caps = {
|
||||
@@ -2375,10 +2375,10 @@ atmel_smc_nand_controller_remove(struct atmel_nand_controller *nc)
|
||||
|
||||
/*
|
||||
* The SMC reg layout of at91rm9200 is completely different which prevents us
|
||||
* from re-using atmel_smc_nand_setup_data_interface() for the
|
||||
* ->setup_data_interface() hook.
|
||||
* from re-using atmel_smc_nand_setup_interface() for the
|
||||
* ->setup_interface() hook.
|
||||
* At this point, there's no support for the at91rm9200 SMC IP, so we leave
|
||||
* ->setup_data_interface() unassigned.
|
||||
* ->setup_interface() unassigned.
|
||||
*/
|
||||
static const struct atmel_nand_controller_ops at91rm9200_nc_ops = {
|
||||
.probe = atmel_smc_nand_controller_probe,
|
||||
@@ -2399,7 +2399,7 @@ static const struct atmel_nand_controller_ops atmel_smc_nc_ops = {
|
||||
.remove = atmel_smc_nand_controller_remove,
|
||||
.ecc_init = atmel_nand_ecc_init,
|
||||
.nand_init = atmel_smc_nand_init,
|
||||
.setup_data_interface = atmel_smc_nand_setup_data_interface,
|
||||
.setup_interface = atmel_smc_nand_setup_interface,
|
||||
};
|
||||
|
||||
static const struct atmel_nand_controller_caps atmel_sam9260_nc_caps = {
|
||||
|
||||
@@ -1918,6 +1918,22 @@ static int brcmnand_edu_trans(struct brcmnand_host *host, u64 addr, u32 *buf,
|
||||
edu_writel(ctrl, EDU_STOP, 0); /* force stop */
|
||||
edu_readl(ctrl, EDU_STOP);
|
||||
|
||||
if (!ret && edu_cmd == EDU_CMD_READ) {
|
||||
u64 err_addr = 0;
|
||||
|
||||
/*
|
||||
* check for ECC errors here, subpage ECC errors are
|
||||
* retained in ECC error address register
|
||||
*/
|
||||
err_addr = brcmnand_get_uncorrecc_addr(ctrl);
|
||||
if (!err_addr) {
|
||||
err_addr = brcmnand_get_correcc_addr(ctrl);
|
||||
if (err_addr)
|
||||
ret = -EUCLEAN;
|
||||
} else
|
||||
ret = -EBADMSG;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
@@ -2124,6 +2140,7 @@ static int brcmnand_read(struct mtd_info *mtd, struct nand_chip *chip,
|
||||
u64 err_addr = 0;
|
||||
int err;
|
||||
bool retry = true;
|
||||
bool edu_err = false;
|
||||
|
||||
dev_dbg(ctrl->dev, "read %llx -> %p\n", (unsigned long long)addr, buf);
|
||||
|
||||
@@ -2141,6 +2158,10 @@ try_dmaread:
|
||||
else
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
if (has_edu(ctrl) && err_addr)
|
||||
edu_err = true;
|
||||
|
||||
} else {
|
||||
if (oob)
|
||||
memset(oob, 0x99, mtd->oobsize);
|
||||
@@ -2188,6 +2209,11 @@ try_dmaread:
|
||||
if (mtd_is_bitflip(err)) {
|
||||
unsigned int corrected = brcmnand_count_corrected(ctrl);
|
||||
|
||||
/* in case of EDU correctable error we read again using PIO */
|
||||
if (edu_err)
|
||||
err = brcmnand_read_by_pio(mtd, chip, addr, trans, buf,
|
||||
oob, &err_addr);
|
||||
|
||||
dev_dbg(ctrl->dev, "corrected error at 0x%llx\n",
|
||||
(unsigned long long)err_addr);
|
||||
mtd->ecc_stats.corrected += corrected;
|
||||
@@ -3023,8 +3049,9 @@ int brcmnand_probe(struct platform_device *pdev, struct brcmnand_soc *soc)
|
||||
if (ret < 0)
|
||||
goto err;
|
||||
|
||||
/* set edu transfer function to call */
|
||||
ctrl->dma_trans = brcmnand_edu_trans;
|
||||
if (has_edu(ctrl))
|
||||
/* set edu transfer function to call */
|
||||
ctrl->dma_trans = brcmnand_edu_trans;
|
||||
}
|
||||
|
||||
/* Disable automatic device ID config, direct addressing */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user