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drm/amd/display: Add more DC HW state info to underflow logging

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[Why]
Debugging underflow issues frequently requires knowing the
HW state at the time of underflow. To enable capturing this
HW state information, interface functions are needed for the
various DC HW blocks.

[How]
This change adds the interface functions to read HW state for
the following DC HW blocks:
- HUBBUB
- HUBP
- DPP
- MPC
- OPP
- DSC
- OPTC
- DCCG

Reviewed-by: George Shen <george.shen@amd.com>
Signed-off-by: Karen Chen <Karen.Chen@amd.com>
Signed-off-by: Wayne Lin <wayne.lin@amd.com>
Tested-by: Dan Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Karen Chen
2025-10-28 09:57:44 -04:00
committed by Alex Deucher
parent e6a8a000cf
commit dbf58a9dad
59 changed files with 1129 additions and 146 deletions
Download Patch File Download Diff File Expand all files Collapse all files
drivers/gpu/drm/amd/display/dc/dc.h
+16 -14
View File
@@ -54,6 +54,14 @@ struct abm_save_restore;
struct aux_payload;
struct set_config_cmd_payload;
struct dmub_notification;
struct dcn_hubbub_reg_state;
struct dcn_hubp_reg_state;
struct dcn_dpp_reg_state;
struct dcn_mpc_reg_state;
struct dcn_opp_reg_state;
struct dcn_dsc_reg_state;
struct dcn_optc_reg_state;
struct dcn_dccg_reg_state;
#define DC_VER "3.2.355"
@@ -1831,20 +1839,14 @@ struct dc_surface_update {
};
struct dc_underflow_debug_data {
uint32_t otg_inst;
uint32_t otg_underflow;
uint32_t h_position;
uint32_t v_position;
uint32_t otg_frame_count;
struct dc_underflow_per_hubp_debug_data {
uint32_t hubp_underflow;
uint32_t hubp_in_blank;
uint32_t hubp_readline;
uint32_t det_config_error;
} hubps[MAX_PIPES];
uint32_t curr_det_sizes[MAX_PIPES];
uint32_t target_det_sizes[MAX_PIPES];
uint32_t compbuf_config_error;
struct dcn_hubbub_reg_state *hubbub_reg_state;
struct dcn_hubp_reg_state *hubp_reg_state[MAX_PIPES];
struct dcn_dpp_reg_state *dpp_reg_state[MAX_PIPES];
struct dcn_mpc_reg_state *mpc_reg_state[MAX_PIPES];
struct dcn_opp_reg_state *opp_reg_state[MAX_PIPES];
struct dcn_dsc_reg_state *dsc_reg_state[MAX_PIPES];
struct dcn_optc_reg_state *optc_reg_state[MAX_PIPES];
struct dcn_dccg_reg_state *dccg_reg_state[MAX_PIPES];
};
/*
drivers/gpu/drm/amd/display/dc/dccg/dcn20/dcn20_dccg.h
+63 -1
View File
@@ -425,7 +425,69 @@ struct dccg_mask {
uint32_t SYMCLKD_CLOCK_ENABLE; \
uint32_t SYMCLKE_CLOCK_ENABLE; \
uint32_t DP_DTO_MODULO[MAX_PIPES]; \
uint32_t DP_DTO_PHASE[MAX_PIPES]
uint32_t DP_DTO_PHASE[MAX_PIPES]; \
uint32_t DC_MEM_GLOBAL_PWR_REQ_CNTL; \
uint32_t DCCG_AUDIO_DTO0_MODULE; \
uint32_t DCCG_AUDIO_DTO0_PHASE; \
uint32_t DCCG_AUDIO_DTO1_MODULE; \
uint32_t DCCG_AUDIO_DTO1_PHASE; \
uint32_t DCCG_CAC_STATUS; \
uint32_t DCCG_CAC_STATUS2; \
uint32_t DCCG_DISP_CNTL_REG; \
uint32_t DCCG_DS_CNTL; \
uint32_t DCCG_DS_DTO_INCR; \
uint32_t DCCG_DS_DTO_MODULO; \
uint32_t DCCG_DS_HW_CAL_INTERVAL; \
uint32_t DCCG_GTC_CNTL; \
uint32_t DCCG_GTC_CURRENT; \
uint32_t DCCG_GTC_DTO_INCR; \
uint32_t DCCG_GTC_DTO_MODULO; \
uint32_t DCCG_PERFMON_CNTL; \
uint32_t DCCG_PERFMON_CNTL2; \
uint32_t DCCG_SOFT_RESET; \
uint32_t DCCG_TEST_CLK_SEL; \
uint32_t DCCG_VSYNC_CNT_CTRL; \
uint32_t DCCG_VSYNC_CNT_INT_CTRL; \
uint32_t DCCG_VSYNC_OTG0_LATCH_VALUE; \
uint32_t DCCG_VSYNC_OTG1_LATCH_VALUE; \
uint32_t DCCG_VSYNC_OTG2_LATCH_VALUE; \
uint32_t DCCG_VSYNC_OTG3_LATCH_VALUE; \
uint32_t DCCG_VSYNC_OTG4_LATCH_VALUE; \
uint32_t DCCG_VSYNC_OTG5_LATCH_VALUE; \
uint32_t DISPCLK_CGTT_BLK_CTRL_REG; \
uint32_t DP_DTO_DBUF_EN; \
uint32_t DPIACLK_540M_DTO_MODULO; \
uint32_t DPIACLK_540M_DTO_PHASE; \
uint32_t DPIACLK_810M_DTO_MODULO; \
uint32_t DPIACLK_810M_DTO_PHASE; \
uint32_t DPIACLK_DTO_CNTL; \
uint32_t DPIASYMCLK_CNTL; \
uint32_t DPPCLK_CGTT_BLK_CTRL_REG; \
uint32_t DPREFCLK_CGTT_BLK_CTRL_REG; \
uint32_t DPREFCLK_CNTL; \
uint32_t DTBCLK_DTO_DBUF_EN; \
uint32_t FORCE_SYMCLK_DISABLE; \
uint32_t HDMICHARCLK0_CLOCK_CNTL; \
uint32_t MICROSECOND_TIME_BASE_DIV; \
uint32_t MILLISECOND_TIME_BASE_DIV; \
uint32_t OTG0_PHYPLL_PIXEL_RATE_CNTL; \
uint32_t OTG0_PIXEL_RATE_CNTL; \
uint32_t OTG1_PHYPLL_PIXEL_RATE_CNTL; \
uint32_t OTG1_PIXEL_RATE_CNTL; \
uint32_t OTG2_PHYPLL_PIXEL_RATE_CNTL; \
uint32_t OTG2_PIXEL_RATE_CNTL; \
uint32_t OTG3_PHYPLL_PIXEL_RATE_CNTL; \
uint32_t OTG3_PIXEL_RATE_CNTL; \
uint32_t PHYPLLA_PIXCLK_RESYNC_CNTL; \
uint32_t PHYPLLB_PIXCLK_RESYNC_CNTL; \
uint32_t PHYPLLC_PIXCLK_RESYNC_CNTL; \
uint32_t PHYPLLD_PIXCLK_RESYNC_CNTL; \
uint32_t PHYPLLE_PIXCLK_RESYNC_CNTL; \
uint32_t REFCLK_CGTT_BLK_CTRL_REG; \
uint32_t SOCCLK_CGTT_BLK_CTRL_REG; \
uint32_t SYMCLK_CGTT_BLK_CTRL_REG; \
uint32_t SYMCLK_PSP_CNTL
struct dccg_registers {
DCCG_REG_VARIABLE_LIST;
};
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.c
+123
View File
@@ -709,6 +709,128 @@ void dccg31_otg_drop_pixel(struct dccg *dccg,
OTG_DROP_PIXEL[otg_inst], 1);
}
void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state)
{
struct dcn_dccg *dccg_dcn = TO_DCN_DCCG(dccg);
dccg_reg_state->dc_mem_global_pwr_req_cntl = REG_READ(DC_MEM_GLOBAL_PWR_REQ_CNTL);
dccg_reg_state->dccg_audio_dtbclk_dto_modulo = REG_READ(DCCG_AUDIO_DTBCLK_DTO_MODULO);
dccg_reg_state->dccg_audio_dtbclk_dto_phase = REG_READ(DCCG_AUDIO_DTBCLK_DTO_PHASE);
dccg_reg_state->dccg_audio_dto_source = REG_READ(DCCG_AUDIO_DTO_SOURCE);
dccg_reg_state->dccg_audio_dto0_module = REG_READ(DCCG_AUDIO_DTO0_MODULE);
dccg_reg_state->dccg_audio_dto0_phase = REG_READ(DCCG_AUDIO_DTO0_PHASE);
dccg_reg_state->dccg_audio_dto1_module = REG_READ(DCCG_AUDIO_DTO1_MODULE);
dccg_reg_state->dccg_audio_dto1_phase = REG_READ(DCCG_AUDIO_DTO1_PHASE);
dccg_reg_state->dccg_cac_status = REG_READ(DCCG_CAC_STATUS);
dccg_reg_state->dccg_cac_status2 = REG_READ(DCCG_CAC_STATUS2);
dccg_reg_state->dccg_disp_cntl_reg = REG_READ(DCCG_DISP_CNTL_REG);
dccg_reg_state->dccg_ds_cntl = REG_READ(DCCG_DS_CNTL);
dccg_reg_state->dccg_ds_dto_incr = REG_READ(DCCG_DS_DTO_INCR);
dccg_reg_state->dccg_ds_dto_modulo = REG_READ(DCCG_DS_DTO_MODULO);
dccg_reg_state->dccg_ds_hw_cal_interval = REG_READ(DCCG_DS_HW_CAL_INTERVAL);
dccg_reg_state->dccg_gate_disable_cntl = REG_READ(DCCG_GATE_DISABLE_CNTL);
dccg_reg_state->dccg_gate_disable_cntl2 = REG_READ(DCCG_GATE_DISABLE_CNTL2);
dccg_reg_state->dccg_gate_disable_cntl3 = REG_READ(DCCG_GATE_DISABLE_CNTL3);
dccg_reg_state->dccg_gate_disable_cntl4 = REG_READ(DCCG_GATE_DISABLE_CNTL4);
dccg_reg_state->dccg_gate_disable_cntl5 = REG_READ(DCCG_GATE_DISABLE_CNTL5);
dccg_reg_state->dccg_gate_disable_cntl6 = REG_READ(DCCG_GATE_DISABLE_CNTL6);
dccg_reg_state->dccg_global_fgcg_rep_cntl = REG_READ(DCCG_GLOBAL_FGCG_REP_CNTL);
dccg_reg_state->dccg_gtc_cntl = REG_READ(DCCG_GTC_CNTL);
dccg_reg_state->dccg_gtc_current = REG_READ(DCCG_GTC_CURRENT);
dccg_reg_state->dccg_gtc_dto_incr = REG_READ(DCCG_GTC_DTO_INCR);
dccg_reg_state->dccg_gtc_dto_modulo = REG_READ(DCCG_GTC_DTO_MODULO);
dccg_reg_state->dccg_perfmon_cntl = REG_READ(DCCG_PERFMON_CNTL);
dccg_reg_state->dccg_perfmon_cntl2 = REG_READ(DCCG_PERFMON_CNTL2);
dccg_reg_state->dccg_soft_reset = REG_READ(DCCG_SOFT_RESET);
dccg_reg_state->dccg_test_clk_sel = REG_READ(DCCG_TEST_CLK_SEL);
dccg_reg_state->dccg_vsync_cnt_ctrl = REG_READ(DCCG_VSYNC_CNT_CTRL);
dccg_reg_state->dccg_vsync_cnt_int_ctrl = REG_READ(DCCG_VSYNC_CNT_INT_CTRL);
dccg_reg_state->dccg_vsync_otg0_latch_value = REG_READ(DCCG_VSYNC_OTG0_LATCH_VALUE);
dccg_reg_state->dccg_vsync_otg1_latch_value = REG_READ(DCCG_VSYNC_OTG1_LATCH_VALUE);
dccg_reg_state->dccg_vsync_otg2_latch_value = REG_READ(DCCG_VSYNC_OTG2_LATCH_VALUE);
dccg_reg_state->dccg_vsync_otg3_latch_value = REG_READ(DCCG_VSYNC_OTG3_LATCH_VALUE);
dccg_reg_state->dccg_vsync_otg4_latch_value = REG_READ(DCCG_VSYNC_OTG4_LATCH_VALUE);
dccg_reg_state->dccg_vsync_otg5_latch_value = REG_READ(DCCG_VSYNC_OTG5_LATCH_VALUE);
dccg_reg_state->dispclk_cgtt_blk_ctrl_reg = REG_READ(DISPCLK_CGTT_BLK_CTRL_REG);
dccg_reg_state->dispclk_freq_change_cntl = REG_READ(DISPCLK_FREQ_CHANGE_CNTL);
dccg_reg_state->dp_dto_dbuf_en = REG_READ(DP_DTO_DBUF_EN);
dccg_reg_state->dp_dto0_modulo = REG_READ(DP_DTO_MODULO[0]);
dccg_reg_state->dp_dto0_phase = REG_READ(DP_DTO_PHASE[0]);
dccg_reg_state->dp_dto1_modulo = REG_READ(DP_DTO_MODULO[1]);
dccg_reg_state->dp_dto1_phase = REG_READ(DP_DTO_PHASE[1]);
dccg_reg_state->dp_dto2_modulo = REG_READ(DP_DTO_MODULO[2]);
dccg_reg_state->dp_dto2_phase = REG_READ(DP_DTO_PHASE[2]);
dccg_reg_state->dp_dto3_modulo = REG_READ(DP_DTO_MODULO[3]);
dccg_reg_state->dp_dto3_phase = REG_READ(DP_DTO_PHASE[3]);
dccg_reg_state->dpiaclk_540m_dto_modulo = REG_READ(DPIACLK_540M_DTO_MODULO);
dccg_reg_state->dpiaclk_540m_dto_phase = REG_READ(DPIACLK_540M_DTO_PHASE);
dccg_reg_state->dpiaclk_810m_dto_modulo = REG_READ(DPIACLK_810M_DTO_MODULO);
dccg_reg_state->dpiaclk_810m_dto_phase = REG_READ(DPIACLK_810M_DTO_PHASE);
dccg_reg_state->dpiaclk_dto_cntl = REG_READ(DPIACLK_DTO_CNTL);
dccg_reg_state->dpiasymclk_cntl = REG_READ(DPIASYMCLK_CNTL);
dccg_reg_state->dppclk_cgtt_blk_ctrl_reg = REG_READ(DPPCLK_CGTT_BLK_CTRL_REG);
dccg_reg_state->dppclk_ctrl = REG_READ(DPPCLK_CTRL);
dccg_reg_state->dppclk_dto_ctrl = REG_READ(DPPCLK_DTO_CTRL);
dccg_reg_state->dppclk0_dto_param = REG_READ(DPPCLK_DTO_PARAM[0]);
dccg_reg_state->dppclk1_dto_param = REG_READ(DPPCLK_DTO_PARAM[1]);
dccg_reg_state->dppclk2_dto_param = REG_READ(DPPCLK_DTO_PARAM[2]);
dccg_reg_state->dppclk3_dto_param = REG_READ(DPPCLK_DTO_PARAM[3]);
dccg_reg_state->dprefclk_cgtt_blk_ctrl_reg = REG_READ(DPREFCLK_CGTT_BLK_CTRL_REG);
dccg_reg_state->dprefclk_cntl = REG_READ(DPREFCLK_CNTL);
dccg_reg_state->dpstreamclk_cntl = REG_READ(DPSTREAMCLK_CNTL);
dccg_reg_state->dscclk_dto_ctrl = REG_READ(DSCCLK_DTO_CTRL);
dccg_reg_state->dscclk0_dto_param = REG_READ(DSCCLK0_DTO_PARAM);
dccg_reg_state->dscclk1_dto_param = REG_READ(DSCCLK1_DTO_PARAM);
dccg_reg_state->dscclk2_dto_param = REG_READ(DSCCLK2_DTO_PARAM);
dccg_reg_state->dscclk3_dto_param = REG_READ(DSCCLK3_DTO_PARAM);
dccg_reg_state->dtbclk_dto_dbuf_en = REG_READ(DTBCLK_DTO_DBUF_EN);
dccg_reg_state->dtbclk_dto0_modulo = REG_READ(DTBCLK_DTO_MODULO[0]);
dccg_reg_state->dtbclk_dto0_phase = REG_READ(DTBCLK_DTO_PHASE[0]);
dccg_reg_state->dtbclk_dto1_modulo = REG_READ(DTBCLK_DTO_MODULO[1]);
dccg_reg_state->dtbclk_dto1_phase = REG_READ(DTBCLK_DTO_PHASE[1]);
dccg_reg_state->dtbclk_dto2_modulo = REG_READ(DTBCLK_DTO_MODULO[2]);
dccg_reg_state->dtbclk_dto2_phase = REG_READ(DTBCLK_DTO_PHASE[2]);
dccg_reg_state->dtbclk_dto3_modulo = REG_READ(DTBCLK_DTO_MODULO[3]);
dccg_reg_state->dtbclk_dto3_phase = REG_READ(DTBCLK_DTO_PHASE[3]);
dccg_reg_state->dtbclk_p_cntl = REG_READ(DTBCLK_P_CNTL);
dccg_reg_state->force_symclk_disable = REG_READ(FORCE_SYMCLK_DISABLE);
dccg_reg_state->hdmicharclk0_clock_cntl = REG_READ(HDMICHARCLK0_CLOCK_CNTL);
dccg_reg_state->hdmistreamclk_cntl = REG_READ(HDMISTREAMCLK_CNTL);
dccg_reg_state->hdmistreamclk0_dto_param = REG_READ(HDMISTREAMCLK0_DTO_PARAM);
dccg_reg_state->microsecond_time_base_div = REG_READ(MICROSECOND_TIME_BASE_DIV);
dccg_reg_state->millisecond_time_base_div = REG_READ(MILLISECOND_TIME_BASE_DIV);
dccg_reg_state->otg_pixel_rate_div = REG_READ(OTG_PIXEL_RATE_DIV);
dccg_reg_state->otg0_phypll_pixel_rate_cntl = REG_READ(OTG0_PHYPLL_PIXEL_RATE_CNTL);
dccg_reg_state->otg0_pixel_rate_cntl = REG_READ(OTG0_PIXEL_RATE_CNTL);
dccg_reg_state->otg1_phypll_pixel_rate_cntl = REG_READ(OTG1_PHYPLL_PIXEL_RATE_CNTL);
dccg_reg_state->otg1_pixel_rate_cntl = REG_READ(OTG1_PIXEL_RATE_CNTL);
dccg_reg_state->otg2_phypll_pixel_rate_cntl = REG_READ(OTG2_PHYPLL_PIXEL_RATE_CNTL);
dccg_reg_state->otg2_pixel_rate_cntl = REG_READ(OTG2_PIXEL_RATE_CNTL);
dccg_reg_state->otg3_phypll_pixel_rate_cntl = REG_READ(OTG3_PHYPLL_PIXEL_RATE_CNTL);
dccg_reg_state->otg3_pixel_rate_cntl = REG_READ(OTG3_PIXEL_RATE_CNTL);
dccg_reg_state->phyasymclk_clock_cntl = REG_READ(PHYASYMCLK_CLOCK_CNTL);
dccg_reg_state->phybsymclk_clock_cntl = REG_READ(PHYBSYMCLK_CLOCK_CNTL);
dccg_reg_state->phycsymclk_clock_cntl = REG_READ(PHYCSYMCLK_CLOCK_CNTL);
dccg_reg_state->phydsymclk_clock_cntl = REG_READ(PHYDSYMCLK_CLOCK_CNTL);
dccg_reg_state->phyesymclk_clock_cntl = REG_READ(PHYESYMCLK_CLOCK_CNTL);
dccg_reg_state->phyplla_pixclk_resync_cntl = REG_READ(PHYPLLA_PIXCLK_RESYNC_CNTL);
dccg_reg_state->phypllb_pixclk_resync_cntl = REG_READ(PHYPLLB_PIXCLK_RESYNC_CNTL);
dccg_reg_state->phypllc_pixclk_resync_cntl = REG_READ(PHYPLLC_PIXCLK_RESYNC_CNTL);
dccg_reg_state->phyplld_pixclk_resync_cntl = REG_READ(PHYPLLD_PIXCLK_RESYNC_CNTL);
dccg_reg_state->phyplle_pixclk_resync_cntl = REG_READ(PHYPLLE_PIXCLK_RESYNC_CNTL);
dccg_reg_state->refclk_cgtt_blk_ctrl_reg = REG_READ(REFCLK_CGTT_BLK_CTRL_REG);
dccg_reg_state->socclk_cgtt_blk_ctrl_reg = REG_READ(SOCCLK_CGTT_BLK_CTRL_REG);
dccg_reg_state->symclk_cgtt_blk_ctrl_reg = REG_READ(SYMCLK_CGTT_BLK_CTRL_REG);
dccg_reg_state->symclk_psp_cntl = REG_READ(SYMCLK_PSP_CNTL);
dccg_reg_state->symclk32_le_cntl = REG_READ(SYMCLK32_LE_CNTL);
dccg_reg_state->symclk32_se_cntl = REG_READ(SYMCLK32_SE_CNTL);
dccg_reg_state->symclka_clock_enable = REG_READ(SYMCLKA_CLOCK_ENABLE);
dccg_reg_state->symclkb_clock_enable = REG_READ(SYMCLKB_CLOCK_ENABLE);
dccg_reg_state->symclkc_clock_enable = REG_READ(SYMCLKC_CLOCK_ENABLE);
dccg_reg_state->symclkd_clock_enable = REG_READ(SYMCLKD_CLOCK_ENABLE);
dccg_reg_state->symclke_clock_enable = REG_READ(SYMCLKE_CLOCK_ENABLE);
}
static const struct dccg_funcs dccg31_funcs = {
.update_dpp_dto = dccg31_update_dpp_dto,
.get_dccg_ref_freq = dccg31_get_dccg_ref_freq,
@@ -727,6 +849,7 @@ static const struct dccg_funcs dccg31_funcs = {
.set_dispclk_change_mode = dccg31_set_dispclk_change_mode,
.disable_dsc = dccg31_disable_dscclk,
.enable_dsc = dccg31_enable_dscclk,
.dccg_read_reg_state = dccg31_read_reg_state,
};
struct dccg *dccg31_create(
drivers/gpu/drm/amd/display/dc/dccg/dcn31/dcn31_dccg.h
+2
View File
@@ -236,4 +236,6 @@ void dccg31_disable_dscclk(struct dccg *dccg, int inst);
void dccg31_enable_dscclk(struct dccg *dccg, int inst);
void dccg31_read_reg_state(struct dccg *dccg, struct dcn_dccg_reg_state *dccg_reg_state);
#endif //__DCN31_DCCG_H__
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.c
+2 -1
View File
@@ -377,7 +377,8 @@ static const struct dccg_funcs dccg314_funcs = {
.get_pixel_rate_div = dccg314_get_pixel_rate_div,
.trigger_dio_fifo_resync = dccg314_trigger_dio_fifo_resync,
.set_valid_pixel_rate = dccg314_set_valid_pixel_rate,
.set_dtbclk_p_src = dccg314_set_dtbclk_p_src
.set_dtbclk_p_src = dccg314_set_dtbclk_p_src,
.dccg_read_reg_state = dccg31_read_reg_state
};
struct dccg *dccg314_create(
drivers/gpu/drm/amd/display/dc/dccg/dcn314/dcn314_dccg.h
+1 -2
View File
@@ -74,8 +74,7 @@
SR(DCCG_GATE_DISABLE_CNTL3),\
SR(HDMISTREAMCLK0_DTO_PARAM),\
SR(OTG_PIXEL_RATE_DIV),\
SR(DTBCLK_P_CNTL),\
SR(DCCG_AUDIO_DTO_SOURCE)
SR(DTBCLK_P_CNTL)
#define DCCG_MASK_SH_LIST_DCN314_COMMON(mask_sh) \
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.c
+1
View File
@@ -2453,6 +2453,7 @@ static const struct dccg_funcs dccg35_funcs = {
.disable_symclk_se = dccg35_disable_symclk_se,
.set_dtbclk_p_src = dccg35_set_dtbclk_p_src,
.dccg_root_gate_disable_control = dccg35_root_gate_disable_control,
.dccg_read_reg_state = dccg31_read_reg_state,
};
struct dccg *dccg35_create(
drivers/gpu/drm/amd/display/dc/dccg/dcn35/dcn35_dccg.h
+3 -2
View File
@@ -41,8 +41,9 @@
SR(SYMCLKA_CLOCK_ENABLE),\
SR(SYMCLKB_CLOCK_ENABLE),\
SR(SYMCLKC_CLOCK_ENABLE),\
SR(SYMCLKD_CLOCK_ENABLE),\
SR(SYMCLKE_CLOCK_ENABLE)
SR(SYMCLKD_CLOCK_ENABLE), \
SR(SYMCLKE_CLOCK_ENABLE),\
SR(SYMCLK_PSP_CNTL)
#define DCCG_MASK_SH_LIST_DCN35(mask_sh) \
DCCG_SFI(DPPCLK_DTO_CTRL, DTO_DB_EN, DPPCLK, 0, mask_sh),\
drivers/gpu/drm/amd/display/dc/dccg/dcn401/dcn401_dccg.c
+1
View File
@@ -886,6 +886,7 @@ static const struct dccg_funcs dccg401_funcs = {
.enable_symclk_se = dccg401_enable_symclk_se,
.disable_symclk_se = dccg401_disable_symclk_se,
.set_dtbclk_p_src = dccg401_set_dtbclk_p_src,
.dccg_read_reg_state = dccg31_read_reg_state
};
struct dccg *dccg401_create(
drivers/gpu/drm/amd/display/dc/dpp/dcn10/dcn10_dpp.h
+2 -2
View File
@@ -1348,7 +1348,8 @@ struct dcn_dpp_mask {
uint32_t CURSOR0_COLOR1; \
uint32_t DPP_CONTROL; \
uint32_t CM_HDR_MULT_COEF; \
uint32_t CURSOR0_FP_SCALE_BIAS;
uint32_t CURSOR0_FP_SCALE_BIAS; \
uint32_t OBUF_CONTROL;
struct dcn_dpp_registers {
DPP_COMMON_REG_VARIABLE_LIST
@@ -1450,7 +1451,6 @@ void dpp1_set_degamma(
void dpp1_set_degamma_pwl(struct dpp *dpp_base,
const struct pwl_params *params);
void dpp_read_state(struct dpp *dpp_base,
struct dcn_dpp_state *s);
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.c
+16
View File
@@ -84,6 +84,22 @@ void dpp30_read_state(struct dpp *dpp_base, struct dcn_dpp_state *s)
}
}
void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state)
{
struct dcn3_dpp *dpp = TO_DCN30_DPP(dpp_base);
dpp_reg_state->recout_start = REG_READ(RECOUT_START);
dpp_reg_state->recout_size = REG_READ(RECOUT_SIZE);
dpp_reg_state->scl_horz_filter_scale_ratio = REG_READ(SCL_HORZ_FILTER_SCALE_RATIO);
dpp_reg_state->scl_vert_filter_scale_ratio = REG_READ(SCL_VERT_FILTER_SCALE_RATIO);
dpp_reg_state->scl_mode = REG_READ(SCL_MODE);
dpp_reg_state->cm_control = REG_READ(CM_CONTROL);
dpp_reg_state->dpp_control = REG_READ(DPP_CONTROL);
dpp_reg_state->dscl_control = REG_READ(DSCL_CONTROL);
dpp_reg_state->obuf_control = REG_READ(OBUF_CONTROL);
dpp_reg_state->mpc_size = REG_READ(MPC_SIZE);
}
/*program post scaler scs block in dpp CM*/
void dpp3_program_post_csc(
struct dpp *dpp_base,
drivers/gpu/drm/amd/display/dc/dpp/dcn30/dcn30_dpp.h
+2
View File
@@ -594,6 +594,8 @@ void dpp3_program_CM_dealpha(
void dpp30_read_state(struct dpp *dpp_base,
struct dcn_dpp_state *s);
void dpp30_read_reg_state(struct dpp *dpp_base, struct dcn_dpp_reg_state *dpp_reg_state);
bool dpp3_get_optimal_number_of_taps(
struct dpp *dpp,
struct scaler_data *scl_data,
drivers/gpu/drm/amd/display/dc/dpp/dcn32/dcn32_dpp.c
+1
View File
@@ -134,6 +134,7 @@ static struct dpp_funcs dcn32_dpp_funcs = {
.dpp_dppclk_control = dpp1_dppclk_control,
.dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
.dpp_get_gamut_remap = dpp3_cm_get_gamut_remap,
.dpp_read_reg_state = dpp30_read_reg_state,
};
drivers/gpu/drm/amd/display/dc/dpp/dcn35/dcn35_dpp.c
+1
View File
@@ -95,6 +95,7 @@ void dpp35_program_bias_and_scale_fcnv(
static struct dpp_funcs dcn35_dpp_funcs = {
.dpp_program_gamcor_lut = dpp3_program_gamcor_lut,
.dpp_read_state = dpp30_read_state,
.dpp_read_reg_state = dpp30_read_reg_state,
.dpp_reset = dpp_reset,
.dpp_set_scaler = dpp1_dscl_set_scaler_manual_scale,
.dpp_get_optimal_number_of_taps = dpp3_get_optimal_number_of_taps,
drivers/gpu/drm/amd/display/dc/dpp/dcn401/dcn401_dpp.c
+1
View File
@@ -248,6 +248,7 @@ static struct dpp_funcs dcn401_dpp_funcs = {
.set_optional_cursor_attributes = dpp401_set_optional_cursor_attributes,
.dpp_dppclk_control = dpp1_dppclk_control,
.dpp_set_hdr_multiplier = dpp3_set_hdr_multiplier,
.dpp_read_reg_state = dpp30_read_reg_state,
.set_cursor_matrix = dpp401_set_cursor_matrix,
};
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.c
+8
View File
@@ -35,6 +35,7 @@ static void dsc_write_to_registers(struct display_stream_compressor *dsc, const
static const struct dsc_funcs dcn20_dsc_funcs = {
.dsc_get_enc_caps = dsc2_get_enc_caps,
.dsc_read_state = dsc2_read_state,
.dsc_read_reg_state = dsc2_read_reg_state,
.dsc_validate_stream = dsc2_validate_stream,
.dsc_set_config = dsc2_set_config,
.dsc_get_packed_pps = dsc2_get_packed_pps,
@@ -155,6 +156,13 @@ void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state
DSCRM_DSC_OPP_PIPE_SOURCE, &s->dsc_opp_source);
}
void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state)
{
struct dcn20_dsc *dsc20 = TO_DCN20_DSC(dsc);
dccg_reg_state->dsc_top_control = REG_READ(DSC_TOP_CONTROL);
dccg_reg_state->dscc_interrupt_control_status = REG_READ(DSCC_INTERRUPT_CONTROL_STATUS);
}
bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg)
{
drivers/gpu/drm/amd/display/dc/dsc/dcn20/dcn20_dsc.h
+1
View File
@@ -606,6 +606,7 @@ bool dsc2_get_packed_pps(struct display_stream_compressor *dsc,
uint8_t *dsc_packed_pps);
void dsc2_read_state(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
void dsc2_read_reg_state(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state);
bool dsc2_validate_stream(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
void dsc2_set_config(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
struct dsc_optc_config *dsc_optc_cfg);
drivers/gpu/drm/amd/display/dc/dsc/dcn35/dcn35_dsc.c
+1
View File
@@ -32,6 +32,7 @@ static void dsc35_enable(struct display_stream_compressor *dsc, int opp_pipe);
static const struct dsc_funcs dcn35_dsc_funcs = {
.dsc_get_enc_caps = dsc2_get_enc_caps,
.dsc_read_state = dsc2_read_state,
.dsc_read_reg_state = dsc2_read_reg_state,
.dsc_validate_stream = dsc2_validate_stream,
.dsc_set_config = dsc2_set_config,
.dsc_get_packed_pps = dsc2_get_packed_pps,
drivers/gpu/drm/amd/display/dc/dsc/dcn401/dcn401_dsc.c
+1
View File
@@ -26,6 +26,7 @@ static const struct dsc_funcs dcn401_dsc_funcs = {
.dsc_disconnect = dsc401_disconnect,
.dsc_wait_disconnect_pending_clear = dsc401_wait_disconnect_pending_clear,
.dsc_get_single_enc_caps = dsc401_get_single_enc_caps,
.dsc_read_reg_state = dsc2_read_reg_state
};
/* Macro definitios for REG_SET macros*/
drivers/gpu/drm/amd/display/dc/dsc/dsc.h
+5
View File
@@ -66,6 +66,10 @@ struct dcn_dsc_state {
uint32_t dsc_opp_source;
};
struct dcn_dsc_reg_state {
uint32_t dsc_top_control;
uint32_t dscc_interrupt_control_status;
};
/* DSC encoder capabilities
* They differ from the DPCD DSC caps because they are based on AMD DSC encoder caps.
@@ -100,6 +104,7 @@ struct dsc_enc_caps {
struct dsc_funcs {
void (*dsc_get_enc_caps)(struct dsc_enc_caps *dsc_enc_caps, int pixel_clock_100Hz);
void (*dsc_read_state)(struct display_stream_compressor *dsc, struct dcn_dsc_state *s);
void (*dsc_read_reg_state)(struct display_stream_compressor *dsc, struct dcn_dsc_reg_state *dccg_reg_state);
bool (*dsc_validate_stream)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg);
void (*dsc_set_config)(struct display_stream_compressor *dsc, const struct dsc_config *dsc_cfg,
struct dsc_optc_config *dsc_optc_cfg);

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