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Merge tag 'media/v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media

Browse Source 
Pull media updates from Mauro Carvalho Chehab:

 - New drivers:
    - Mali-C55 ISP
    - Rockchip VICAP (RKCIF)
    - RKVDEC HEVC Decoder
    - Renesas RZV2H IVC
    - Sony IMX111 CMOS sensor driver

 - Removed STi C8SECTPFE Driver

 - Added a V4L2 ISP generic framework

 - Usual set of cleanup, fixes and driver improvements

* tag 'media/v6.19-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mchehab/linux-media: (249 commits)
  media: rockchip: rkcif: add support for rk3568 vicap mipi capture
  media: rockchip: rkcif: add support for rk3568 vicap dvp capture
  media: rockchip: rkcif: add support for px30 vip dvp capture
  media: rockchip: rkcif: add abstraction for dma blocks
  media: rockchip: rkcif: add abstraction for interface and crop blocks
  media: rockchip: add driver for the rockchip camera interface
  media: dt-bindings: add rockchip rk3568 vicap
  media: dt-bindings: add rockchip px30 vip
  media: dt-bindings: video-interfaces: add defines for sampling modes
  Documentation: admin-guide: media: add rockchip camera interface
  media: mali-c55: Mark pm handlers as __maybe_unused
  media: mali-c55: Assert ISP blocks size correctness
  media: v4l2-isp: Rename block_info to block_type_info
  MAINTAINERS: Add entry for rzv2h-ivc driver
  media: platform: Add Renesas Input Video Control block driver
  dt-bindings: media: Add bindings for the RZ/V2H(P) IVC block
  Documentation: media: mali-c55: Document the mali-c55 parameter setting
  media: platform: Add mali-c55 parameters video node
  media: uapi: Add parameters structs to mali-c55-config.h
  media: mali-c55: Add image formats for Mali-C55 parameters buffer
  ...
This commit is contained in:
Linus Torvalds
2025-12-04 08:15:19 -08:00
parent 559e608c46 1f2353f5a1
commit d7aa60d966
310 changed files with 22135 additions and 4828 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/admin-guide/media/mali-c55-graph.dot
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digraph board {
rankdir=TB
n00000001 [label="{{} | mali-c55 tpg\n/dev/v4l-subdev0 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green]
n00000001:port0 -> n00000003:port0 [style=dashed]
n00000003 [label="{{<port0> 0} | mali-c55 isp\n/dev/v4l-subdev1 | {<port1> 1 | <port2> 2}}", shape=Mrecord, style=filled, fillcolor=green]
n00000003:port1 -> n00000007:port0 [style=bold]
n00000003:port2 -> n00000007:port2 [style=bold]
n00000003:port1 -> n0000000b:port0 [style=bold]
n00000007 [label="{{<port0> 0 | <port2> 2} | mali-c55 resizer fr\n/dev/v4l-subdev2 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
n00000007:port1 -> n0000000e [style=bold]
n0000000b [label="{{<port0> 0} | mali-c55 resizer ds\n/dev/v4l-subdev3 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
n0000000b:port1 -> n00000012 [style=bold]
n0000000e [label="mali-c55 fr\n/dev/video0", shape=box, style=filled, fillcolor=yellow]
n00000012 [label="mali-c55 ds\n/dev/video1", shape=box, style=filled, fillcolor=yellow]
n00000022 [label="{{<port0> 0} | csi2-rx\n/dev/v4l-subdev4 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
n00000022:port1 -> n00000003:port0
n00000027 [label="{{} | imx415 1-001a\n/dev/v4l-subdev5 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green]
n00000027:port0 -> n00000022:port0 [style=bold]
}
Documentation/admin-guide/media/mali-c55.rst
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@@ -0,0 +1,413 @@
.. SPDX-License-Identifier: GPL-2.0
==========================================
ARM Mali-C55 Image Signal Processor driver
==========================================
Introduction
============
This file documents the driver for ARM's Mali-C55 Image Signal Processor. The
driver is located under drivers/media/platform/arm/mali-c55.
The Mali-C55 ISP receives data in either raw Bayer format or RGB/YUV format from
sensors through either a parallel interface or a memory bus before processing it
and outputting it through an internal DMA engine. Two output pipelines are
possible (though one may not be fitted, depending on the implementation). These
are referred to as "Full resolution" and "Downscale", but the naming is historic
and both pipes are capable of cropping/scaling operations. The full resolution
pipe is also capable of outputting RAW data, bypassing much of the ISP's
processing. The downscale pipe cannot output RAW data. An integrated test
pattern generator can be used to drive the ISP and produce image data in the
absence of a connected camera sensor. The driver module is named mali_c55, and
is enabled through the CONFIG_VIDEO_MALI_C55 config option.
The driver implements V4L2, Media Controller and V4L2 Subdevice interfaces and
expects camera sensors connected to the ISP to have V4L2 subdevice interfaces.
Mali-C55 ISP hardware
=====================
A high level functional view of the Mali-C55 ISP is presented below. The ISP
takes input from either a live source or through a DMA engine for memory input,
depending on the SoC integration.::
+---------+ +----------+ +--------+
| Sensor |--->| CSI-2 Rx | "Full Resolution" | DMA |
+---------+ +----------+ |\ Output +--->| Writer |
| | \ | +--------+
| | \ +----------+ +------+---> Streaming I/O
+------------+ +------->| | | | |
| | | |-->| Mali-C55 |--+
| DMA Reader |--------------->| | | ISP | |
| | | / | | | +---> Streaming I/O
+------------+ | / +----------+ | |
|/ +------+
| +--------+
+--->| DMA |
"Downscaled" | Writer |
Output +--------+
Media Controller Topology
=========================
An example of the ISP's topology (as implemented in a system with an IMX415
camera sensor and generic CSI-2 receiver) is below:
.. kernel-figure:: mali-c55-graph.dot
:alt: mali-c55-graph.dot
:align: center
The driver has 4 V4L2 subdevices:
- `mali_c55 isp`: Responsible for configuring input crop and color space
conversion
- `mali_c55 tpg`: The test pattern generator, emulating a camera sensor.
- `mali_c55 resizer fr`: The Full-Resolution pipe resizer
- `mali_c55 resizer ds`: The Downscale pipe resizer
The driver has 3 V4L2 video devices:
- `mali-c55 fr`: The full-resolution pipe's capture device
- `mali-c55 ds`: The downscale pipe's capture device
- `mali-c55 3a stats`: The 3A statistics capture device
Frame sequences are synchronised across to two capture devices, meaning if one
pipe is started later than the other the sequence numbers returned in its
buffers will match those of the other pipe rather than starting from zero.
Idiosyncrasies
--------------
**mali-c55 isp**
The `mali-c55 isp` subdevice has a single sink pad to which all sources of data
should be connected. The active source is selected by enabling the appropriate
media link and disabling all others. The ISP has two source pads, reflecting the
different paths through which it can internally route data. Tap points within
the ISP allow users to divert data to avoid processing by some or all of the
hardware's processing steps. The diagram below is intended only to highlight how
the bypassing works and is not a true reflection of those processing steps; for
a high-level functional block diagram see ARM's developer page for the
ISP [3]_::
+--------------------------------------------------------------+
| Possible Internal ISP Data Routes |
| +------------+ +----------+ +------------+ |
+---+ | | | | | Colour | +---+
| 0 |--+-->| Processing |->| Demosaic |->| Space |--->| 1 |
+---+ | | | | | | Conversion | +---+
| | +------------+ +----------+ +------------+ |
| | +---+
| +---------------------------------------------------| 2 |
| +---+
| |
+--------------------------------------------------------------+
.. flat-table::
:header-rows: 1
* - Pad
- Direction
- Purpose
* - 0
- sink
- Data input, connected to the TPG and camera sensors
* - 1
- source
- RGB/YUV data, connected to the FR and DS V4L2 subdevices
* - 2
- source
- RAW bayer data, connected to the FR V4L2 subdevices
The ISP is limited to both input and output resolutions between 640x480 and
8192x8192, and this is reflected in the ISP and resizer subdevice's .set_fmt()
operations.
**mali-c55 resizer fr**
The `mali-c55 resizer fr` subdevice has two _sink_ pads to reflect the different
insertion points in the hardware (either RAW or demosaiced data):
.. flat-table::
:header-rows: 1
* - Pad
- Direction
- Purpose
* - 0
- sink
- Data input connected to the ISP's demosaiced stream.
* - 1
- source
- Data output connected to the capture video device
* - 2
- sink
- Data input connected to the ISP's raw data stream
The data source in use is selected through the routing API; two routes each of a
single stream are available:
.. flat-table::
:header-rows: 1
* - Sink Pad
- Source Pad
- Purpose
* - 0
- 1
- Demosaiced data route
* - 2
- 1
- Raw data route
If the demosaiced route is active then the FR pipe is only capable of output
in RGB/YUV formats. If the raw route is active then the output reflects the
input (which may be either Bayer or RGB/YUV data).
Using the driver to capture video
=================================
Using the media controller APIs we can configure the input source and ISP to
capture images in a variety of formats. In the examples below, configuring the
media graph is done with the v4l-utils [1]_ package's media-ctl utility.
Capturing the images is done with yavta [2]_.
Configuring the input source
----------------------------
The first step is to set the input source that we wish by enabling the correct
media link. Using the example topology above, we can select the TPG as follows:
.. code-block:: none
media-ctl -l "'lte-csi2-rx':1->'mali-c55 isp':0[0]"
media-ctl -l "'mali-c55 tpg':0->'mali-c55 isp':0[1]"
Configuring which video devices will stream data
------------------------------------------------
The driver will wait for all video devices to have their VIDIOC_STREAMON ioctl
called before it tells the sensor to start streaming. To facilitate this we need
to enable links to the video devices that we want to use. In the example below
we enable the links to both of the image capture video devices
.. code-block:: none
media-ctl -l "'mali-c55 resizer fr':1->'mali-c55 fr':0[1]"
media-ctl -l "'mali-c55 resizer ds':1->'mali-c55 ds':0[1]"
Capturing bayer data from the source and processing to RGB/YUV
--------------------------------------------------------------
To capture 1920x1080 bayer data from the source and push it through the ISP's
full processing pipeline, we configure the data formats appropriately on the
source, ISP and resizer subdevices and set the FR resizer's routing to select
processed data. The media bus format on the resizer's source pad will be either
RGB121212_1X36 or YUV10_1X30, depending on whether you want to capture RGB or
YUV. The ISP's debayering block outputs RGB data natively, setting the source
pad format to YUV10_1X30 enables the colour space conversion block.
In this example we target RGB565 output, so select RGB121212_1X36 as the resizer
source pad's format:
.. code-block:: none
# Set formats on the TPG and ISP
media-ctl -V "'mali-c55 tpg':0[fmt:SRGGB20_1X20/1920x1080]"
media-ctl -V "'mali-c55 isp':0[fmt:SRGGB20_1X20/1920x1080]"
media-ctl -V "'mali-c55 isp':1[fmt:SRGGB20_1X20/1920x1080]"
# Set routing on the FR resizer
media-ctl -R "'mali-c55 resizer fr'[0/0->1/0[1],2/0->1/0[0]]"
# Set format on the resizer, must be done AFTER the routing.
media-ctl -V "'mali-c55 resizer fr':1[fmt:RGB121212_1X36/1920x1080]"
The downscale output can also be used to stream data at the same time. In this
case since only processed data can be captured through the downscale output no
routing need be set:
.. code-block:: none
# Set format on the resizer
media-ctl -V "'mali-c55 resizer ds':1[fmt:RGB121212_1X36/1920x1080]"
Following which images can be captured from both the FR and DS output's video
devices (simultaneously, if desired):
.. code-block:: none
yavta -f RGB565 -s 1920x1080 -c10 /dev/video0
yavta -f RGB565 -s 1920x1080 -c10 /dev/video1
Cropping the image
~~~~~~~~~~~~~~~~~~
Both the full resolution and downscale pipes can crop to a minimum resolution of
640x480. To crop the image simply configure the resizer's sink pad's crop and
compose rectangles and set the format on the video device:
.. code-block:: none
media-ctl -V "'mali-c55 resizer fr':0[fmt:RGB121212_1X36/1920x1080 crop:(480,270)/640x480 compose:(0,0)/640x480]"
media-ctl -V "'mali-c55 resizer fr':1[fmt:RGB121212_1X36/640x480]"
yavta -f RGB565 -s 640x480 -c10 /dev/video0
Downscaling the image
~~~~~~~~~~~~~~~~~~~~~
Both the full resolution and downscale pipes can downscale the image by up to 8x
provided the minimum 640x480 output resolution is adhered to. For the best image
result the scaling ratio for each direction should be the same. To configure
scaling we use the compose rectangle on the resizer's sink pad:
.. code-block:: none
media-ctl -V "'mali-c55 resizer fr':0[fmt:RGB121212_1X36/1920x1080 crop:(0,0)/1920x1080 compose:(0,0)/640x480]"
media-ctl -V "'mali-c55 resizer fr':1[fmt:RGB121212_1X36/640x480]"
yavta -f RGB565 -s 640x480 -c10 /dev/video0
Capturing images in YUV formats
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
If we need to output YUV data rather than RGB the color space conversion block
needs to be active, which is achieved by setting MEDIA_BUS_FMT_YUV10_1X30 on the
resizer's source pad. We can then configure a capture format like NV12 (here in
its multi-planar variant)
.. code-block:: none
media-ctl -V "'mali-c55 resizer fr':1[fmt:YUV10_1X30/1920x1080]"
yavta -f NV12M -s 1920x1080 -c10 /dev/video0
Capturing RGB data from the source and processing it with the resizers
----------------------------------------------------------------------
The Mali-C55 ISP can work with sensors capable of outputting RGB data. In this
case although none of the image quality blocks would be used it can still
crop/scale the data in the usual way. For this reason RGB data input to the ISP
still goes through the ISP subdevice's pad 1 to the resizer.
To achieve this, the ISP's sink pad's format is set to
MEDIA_BUS_FMT_RGB202020_1X60 - this reflects the format that data must be in to
work with the ISP. Converting the camera sensor's output to that format is the
responsibility of external hardware.
In this example we ask the test pattern generator to give us RGB data instead of
bayer.
.. code-block:: none
media-ctl -V "'mali-c55 tpg':0[fmt:RGB202020_1X60/1920x1080]"
media-ctl -V "'mali-c55 isp':0[fmt:RGB202020_1X60/1920x1080]"
Cropping or scaling the data can be done in exactly the same way as outlined
earlier.
Capturing raw data from the source and outputting it unmodified
-----------------------------------------------------------------
The ISP can additionally capture raw data from the source and output it on the
full resolution pipe only, completely unmodified. In this case the downscale
pipe can still process the data normally and be used at the same time.
To configure raw bypass the FR resizer's subdevice's routing table needs to be
configured, followed by formats in the appropriate places:
.. code-block:: none
media-ctl -R "'mali-c55 resizer fr'[0/0->1/0[0],2/0->1/0[1]]"
media-ctl -V "'mali-c55 isp':0[fmt:RGB202020_1X60/1920x1080]"
media-ctl -V "'mali-c55 resizer fr':2[fmt:RGB202020_1X60/1920x1080]"
media-ctl -V "'mali-c55 resizer fr':1[fmt:RGB202020_1X60/1920x1080]"
# Set format on the video device and stream
yavta -f RGB565 -s 1920x1080 -c10 /dev/video0
.. _mali-c55-3a-stats:
Capturing ISP Statistics
========================
The ISP is capable of producing statistics for consumption by image processing
algorithms running in userspace. These statistics can be captured by queueing
buffers to the `mali-c55 3a stats` V4L2 Device whilst the ISP is streaming. Only
the :ref:`V4L2_META_FMT_MALI_C55_STATS <v4l2-meta-fmt-mali-c55-stats>`
format is supported, so no format-setting need be done:
.. code-block:: none
# We assume the media graph has been configured to support RGB565 capture
# from the mali-c55 fr V4L2 Device, which is at /dev/video0. The statistics
# V4L2 device is at /dev/video3
yavta -f RGB565 -s 1920x1080 -c32 /dev/video0 && \
yavta -c10 -F /dev/video3
The layout of the buffer is described by :c:type:`mali_c55_stats_buffer`,
but broadly statistics are generated to support three image processing
algorithms; AEXP (Auto-Exposure), AWB (Auto-White Balance) and AF (Auto-Focus).
These stats can be drawn from various places in the Mali C55 ISP pipeline, known
as "tap points". This high-level block diagram is intended to explain where in
the processing flow the statistics can be drawn from::
+--> AEXP-2 +----> AEXP-1 +--> AF-0
| +----> AF-1 |
| | |
+---------+ | +--------------+ | +--------------+ |
| Input +-+-->+ Digital Gain +---+-->+ Black Level +---+---+
+---------+ +--------------+ +--------------+ |
+-----------------------------------------------------------------+
|
| +--------------+ +---------+ +----------------+
+-->| Sinter Noise +-+ White +--+--->| Lens Shading +--+---------------+
| Reduction | | Balance | | | | | |
+--------------+ +---------+ | +----------------+ | |
+---> AEXP-0 (A) +--> AEXP-0 (B) |
+--------------------------------------------------------------------------+
|
| +----------------+ +--------------+ +----------------+
+-->| Tone mapping +-+--->| Demosaicing +->+ Purple Fringe +-+-----------+
| | | +--------------+ | Correction | | |
+----------------+ +-> AEXP-IRIDIX +----------------+ +---> AWB-0 |
+----------------------------------------------------------------------------+
| +-------------+ +-------------+
+------------------->| Colour +---+--->| Output |
| Correction | | | Pipelines |
+-------------+ | +-------------+
+--> AWB-1
By default all statistics are drawn from the 0th tap point for each algorithm;
I.E. AEXP statistics from AEXP-0 (A), AWB statistics from AWB-0 and AF
statistics from AF-0. This is configurable for AEXP and AWB statsistics through
programming the ISP's parameters.
.. _mali-c55-3a-params:
Programming ISP Parameters
==========================
The ISP can be programmed with various parameters from userspace to apply to the
hardware before and during video stream. This allows userspace to dynamically
change values such as black level, white balance and lens shading gains and so
on.
The buffer format and how to populate it are described by the
:ref:`V4L2_META_FMT_MALI_C55_PARAMS <v4l2-meta-fmt-mali-c55-params>` format,
which should be set as the data format for the `mali-c55 3a params` video node.
References
==========
.. [1] https://git.linuxtv.org/v4l-utils.git/
.. [2] https://git.ideasonboard.org/yavta.git
.. [3] https://developer.arm.com/Processors/Mali-C55
Documentation/admin-guide/media/platform-cardlist.rst
-2
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@@ -18,8 +18,6 @@ am437x-vpfe TI AM437x VPFE
aspeed-video Aspeed AST2400 and AST2500
atmel-isc ATMEL Image Sensor Controller (ISC)
atmel-isi ATMEL Image Sensor Interface (ISI)
c8sectpfe SDR platform devices
c8sectpfe SDR platform devices
cafe_ccic Marvell 88ALP01 (Cafe) CMOS Camera Controller
cdns-csi2rx Cadence MIPI-CSI2 RX Controller
cdns-csi2tx Cadence MIPI-CSI2 TX Controller
Documentation/admin-guide/media/rkcif-rk3568-vicap.dot
+8
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@@ -0,0 +1,8 @@
digraph board {
rankdir=TB
n00000001 [label="{{<port0> 0} | rkcif-dvp0\n/dev/v4l-subdev0 | {<port1> 1}}", shape=Mrecord, style=filled, fillcolor=green]
n00000001:port1 -> n00000004
n00000004 [label="rkcif-dvp0-id0\n/dev/video0", shape=box, style=filled, fillcolor=yellow]
n00000025 [label="{{} | it6801 2-0048\n/dev/v4l-subdev1 | {<port0> 0}}", shape=Mrecord, style=filled, fillcolor=green]
n00000025:port0 -> n00000001:port0
}
Documentation/admin-guide/media/rkcif.rst
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@@ -0,0 +1,79 @@
.. SPDX-License-Identifier: GPL-2.0
=========================================
Rockchip Camera Interface (CIF)
=========================================
Introduction
============
The Rockchip Camera Interface (CIF) is featured in many Rockchip SoCs in
different variants.
The different variants are combinations of common building blocks, such as
* INTERFACE blocks of different types, namely
* the Digital Video Port (DVP, a parallel data interface)
* the interface block for the MIPI CSI-2 receiver
* CROP units
* MIPI CSI-2 receiver (not available on all variants): This unit is referred
to as MIPI CSI HOST in the Rockchip documentation.
Technically, it is a separate hardware block, but it is strongly coupled to
the CIF and therefore included here.
* MUX units (not available on all variants) that pass the video data to an
image signal processor (ISP)
* SCALE units (not available on all variants)
* DMA engines that transfer video data into system memory using a
double-buffering mechanism called ping-pong mode
* Support for four streams per INTERFACE block (not available on all
variants), e.g., for MIPI CSI-2 Virtual Channels (VCs)
This document describes the different variants of the CIF, their hardware
layout, as well as their representation in the media controller centric rkcif
device driver, which is located under drivers/media/platform/rockchip/rkcif.
Variants
========
Rockchip PX30 Video Input Processor (VIP)
-----------------------------------------
The PX30 Video Input Processor (VIP) features a digital video port that accepts
parallel video data or BT.656.
Since these protocols do not feature multiple streams, the VIP has one DMA
engine that transfers the input video data into system memory.
The rkcif driver represents this hardware variant by exposing one V4L2 subdevice
(the DVP INTERFACE/CROP block) and one V4L2 device (the DVP DMA engine).
Rockchip RK3568 Video Capture (VICAP)
-------------------------------------
The RK3568 Video Capture (VICAP) unit features a digital video port and a MIPI
CSI-2 receiver that can receive video data independently.
The DVP accepts parallel video data, BT.656 and BT.1120.
Since the BT.1120 protocol may feature more than one stream, the RK3568 VICAP
DVP features four DMA engines that can capture different streams.
Similarly, the RK3568 VICAP MIPI CSI-2 receiver features four DMA engines to
handle different Virtual Channels (VCs).
The rkcif driver represents this hardware variant by exposing up the following
V4L2 subdevices:
* rkcif-dvp0: INTERFACE/CROP block for the DVP
and the following video devices:
* rkcif-dvp0-id0: The support for multiple streams on the DVP is not yet
implemented, as it is hard to find test hardware. Thus, this video device
represents the first DMA engine of the RK3568 DVP.
.. kernel-figure:: rkcif-rk3568-vicap.dot
:alt: Topology of the RK3568 Video Capture (VICAP) unit
:align: center
Documentation/admin-guide/media/v4l-drivers.rst
+2
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@@ -19,12 +19,14 @@ Video4Linux (V4L) driver-specific documentation
ipu3
ipu6-isys
ivtv
mali-c55
mgb4
omap3isp
philips
qcom_camss
raspberrypi-pisp-be
rcar-fdp1
rkcif
rkisp1
raspberrypi-rp1-cfe
saa7134
Documentation/devicetree/bindings/media/arm,mali-c55.yaml
+86
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@@ -0,0 +1,86 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/arm,mali-c55.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ARM Mali-C55 Image Signal Processor
maintainers:
- Daniel Scally <dan.scally@ideasonboard.com>
- Jacopo Mondi <jacopo.mondi@ideasonboard.com>
properties:
compatible:
const: arm,mali-c55
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: ISP Video Clock
- description: ISP AXI clock
- description: ISP AHB-lite clock
clock-names:
items:
- const: vclk
- const: aclk
- const: hclk
resets:
items:
- description: vclk domain reset
- description: aclk domain reset
- description: hclk domain reset
reset-names:
items:
- const: vresetn
- const: aresetn
- const: hresetn
port:
$ref: /schemas/graph.yaml#/properties/port
description: Input parallel video bus
properties:
endpoint:
$ref: /schemas/graph.yaml#/properties/endpoint
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- resets
- reset-names
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
isp@400000 {
compatible = "arm,mali-c55";
reg = <0x400000 0x200000>;
clocks = <&clk 0>, <&clk 1>, <&clk 2>;
clock-names = "vclk", "aclk", "hclk";
resets = <&resets 0>, <&resets 1>, <&resets 2>;
reset-names = "vresetn", "aresetn", "hresetn";
interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
port {
isp_in: endpoint {
remote-endpoint = <&csi2_rx_out>;
};
};
};
...
Documentation/devicetree/bindings/media/i2c/dongwoon,dw9719.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/dongwoon,dw9719.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Dongwoon Anatech DW9719 Voice Coil Motor (VCM) Controller
maintainers:
- André Apitzsch <git@apitzsch.eu>
description:
The Dongwoon DW9718S/9719/9761 is a single 10-bit digital-to-analog converter
with 100 mA output current sink capability, designed for linear control of
voice coil motors (VCM) in camera lenses. This chip provides a Smart Actuator
Control (SAC) mode intended for driving voice coil lenses in camera modules.
properties:
compatible:
enum:
- dongwoon,dw9718s
- dongwoon,dw9719
- dongwoon,dw9761
- dongwoon,dw9800k
reg:
maxItems: 1
vdd-supply:
description: VDD power supply
dongwoon,sac-mode:
description: |
Slew Rate Control mode to use: direct, LSC (Linear Slope Control) or
SAC1-SAC6 (Smart Actuator Control).
$ref: /schemas/types.yaml#/definitions/uint32
enum:
- 0 # Direct mode
- 1 # LSC mode
- 2 # SAC1 mode (operation time# 0.32 x Tvib)
- 3 # SAC2 mode (operation time# 0.48 x Tvib)
- 4 # SAC3 mode (operation time# 0.72 x Tvib)
- 5 # SAC4 mode (operation time# 1.20 x Tvib)
- 6 # SAC5 mode (operation time# 1.64 x Tvib)
- 7 # SAC6 mode (operation time# 1.88 x Tvib)
default: 4
dongwoon,vcm-prescale:
description:
Indication of VCM switching frequency dividing rate select.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- compatible
- reg
- vdd-supply
allOf:
- if:
properties:
compatible:
contains:
const: dongwoon,dw9718s
then:
properties:
dongwoon,vcm-prescale:
description:
The final frequency is 10 MHz divided by (value + 2).
maximum: 15
default: 0
additionalProperties: false
examples:
- |
i2c {
#address-cells = <1>;
#size-cells = <0>;
actuator@c {
compatible = "dongwoon,dw9718s";
reg = <0x0c>;
vdd-supply = <&pm8937_l17>;
dongwoon,sac-mode = <4>;
dongwoon,vcm-prescale = <0>;
};
};
Documentation/devicetree/bindings/media/i2c/nxp,tda19971.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/nxp,tda19971.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: NXP TDA1997x HDMI receiver
maintainers:
- Frank Li <Frank.Li@nxp.com>
description: |
The TDA19971/73 are HDMI video receivers.
The TDA19971 Video port output pins can be used as follows:
- RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
- YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
- YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
- YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
- YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
- YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
- YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
- YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
The TDA19973 Video port output pins can be used as follows:
- RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
- YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
- YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
- YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
The Video port output pins are mapped via 4-bit 'pin groups' allowing
for a variety of connection possibilities including swapping pin order within
pin groups. The video_portcfg device-tree property consists of register mapping
pairs which map a chip-specific VP output register to a 4-bit pin group. If
the pin group needs to be bit-swapped you can use the *_S pin-group defines.
properties:
compatible:
enum:
- nxp,tda19971
- nxp,tda19973
reg:
maxItems: 1
interrupts:
maxItems: 1
DOVDD-supply: true
DVDD-supply: true
AVDD-supply: true
'#sound-dai-cells':
const: 0
port:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
nxp,vidout-portcfg:
$ref: /schemas/types.yaml#/definitions/uint32-matrix
minItems: 1
maxItems: 4
items:
items:
- description: Video Port control registers index.
maximum: 8
minimum: 0
- description: pin(pinswapped) groups
description:
array of pairs mapping VP output pins to pin groups.
nxp,audout-format:
enum:
- i2s
- spdif
nxp,audout-width:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [8, 16, 24, 32]
description:
width of audio output data bus.
nxp,audout-layout:
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1]
description:
data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used).
nxp,audout-mclk-fs:
$ref: /schemas/types.yaml#/definitions/uint32
description:
Multiplication factor between stream rate and codec mclk.
required:
- compatible
- reg
- interrupts
- DOVDD-supply
- AVDD-supply
- DVDD-supply
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/media/tda1997x.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
hdmi-receiver@48 {
compatible = "nxp,tda19971";
reg = <0x48>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tda1997x>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
DOVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_1p8v>;
DVDD-supply = <&reg_1p8v>;
/* audio */
#sound-dai-cells = <0>;
nxp,audout-format = "i2s";
nxp,audout-layout = <0>;
nxp,audout-width = <16>;
nxp,audout-mclk-fs = <128>;
/*
* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
* and Y[11:4] across 16bits in the same pixclk cycle.
*/
nxp,vidout-portcfg =
/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
/* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
/* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
port {
endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <16>;
hsync-active = <1>;
vsync-active = <1>;
data-active = <1>;
};
};
};
};
Documentation/devicetree/bindings/media/i2c/nxp,tda1997x.txt
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Device-Tree bindings for the NXP TDA1997x HDMI receiver
The TDA19971/73 are HDMI video receivers.
The TDA19971 Video port output pins can be used as follows:
- RGB 8bit per color (24 bits total): R[11:4] B[11:4] G[11:4]
- YUV444 8bit per color (24 bits total): Y[11:4] Cr[11:4] Cb[11:4]
- YUV422 semi-planar 8bit per component (16 bits total): Y[11:4] CbCr[11:4]
- YUV422 semi-planar 10bit per component (20 bits total): Y[11:2] CbCr[11:2]
- YUV422 semi-planar 12bit per component (24 bits total): - Y[11:0] CbCr[11:0]
- YUV422 BT656 8bit per component (8 bits total): YCbCr[11:4] (2-cycles)
- YUV422 BT656 10bit per component (10 bits total): YCbCr[11:2] (2-cycles)
- YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
The TDA19973 Video port output pins can be used as follows:
- RGB 12bit per color (36 bits total): R[11:0] B[11:0] G[11:0]
- YUV444 12bit per color (36 bits total): Y[11:0] Cb[11:0] Cr[11:0]
- YUV422 semi-planar 12bit per component (24 bits total): Y[11:0] CbCr[11:0]
- YUV422 BT656 12bit per component (12 bits total): YCbCr[11:0] (2-cycles)
The Video port output pins are mapped via 4-bit 'pin groups' allowing
for a variety of connection possibilities including swapping pin order within
pin groups. The video_portcfg device-tree property consists of register mapping
pairs which map a chip-specific VP output register to a 4-bit pin group. If
the pin group needs to be bit-swapped you can use the *_S pin-group defines.
Required Properties:
- compatible :
- "nxp,tda19971" for the TDA19971
- "nxp,tda19973" for the TDA19973
- reg : I2C slave address
- interrupts : The interrupt number
- DOVDD-supply : Digital I/O supply
- DVDD-supply : Digital Core supply
- AVDD-supply : Analog supply
- nxp,vidout-portcfg : array of pairs mapping VP output pins to pin groups.
Optional Properties:
- nxp,audout-format : DAI bus format: "i2s" or "spdif".
- nxp,audout-width : width of audio output data bus (1-4).
- nxp,audout-layout : data layout (0=AP0 used, 1=AP0/AP1/AP2/AP3 used).
- nxp,audout-mclk-fs : Multiplication factor between stream rate and codec
mclk.
The port node shall contain one endpoint child node for its digital
output video port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt.
Optional Endpoint Properties:
The following three properties are defined in video-interfaces.txt and
are valid for the output parallel bus endpoint:
- hsync-active: Horizontal synchronization polarity. Defaults to active high.
- vsync-active: Vertical synchronization polarity. Defaults to active high.
- data-active: Data polarity. Defaults to active high.
Examples:
- VP[15:0] connected to IMX6 CSI_DATA[19:4] for 16bit YUV422
16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
hdmi-receiver@48 {
compatible = "nxp,tda19971";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tda1997x>;
reg = <0x48>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
DOVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_1p8v>;
DVDD-supply = <&reg_1p8v>;
/* audio */
#sound-dai-cells = <0>;
nxp,audout-format = "i2s";
nxp,audout-layout = <0>;
nxp,audout-width = <16>;
nxp,audout-mclk-fs = <128>;
/*
* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
* and Y[11:4] across 16bits in the same pixclk cycle.
*/
nxp,vidout-portcfg =
/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
/* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
/* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
port {
tda1997x_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <16>;
hsync-active = <1>;
vsync-active = <1>;
data-active = <1>;
};
};
};
- VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
hdmi-receiver@48 {
compatible = "nxp,tda19971";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tda1997x>;
reg = <0x48>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
DOVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_1p8v>;
DVDD-supply = <&reg_1p8v>;
/* audio */
#sound-dai-cells = <0>;
nxp,audout-format = "i2s";
nxp,audout-layout = <0>;
nxp,audout-width = <16>;
nxp,audout-mclk-fs = <128>;
/*
* The 8bpp YUV422 semi-planar mode outputs CbCr[11:4]
* and Y[11:4] across 16bits in the same pixclk cycle.
*/
nxp,vidout-portcfg =
/* Y[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
< TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >,
/* Y[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
< TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >,
/* CbCc[11:8]<->VP[07:04]<->CSI_DATA[11:8] */
< TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >,
/* CbCr[7:4]<->VP[03:00]<->CSI_DATA[7:4] */
< TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >;
port {
tda1997x_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <16>;
hsync-active = <1>;
vsync-active = <1>;
data-active = <1>;
};
};
};
- VP[15:8] connected to IMX6 CSI_DATA[19:12] for 8bit BT656
16bit I2S layout0 with a 128*fs clock (A_WS, AP0, A_CLK pins)
hdmi-receiver@48 {
compatible = "nxp,tda19971";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_tda1997x>;
reg = <0x48>;
interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
DOVDD-supply = <&reg_3p3v>;
AVDD-supply = <&reg_1p8v>;
DVDD-supply = <&reg_1p8v>;
/* audio */
#sound-dai-cells = <0>;
nxp,audout-format = "i2s";
nxp,audout-layout = <0>;
nxp,audout-width = <16>;
nxp,audout-mclk-fs = <128>;
/*
* The 8bpp BT656 mode outputs YCbCr[11:4] across 8bits over
* 2 pixclk cycles.
*/
nxp,vidout-portcfg =
/* YCbCr[11:8]<->VP[15:12]<->CSI_DATA[19:16] */
< TDA1997X_VP24_V15_12 TDA1997X_R_CR_CBCR_11_8 >,
/* YCbCr[7:4]<->VP[11:08]<->CSI_DATA[15:12] */
< TDA1997X_VP24_V11_08 TDA1997X_R_CR_CBCR_7_4 >,
port {
tda1997x_to_ipu1_csi0_mux: endpoint {
remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
bus-width = <16>;
hsync-active = <1>;
vsync-active = <1>;
data-active = <1>;
};
};
};
Documentation/devicetree/bindings/media/i2c/sony,imx111.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/sony,imx111.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Sony IMX111 8MP CMOS Digital Image Sensor
maintainers:
- Svyatoslav Ryhel <clamor95@gmail.com>
description:
IMX111 sensor is a Sony CMOS active pixel digital image sensor with an active
array size of 2464H x 3280V. It is programmable through I2C interface. Image
data is sent through MIPI CSI-2, through 1 or 2 lanes.
allOf:
- $ref: /schemas/media/video-interface-devices.yaml#
- $ref: /schemas/nvmem/nvmem-consumer.yaml#
properties:
compatible:
const: sony,imx111
reg:
maxItems: 1
clocks:
description: EXTCLK with possible frequency from 6 to 54 MHz
maxItems: 1
reset-gpios:
maxItems: 1
iovdd-supply:
description: Digital IO power supply (1.8V)
dvdd-supply:
description: Digital power supply (1.2V)
avdd-supply:
description: Analog power supply (2.7V)
port:
additionalProperties: false
$ref: /schemas/graph.yaml#/$defs/port-base
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
required:
- data-lanes
- link-frequencies
required:
- endpoint
required:
- compatible
- reg
- clocks
- port
unevaluatedProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/media/video-interfaces.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
camera@10 {
compatible = "sony,imx111";
reg = <0x10>;
clocks = <&imx111_clk>;
iovdd-supply = <&camera_vddio_1v8>;
dvdd-supply = <&camera_vddd_1v2>;
avdd-supply = <&camera_vdda_2v7>;
orientation = <1>;
rotation = <90>;
nvmem = <&eeprom>;
flash-leds = <&led>;
lens-focus = <&vcm>;
reset-gpios = <&gpio 84 GPIO_ACTIVE_LOW>;
port {
imx111_output: endpoint {
data-lanes = <1 2>;
link-frequencies = /bits/ 64 <542400000>;
remote-endpoint = <&csi_input>;
};
};
};
};
...
Documentation/devicetree/bindings/media/i2c/st,vd55g1.yaml
+5 -1
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@@ -25,7 +25,11 @@ allOf:
properties:
compatible:
const: st,vd55g1
enum:
- st,vd55g1
- st,vd65g4
description:
VD55G1 is the monochrome variant, while VD65G4 is the color one.
reg:
maxItems: 1
Documentation/devicetree/bindings/media/i2c/ti,tvp5150.txt
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* Texas Instruments TVP5150 and TVP5151 video decoders
The TVP5150 and TVP5151 are video decoders that convert baseband NTSC and PAL
(and also SECAM in the TVP5151 case) video signals to either 8-bit 4:2:2 YUV
with discrete syncs or 8-bit ITU-R BT.656 with embedded syncs output formats.
Required Properties:
====================
- compatible: Value must be "ti,tvp5150".
- reg: I2C slave address.
Optional Properties:
====================
- pdn-gpios: Phandle for the GPIO connected to the PDN pin, if any.
- reset-gpios: Phandle for the GPIO connected to the RESETB pin, if any.
The device node must contain one 'port' child node per device physical input
and output port, in accordance with the video interface bindings defined in
Documentation/devicetree/bindings/media/video-interfaces.txt. The port nodes
are numbered as follows
Name Type Port
--------------------------------------
AIP1A sink 0
AIP1B sink 1
Y-OUT src 2
The device node must contain at least one sink port and the src port. Each input
port must be linked to an endpoint defined in [1]. The port/connector layout is
as follows
tvp-5150 port@0 (AIP1A)
endpoint@0 -----------> Comp0-Con port
endpoint@1 ------+----> Svideo-Con port
tvp-5150 port@1 (AIP1B) |
endpoint@1 ------+
endpoint@0 -----------> Comp1-Con port
tvp-5150 port@2
endpoint (video bitstream output at YOUT[0-7] parallel bus)
Required Endpoint Properties for parallel synchronization on output port:
=========================================================================
- hsync-active: Active state of the HSYNC signal. Must be <1> (HIGH).
- vsync-active: Active state of the VSYNC signal. Must be <1> (HIGH).
- field-even-active: Field signal level during the even field data
transmission. Must be <0>.
Note: Do not specify any of these properties if you want to use the embedded
BT.656 synchronization.
Optional Connector Properties:
==============================
- sdtv-standards: Set the possible signals to which the hardware tries to lock
instead of using the autodetection mechanism. Please look at
[1] for more information.
[1] Documentation/devicetree/bindings/display/connector/analog-tv-connector.yaml.
Example - three input sources:
#include <dt-bindings/display/sdtv-standards.h>
comp_connector_0 {
compatible = "composite-video-connector";
label = "Composite0";
sdtv-standards = <SDTV_STD_PAL_M>; /* limit to pal-m signals */
port {
composite0_to_tvp5150: endpoint {
remote-endpoint = <&tvp5150_to_composite0>;
};
};
};
comp_connector_1 {
compatible = "composite-video-connector";
label = "Composite1";
sdtv-standards = <SDTV_STD_NTSC_M>; /* limit to ntsc-m signals */
port {
composite1_to_tvp5150: endpoint {
remote-endpoint = <&tvp5150_to_composite1>;
};
};
};
svideo_connector {
compatible = "svideo-connector";
label = "S-Video";
port {
#address-cells = <1>;
#size-cells = <0>;
svideo_luma_to_tvp5150: endpoint@0 {
reg = <0>;
remote-endpoint = <&tvp5150_to_svideo_luma>;
};
svideo_chroma_to_tvp5150: endpoint@1 {
reg = <1>;
remote-endpoint = <&tvp5150_to_svideo_chroma>;
};
};
};
&i2c2 {
tvp5150@5c {
compatible = "ti,tvp5150";
reg = <0x5c>;
pdn-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
tvp5150_to_composite0: endpoint@0 {
reg = <0>;
remote-endpoint = <&composite0_to_tvp5150>;
};
tvp5150_to_svideo_luma: endpoint@1 {
reg = <1>;
remote-endpoint = <&svideo_luma_to_tvp5150>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
tvp5150_to_composite1: endpoint@0 {
reg = <0>;
remote-endpoint = <&composite1_to_tvp5150>;
};
tvp5150_to_svideo_chroma: endpoint@1 {
reg = <1>;
remote-endpoint = <&svideo_chroma_to_tvp5150>;
};
};
port@2 {
reg = <2>;
tvp5150_1: endpoint {
remote-endpoint = <&ccdc_ep>;
};
};
};
};
Documentation/devicetree/bindings/media/i2c/ti,tvp5150.yaml
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# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/i2c/ti,tvp5150.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Texas Instruments TVP5150 and TVP5151 video decoders
maintainers:
- Frank Li <Frank.Li@nxp.com>
description:
The TVP5150 and TVP5151 are video decoders that convert baseband NTSC and PAL
(and also SECAM in the TVP5151 case) video signals to either 8-bit 4:2:2 YUV
with discrete syncs or 8-bit ITU-R BT.656 with embedded syncs output formats.
properties:
compatible:
const: ti,tvp5150
reg:
maxItems: 1
pdn-gpios:
maxItems: 1
reset-gpios:
maxItems: 1
'#address-cells':
const: 1
'#size-cells':
const: 0
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
sink port node, AIP1A
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
port@1:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
sink port node, AIP1B
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
port@2:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
source port node, Y-OUT
properties:
endpoint:
$ref: /schemas/media/video-interfaces.yaml#
unevaluatedProperties: false
required:
- compatible
- reg
- port@2
additionalProperties: false
examples:
- |
#include <dt-bindings/display/sdtv-standards.h>
#include <dt-bindings/gpio/gpio.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
bridge@5c {
compatible = "ti,tvp5150";
reg = <0x5c>;
pdn-gpios = <&gpio4 30 GPIO_ACTIVE_LOW>;
reset-gpios = <&gpio6 7 GPIO_ACTIVE_LOW>;
#address-cells = <1>;
#size-cells = <0>;
port@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
endpoint@0 {
reg = <0>;
remote-endpoint = <&composite0_to_tvp5150>;
};
endpoint@1 {
reg = <1>;
remote-endpoint = <&svideo_luma_to_tvp5150>;
};
};
port@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
endpoint@0 {
reg = <0>;
remote-endpoint = <&composite1_to_tvp5150>;
};
endpoint@1 {
reg = <1>;
remote-endpoint = <&svideo_chroma_to_tvp5150>;
};
};
port@2 {
reg = <2>;
endpoint {
remote-endpoint = <&ccdc_ep>;
};
};
};
};
Documentation/devicetree/bindings/media/nxp,imx8-isi.yaml
+12 -1
View File
@@ -22,6 +22,7 @@ properties:
- fsl,imx8mn-isi
- fsl,imx8mp-isi
- fsl,imx8ulp-isi
- fsl,imx91-isi
- fsl,imx93-isi
reg:
@@ -66,7 +67,6 @@ required:
- interrupts
- clocks
- clock-names
- fsl,blk-ctrl
- ports
allOf:
@@ -77,6 +77,7 @@ allOf:
enum:
- fsl,imx8mn-isi
- fsl,imx8ulp-isi
- fsl,imx91-isi
- fsl,imx93-isi
then:
properties:
@@ -109,6 +110,16 @@ allOf:
- port@0
- port@1
- if:
properties:
compatible:
not:
contains:
const: fsl,imx91-isi
then:
required:
- fsl,blk-ctrl
additionalProperties: false
examples:
Documentation/devicetree/bindings/media/qcom,msm8939-camss.yaml
+254
View File
@@ -0,0 +1,254 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,msm8939-camss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm MSM8939 Camera Subsystem (CAMSS)
maintainers:
- Vincent Knecht <vincent.knecht@mailoo.org>
description:
The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms
properties:
compatible:
const: qcom,msm8939-camss
reg:
maxItems: 11
reg-names:
items:
- const: csiphy0
- const: csiphy0_clk_mux
- const: csiphy1
- const: csiphy1_clk_mux
- const: csid0
- const: csid1
- const: ispif
- const: csi_clk_mux
- const: vfe0
- const: csid2
- const: vfe0_vbif
clocks:
maxItems: 24
clock-names:
items:
- const: top_ahb
- const: ispif_ahb
- const: csiphy0_timer
- const: csiphy1_timer
- const: csi0_ahb
- const: csi0
- const: csi0_phy
- const: csi0_pix
- const: csi0_rdi
- const: csi1_ahb
- const: csi1
- const: csi1_phy
- const: csi1_pix
- const: csi1_rdi
- const: ahb
- const: vfe0
- const: csi_vfe0
- const: vfe_ahb
- const: vfe_axi
- const: csi2_ahb
- const: csi2
- const: csi2_phy
- const: csi2_pix
- const: csi2_rdi
interrupts:
maxItems: 7
interrupt-names:
items:
- const: csiphy0
- const: csiphy1
- const: csid0
- const: csid1
- const: ispif
- const: vfe0
- const: csid2
iommus:
maxItems: 1
power-domains:
items:
- description: VFE GDSC - Video Front End, Global Distributed Switch
Controller.
vdda-supply:
description:
Definition of the regulator used as 1.2V analog power supply.
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
CSI input ports.
patternProperties:
"^port@[0-1]$":
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
bus-type:
enum:
- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
required:
- data-lanes
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- interrupts
- interrupt-names
- iommus
- power-domains
- vdda-supply
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-msm8939.h>
isp@1b0ac00 {
compatible = "qcom,msm8939-camss";
reg = <0x01b0ac00 0x200>,
<0x01b00030 0x4>,
<0x01b0b000 0x200>,
<0x01b00038 0x4>,
<0x01b08000 0x100>,
<0x01b08400 0x100>,
<0x01b0a000 0x500>,
<0x01b00020 0x10>,
<0x01b10000 0x1000>,
<0x01b08800 0x100>,
<0x01b40000 0x200>;
reg-names = "csiphy0",
"csiphy0_clk_mux",
"csiphy1",
"csiphy1_clk_mux",
"csid0",
"csid1",
"ispif",
"csi_clk_mux",
"vfe0",
"csid2",
"vfe0_vbif";
clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
<&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
<&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
<&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
<&gcc GCC_CAMSS_CSI0_AHB_CLK>,
<&gcc GCC_CAMSS_CSI0_CLK>,
<&gcc GCC_CAMSS_CSI0PHY_CLK>,
<&gcc GCC_CAMSS_CSI0PIX_CLK>,
<&gcc GCC_CAMSS_CSI0RDI_CLK>,
<&gcc GCC_CAMSS_CSI1_AHB_CLK>,
<&gcc GCC_CAMSS_CSI1_CLK>,
<&gcc GCC_CAMSS_CSI1PHY_CLK>,
<&gcc GCC_CAMSS_CSI1PIX_CLK>,
<&gcc GCC_CAMSS_CSI1RDI_CLK>,
<&gcc GCC_CAMSS_AHB_CLK>,
<&gcc GCC_CAMSS_VFE0_CLK>,
<&gcc GCC_CAMSS_CSI_VFE0_CLK>,
<&gcc GCC_CAMSS_VFE_AHB_CLK>,
<&gcc GCC_CAMSS_VFE_AXI_CLK>,
<&gcc GCC_CAMSS_CSI2_AHB_CLK>,
<&gcc GCC_CAMSS_CSI2_CLK>,
<&gcc GCC_CAMSS_CSI2PHY_CLK>,
<&gcc GCC_CAMSS_CSI2PIX_CLK>,
<&gcc GCC_CAMSS_CSI2RDI_CLK>;
clock-names = "top_ahb",
"ispif_ahb",
"csiphy0_timer",
"csiphy1_timer",
"csi0_ahb",
"csi0",
"csi0_phy",
"csi0_pix",
"csi0_rdi",
"csi1_ahb",
"csi1",
"csi1_phy",
"csi1_pix",
"csi1_rdi",
"ahb",
"vfe0",
"csi_vfe0",
"vfe_ahb",
"vfe_axi",
"csi2_ahb",
"csi2",
"csi2_phy",
"csi2_pix",
"csi2_rdi";
interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 57 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 153 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csiphy0",
"csiphy1",
"csid0",
"csid1",
"ispif",
"vfe0",
"csid2";
iommus = <&apps_iommu 3>;
power-domains = <&gcc VFE_GDSC>;
vdda-supply = <&reg_1v2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
csiphy1_ep: endpoint {
data-lanes = <0 2>;
remote-endpoint = <&sensor_ep>;
};
};
};
};
Documentation/devicetree/bindings/media/qcom,sm8650-camss.yaml
+375
View File
@@ -0,0 +1,375 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/qcom,sm8650-camss.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm SM8650 Camera Subsystem (CAMSS)
maintainers:
- Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
description:
The CAMSS IP is a CSI decoder and ISP present on Qualcomm platforms.
properties:
compatible:
const: qcom,sm8650-camss
reg:
maxItems: 17
reg-names:
items:
- const: csid_wrapper
- const: csid0
- const: csid1
- const: csid2
- const: csid_lite0
- const: csid_lite1
- const: csiphy0
- const: csiphy1
- const: csiphy2
- const: csiphy3
- const: csiphy4
- const: csiphy5
- const: vfe0
- const: vfe1
- const: vfe2
- const: vfe_lite0
- const: vfe_lite1
clocks:
maxItems: 33
clock-names:
items:
- const: camnoc_axi
- const: cpas_ahb
- const: cpas_fast_ahb
- const: cpas_vfe0
- const: cpas_vfe1
- const: cpas_vfe2
- const: cpas_vfe_lite
- const: csid
- const: csiphy0
- const: csiphy0_timer
- const: csiphy1
- const: csiphy1_timer
- const: csiphy2
- const: csiphy2_timer
- const: csiphy3
- const: csiphy3_timer
- const: csiphy4
- const: csiphy4_timer
- const: csiphy5
- const: csiphy5_timer
- const: csiphy_rx
- const: gcc_axi_hf
- const: qdss_debug_xo
- const: vfe0
- const: vfe0_fast_ahb
- const: vfe1
- const: vfe1_fast_ahb
- const: vfe2
- const: vfe2_fast_ahb
- const: vfe_lite
- const: vfe_lite_ahb
- const: vfe_lite_cphy_rx
- const: vfe_lite_csid
interrupts:
maxItems: 16
interrupt-names:
items:
- const: csid0
- const: csid1
- const: csid2
- const: csid_lite0
- const: csid_lite1
- const: csiphy0
- const: csiphy1
- const: csiphy2
- const: csiphy3
- const: csiphy4
- const: csiphy5
- const: vfe0
- const: vfe1
- const: vfe2
- const: vfe_lite0
- const: vfe_lite1
interconnects:
maxItems: 2
interconnect-names:
items:
- const: ahb
- const: hf_mnoc
iommus:
maxItems: 3
power-domains:
items:
- description: IFE0 GDSC - Image Front End, Global Distributed Switch Controller.
- description: IFE1 GDSC - Image Front End, Global Distributed Switch Controller.
- description: IFE2 GDSC - Image Front End, Global Distributed Switch Controller.
- description: Titan GDSC - Titan ISP Block, Global Distributed Switch Controller.
power-domain-names:
items:
- const: ife0
- const: ife1
- const: ife2
- const: top
ports:
$ref: /schemas/graph.yaml#/properties/ports
description:
CSI input ports.
patternProperties:
"^port@[0-5]$":
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description:
Input port for receiving CSI data from a CSIPHY.
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
data-lanes:
minItems: 1
maxItems: 4
bus-type:
enum:
- 1 # MEDIA_BUS_TYPE_CSI2_CPHY
- 4 # MEDIA_BUS_TYPE_CSI2_DPHY
required:
- data-lanes
vdd-csiphy01-0p9-supply:
description:
Phandle to a 0.9V regulator supply to CSIPHY0 and CSIPHY1 IP blocks.
vdd-csiphy01-1p2-supply:
description:
Phandle to a 1.2V regulator supply to CSIPHY0 and CSIPHY1 IP blocks.
vdd-csiphy24-0p9-supply:
description:
Phandle to a 0.9V regulator supply to CSIPHY2 and CSIPHY4 IP blocks.
vdd-csiphy24-1p2-supply:
description:
Phandle to a 1.2V regulator supply to CSIPHY2 and CSIPHY4 IP blocks.
vdd-csiphy35-0p9-supply:
description:
Phandle to a 0.9V regulator supply to CSIPHY3 and CSIPHY5 IP blocks.
vdd-csiphy35-1p2-supply:
description:
Phandle to a 1.2V regulator supply to CSIPHY3 and CSIPHY5 IP blocks.
required:
- compatible
- reg
- reg-names
- clocks
- clock-names
- interconnects
- interconnect-names
- interrupts
- interrupt-names
- iommus
- power-domains
- power-domain-names
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/qcom,sm8650-camcc.h>
#include <dt-bindings/clock/qcom,sm8650-gcc.h>
#include <dt-bindings/interconnect/qcom,sm8650-rpmh.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
isp@acb6000 {
compatible = "qcom,sm8650-camss";
reg = <0 0x0acb6000 0 0x1000>,
<0 0x0acb8000 0 0x1000>,
<0 0x0acba000 0 0x1000>,
<0 0x0acbc000 0 0x1000>,
<0 0x0accb000 0 0x1000>,
<0 0x0acd0000 0 0x1000>,
<0 0x0ace4000 0 0x2000>,
<0 0x0ace6000 0 0x2000>,
<0 0x0ace8000 0 0x2000>,
<0 0x0acea000 0 0x2000>,
<0 0x0acec000 0 0x2000>,
<0 0x0acee000 0 0x2000>,
<0 0x0ac62000 0 0xf000>,
<0 0x0ac71000 0 0xf000>,
<0 0x0ac80000 0 0xf000>,
<0 0x0accc000 0 0x2000>,
<0 0x0acd1000 0 0x2000>;
reg-names = "csid_wrapper",
"csid0",
"csid1",
"csid2",
"csid_lite0",
"csid_lite1",
"csiphy0",
"csiphy1",
"csiphy2",
"csiphy3",
"csiphy4",
"csiphy5",
"vfe0",
"vfe1",
"vfe2",
"vfe_lite0",
"vfe_lite1";
clocks = <&camcc CAM_CC_CAMNOC_AXI_RT_CLK>,
<&camcc CAM_CC_CPAS_AHB_CLK>,
<&camcc CAM_CC_CPAS_FAST_AHB_CLK>,
<&camcc CAM_CC_CPAS_IFE_0_CLK>,
<&camcc CAM_CC_CPAS_IFE_1_CLK>,
<&camcc CAM_CC_CPAS_IFE_2_CLK>,
<&camcc CAM_CC_CPAS_IFE_LITE_CLK>,
<&camcc CAM_CC_CSID_CLK>,
<&camcc CAM_CC_CSIPHY0_CLK>,
<&camcc CAM_CC_CSI0PHYTIMER_CLK>,
<&camcc CAM_CC_CSI1PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY1_CLK>,
<&camcc CAM_CC_CSI2PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY2_CLK>,
<&camcc CAM_CC_CSI3PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY3_CLK>,
<&camcc CAM_CC_CSI4PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY4_CLK>,
<&camcc CAM_CC_CSI5PHYTIMER_CLK>,
<&camcc CAM_CC_CSIPHY5_CLK>,
<&camcc CAM_CC_CSID_CSIPHY_RX_CLK>,
<&gcc GCC_CAMERA_HF_AXI_CLK>,
<&camcc CAM_CC_QDSS_DEBUG_XO_CLK>,
<&camcc CAM_CC_IFE_0_CLK>,
<&camcc CAM_CC_IFE_0_FAST_AHB_CLK>,
<&camcc CAM_CC_IFE_1_CLK>,
<&camcc CAM_CC_IFE_1_FAST_AHB_CLK>,
<&camcc CAM_CC_IFE_2_CLK>,
<&camcc CAM_CC_IFE_2_FAST_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_CLK>,
<&camcc CAM_CC_IFE_LITE_AHB_CLK>,
<&camcc CAM_CC_IFE_LITE_CPHY_RX_CLK>,
<&camcc CAM_CC_IFE_LITE_CSID_CLK>;
clock-names = "camnoc_axi",
"cpas_ahb",
"cpas_fast_ahb",
"cpas_vfe0",
"cpas_vfe1",
"cpas_vfe2",
"cpas_vfe_lite",
"csid",
"csiphy0",
"csiphy0_timer",
"csiphy1",
"csiphy1_timer",
"csiphy2",
"csiphy2_timer",
"csiphy3",
"csiphy3_timer",
"csiphy4",
"csiphy4_timer",
"csiphy5",
"csiphy5_timer",
"csiphy_rx",
"gcc_axi_hf",
"qdss_debug_xo",
"vfe0",
"vfe0_fast_ahb",
"vfe1",
"vfe1_fast_ahb",
"vfe2",
"vfe2_fast_ahb",
"vfe_lite",
"vfe_lite_ahb",
"vfe_lite_cphy_rx",
"vfe_lite_csid";
interrupts = <GIC_SPI 601 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 603 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 431 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 605 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 376 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 477 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 478 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 479 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 448 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 122 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 89 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 602 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 604 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 688 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 606 IRQ_TYPE_EDGE_RISING>,
<GIC_SPI 377 IRQ_TYPE_EDGE_RISING>;
interrupt-names = "csid0",
"csid1",
"csid2",
"csid_lite0",
"csid_lite1",
"csiphy0",
"csiphy1",
"csiphy2",
"csiphy3",
"csiphy4",
"csiphy5",
"vfe0",
"vfe1",
"vfe2",
"vfe_lite0",
"vfe_lite1";
interconnects = <&gem_noc MASTER_APPSS_PROC 0
&config_noc SLAVE_CAMERA_CFG 0>,
<&mmss_noc MASTER_CAMNOC_HF 0
&mc_virt SLAVE_EBI1 0>;
interconnect-names = "ahb", "hf_mnoc";
iommus = <&apps_smmu 0x800 0x20>,
<&apps_smmu 0x18a0 0x40>,
<&apps_smmu 0x1860 0x00>;
power-domains = <&camcc CAM_CC_IFE_0_GDSC>,
<&camcc CAM_CC_IFE_1_GDSC>,
<&camcc CAM_CC_IFE_2_GDSC>,
<&camcc CAM_CC_TITAN_TOP_GDSC>;
power-domain-names = "ife0", "ife1", "ife2", "top";
vdd-csiphy01-0p9-supply = <&vreg_0p9>;
vdd-csiphy01-1p2-supply = <&vreg_1p2>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@1 {
reg = <1>;
csiphy1_ep: endpoint {
data-lanes = <0 1>;
remote-endpoint = <&camera_sensor>;
};
};
};
};
};
Documentation/devicetree/bindings/media/qcom,x1e80100-camss.yaml
+1 -1
View File
@@ -124,7 +124,7 @@ properties:
vdd-csiphy-1p2-supply:
description:
Phandle to 1.8V regulator supply to a PHY.
Phandle to 1.2V regulator supply to a PHY.
ports:
$ref: /schemas/graph.yaml#/properties/ports
Documentation/devicetree/bindings/media/renesas,r9a09g057-ivc.yaml
+103
View File
@@ -0,0 +1,103 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/renesas,r9a09g057-ivc.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Renesas RZ/V2H(P) Input Video Control Block
maintainers:
- Daniel Scally <dan.scally@ideasonboard.com>
description:
The IVC block is a module that takes video frames from memory and feeds them
to the Image Signal Processor for processing.
properties:
compatible:
const: renesas,r9a09g057-ivc # RZ/V2H(P)
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: Input Video Control block register access clock
- description: Video input data AXI bus clock
- description: ISP system clock
clock-names:
items:
- const: reg
- const: axi
- const: isp
power-domains:
maxItems: 1
resets:
items:
- description: Input Video Control block register access reset
- description: Video input data AXI bus reset
- description: ISP core reset
reset-names:
items:
- const: reg
- const: axi
- const: isp
port:
$ref: /schemas/graph.yaml#/properties/port
description: Output parallel video bus
properties:
endpoint:
$ref: /schemas/graph.yaml#/properties/endpoint
required:
- compatible
- reg
- interrupts
- clocks
- clock-names
- power-domains
- resets
- reset-names
- port
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/renesas,r9a09g057-cpg.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
isp-input@16040000 {
compatible = "renesas,r9a09g057-ivc";
reg = <0x16040000 0x230>;
clocks = <&cpg CPG_MOD 0xe3>,
<&cpg CPG_MOD 0xe4>,
<&cpg CPG_MOD 0xe5>;
clock-names = "reg", "axi", "isp";
power-domains = <&cpg>;
resets = <&cpg 0xd4>,
<&cpg 0xd1>,
<&cpg 0xd3>;
reset-names = "reg", "axi", "isp";
interrupts = <GIC_SPI 861 IRQ_TYPE_EDGE_RISING>;
port {
ivc_out: endpoint {
remote-endpoint = <&isp_in>;
};
};
};
...
Documentation/devicetree/bindings/media/rockchip,px30-vip.yaml
+124
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@@ -0,0 +1,124 @@
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/media/rockchip,px30-vip.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Rockchip PX30 Video Input Processor (VIP)
maintainers:
- Mehdi Djait <mehdi.djait@linux.intel.com>
- Michael Riesch <michael.riesch@collabora.com>
description:
The Rockchip PX30 Video Input Processor (VIP) receives the data from a camera
sensor or CCIR656 encoder and transfers it into system main memory by AXI bus.
properties:
compatible:
const: rockchip,px30-vip
reg:
maxItems: 1
interrupts:
maxItems: 1
clocks:
items:
- description: ACLK
- description: HCLK
- description: PCLK
clock-names:
items:
- const: aclk
- const: hclk
- const: pclk
resets:
items:
- description: AXI
- description: AHB
- description: PCLK IN
reset-names:
items:
- const: axi
- const: ahb
- const: pclkin
power-domains:
maxItems: 1
ports:
$ref: /schemas/graph.yaml#/properties/ports
properties:
port@0:
$ref: /schemas/graph.yaml#/$defs/port-base
unevaluatedProperties: false
description: input port on the parallel interface
properties:
endpoint:
$ref: video-interfaces.yaml#
unevaluatedProperties: false
properties:
bus-type:
enum:
- 5 # MEDIA_BUS_TYPE_PARALLEL
- 6 # MEDIA_BUS_TYPE_BT656
required:
- bus-type
required:
- port@0
required:
- compatible
- reg
- interrupts
- clocks
- ports
additionalProperties: false
examples:
- |
#include <dt-bindings/clock/px30-cru.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/media/video-interfaces.h>
#include <dt-bindings/power/px30-power.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
video-capture@ff490000 {
compatible = "rockchip,px30-vip";
reg = <0x0 0xff490000 0x0 0x200>;
interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cru ACLK_CIF>, <&cru HCLK_CIF>, <&cru PCLK_CIF>;
clock-names = "aclk", "hclk", "pclk";
power-domains = <&power PX30_PD_VI>;
resets = <&cru SRST_CIF_A>, <&cru SRST_CIF_H>, <&cru SRST_CIF_PCLKIN>;
reset-names = "axi", "ahb", "pclkin";
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
cif_in: endpoint {
remote-endpoint = <&tw9900_out>;
bus-type = <MEDIA_BUS_TYPE_BT656>;
};
};
};
};
};

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