mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'mips_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer: - loongson64 irq rework - dmi support loongson - replace setup_irq() by request_irq() - jazz cleanups - minor cleanups and fixes * tag 'mips_5.7' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (44 commits) MIPS: ralink: mt7621: Fix soc_device introduction MIPS: Exclude more dsemul code when CONFIG_MIPS_FP_SUPPORT=n MIPS/tlbex: Fix LDDIR usage in setup_pw() for Loongson-3 MIPS: do not compile generic functions for CONFIG_CAVIUM_OCTEON_SOC MAINTAINERS: Update Loongson64 entry MIPS: Loongson64: Load built-in dtbs MIPS: Loongson64: Add generic dts dt-bindings: mips: Add loongson boards MIPS: Loongson64: Drop legacy IRQ code dt-bindings: interrupt-controller: Add Loongson-3 HTPIC irqchip: Add driver for Loongson-3 HyperTransport PIC controller dt-bindings: interrupt-controller: Add Loongson LIOINTC irqchip: loongson-liointc: Workaround LPC IRQ Errata irqchip: Add driver for Loongson I/O Local Interrupt Controller docs: mips: remove no longer needed au1xxx_ide.rst documentation MIPS: Alchemy: remove no longer used au1xxx_ide.h header ide: remove no longer used au1xxx-ide driver MIPS: Add support for Desktop Management Interface (DMI) firmware: dmi: Add macro SMBIOS_ENTRY_POINT_SCAN_START MIPS: ralink: mt7621: introduce 'soc_device' initialization ...
This commit is contained in:
Linus Torvalds
@@ -0,0 +1,59 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,htpic.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Loongson-3 HyperTransport Interrupt Controller
|
||||
|
||||
maintainers:
|
||||
- Jiaxun Yang <jiaxun.yang@flygoat.com>
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/interrupt-controller.yaml#
|
||||
|
||||
description: |
|
||||
This interrupt controller is found in the Loongson-3 family of chips to transmit
|
||||
interrupts from PCH PIC connected on HyperTransport bus.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: loongson,htpic-1.0
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
description: |
|
||||
Four parent interrupts that receive chained interrupts.
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
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htintc: interrupt-controller@1fb000080 {
|
||||
compatible = "loongson,htintc-1.0";
|
||||
reg = <0xfb000080 0x40>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&liointc>;
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
|
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<25 IRQ_TYPE_LEVEL_HIGH>,
|
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<26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,93 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: "http://devicetree.org/schemas/interrupt-controller/loongson,liointc.yaml#"
|
||||
$schema: "http://devicetree.org/meta-schemas/core.yaml#"
|
||||
|
||||
title: Loongson Local I/O Interrupt Controller
|
||||
|
||||
maintainers:
|
||||
- Jiaxun Yang <jiaxun.yang@flygoat.com>
|
||||
|
||||
description: |
|
||||
This interrupt controller is found in the Loongson-3 family of chips as the primary
|
||||
package interrupt controller which can route local I/O interrupt to interrupt lines
|
||||
of cores.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/interrupt-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: loongson,liointc-1.0
|
||||
- const: loongson,liointc-1.0a
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
interrupts:
|
||||
description:
|
||||
Interrupt source of the CPU interrupts.
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
interrupt-names:
|
||||
description: List of names for the parent interrupts.
|
||||
items:
|
||||
- const: int0
|
||||
- const: int1
|
||||
- const: int2
|
||||
- const: int3
|
||||
minItems: 1
|
||||
maxItems: 4
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 2
|
||||
|
||||
'loongson,parent_int_map':
|
||||
description: |
|
||||
This property points how the children interrupts will be mapped into CPU
|
||||
interrupt lines. Each cell refers to a parent interrupt line from 0 to 3
|
||||
and each bit in the cell refers to a children interrupt fron 0 to 31.
|
||||
If a CPU interrupt line didn't connected with liointc, then keep it's
|
||||
cell with zero.
|
||||
allOf:
|
||||
- $ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
- items:
|
||||
minItems: 4
|
||||
maxItems: 4
|
||||
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
- interrupt-controller
|
||||
- '#interrupt-cells'
|
||||
- 'loongson,parent_int_map'
|
||||
|
||||
|
||||
examples:
|
||||
- |
|
||||
iointc: interrupt-controller@3ff01400 {
|
||||
compatible = "loongson,liointc-1.0";
|
||||
reg = <0x3ff01400 0x64>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>, <3>;
|
||||
interrupt-names = "int0", "int1";
|
||||
|
||||
loongson,parent_int_map = <0xf0ffffff>, /* int0 */
|
||||
<0x0f000000>, /* int1 */
|
||||
<0x00000000>, /* int2 */
|
||||
<0x00000000>; /* int3 */
|
||||
|
||||
};
|
||||
|
||||
...
|
||||
@@ -0,0 +1,27 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mips/loongson/devices.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Loongson based Platforms Device Tree Bindings
|
||||
|
||||
maintainers:
|
||||
- Jiaxun Yang <jiaxun.yang@flygoat.com>
|
||||
description: |
|
||||
Devices with a Loongson CPU shall have the following properties.
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
const: '/'
|
||||
compatible:
|
||||
oneOf:
|
||||
|
||||
- description: Generic Loongson3 Quad Core + RS780E
|
||||
items:
|
||||
- const: loongson,loongson3-4core-rs780e
|
||||
|
||||
- description: Generic Loongson3 Octa Core + RS780E
|
||||
items:
|
||||
- const: loongson,loongson3-8core-rs780e
|
||||
...
|
||||
@@ -1,130 +0,0 @@
|
||||
.. include:: <isonum.txt>
|
||||
|
||||
======================
|
||||
MIPS AU1XXX IDE driver
|
||||
======================
|
||||
|
||||
Released 2005-07-15
|
||||
|
||||
About
|
||||
=====
|
||||
|
||||
This file describes the 'drivers/ide/au1xxx-ide.c', related files and the
|
||||
services they provide.
|
||||
|
||||
If you are short in patience and just want to know how to add your hard disc to
|
||||
the white or black list, go to the 'ADD NEW HARD DISC TO WHITE OR BLACK LIST'
|
||||
section.
|
||||
|
||||
|
||||
License
|
||||
=======
|
||||
|
||||
:Copyright: |copy| 2003-2005 AMD, Personal Connectivity Solutions
|
||||
|
||||
This program is free software; you can redistribute it and/or modify it under
|
||||
the terms of the GNU General Public License as published by the Free Software
|
||||
Foundation; either version 2 of the License, or (at your option) any later
|
||||
version.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED ``AS IS`` AND ANY EXPRESS OR IMPLIED WARRANTIES,
|
||||
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
|
||||
FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
|
||||
BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
You should have received a copy of the GNU General Public License along with
|
||||
this program; if not, write to the Free Software Foundation, Inc.,
|
||||
675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
|
||||
Note:
|
||||
for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
|
||||
Interface and Linux Device Driver" Application Note.
|
||||
|
||||
|
||||
Files, Configs and Compatibility
|
||||
================================
|
||||
|
||||
Two files are introduced:
|
||||
|
||||
a) 'arch/mips/include/asm/mach-au1x00/au1xxx_ide.h'
|
||||
contains : struct _auide_hwif
|
||||
|
||||
- timing parameters for PIO mode 0/1/2/3/4
|
||||
- timing parameters for MWDMA 0/1/2
|
||||
|
||||
b) 'drivers/ide/mips/au1xxx-ide.c'
|
||||
contains the functionality of the AU1XXX IDE driver
|
||||
|
||||
Following extra configs variables are introduced:
|
||||
|
||||
CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA
|
||||
- enable the PIO+DBDMA mode
|
||||
CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
|
||||
- enable the MWDMA mode
|
||||
|
||||
|
||||
Supported IDE Modes
|
||||
===================
|
||||
|
||||
The AU1XXX IDE driver supported all PIO modes - PIO mode 0/1/2/3/4 - and all
|
||||
MWDMA modes - MWDMA 0/1/2 -. There is no support for SWDMA and UDMA mode.
|
||||
|
||||
To change the PIO mode use the program hdparm with option -p, e.g.
|
||||
'hdparm -p0 [device]' for PIO mode 0. To enable the MWDMA mode use the option
|
||||
-X, e.g. 'hdparm -X32 [device]' for MWDMA mode 0.
|
||||
|
||||
|
||||
Performance Configurations
|
||||
==========================
|
||||
|
||||
If the used system doesn't need USB support enable the following kernel
|
||||
configs::
|
||||
|
||||
CONFIG_IDE=y
|
||||
CONFIG_BLK_DEV_IDE=y
|
||||
CONFIG_IDE_GENERIC=y
|
||||
CONFIG_BLK_DEV_IDEPCI=y
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
CONFIG_BLK_DEV_IDEDMA_PCI=y
|
||||
CONFIG_BLK_DEV_IDE_AU1XXX=y
|
||||
CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
|
||||
CONFIG_BLK_DEV_IDEDMA=y
|
||||
|
||||
Also define 'IDE_AU1XXX_BURSTMODE' in 'drivers/ide/mips/au1xxx-ide.c' to enable
|
||||
the burst support on DBDMA controller.
|
||||
|
||||
If the used system need the USB support enable the following kernel configs for
|
||||
high IDE to USB throughput.
|
||||
|
||||
::
|
||||
|
||||
CONFIG_IDE_GENERIC=y
|
||||
CONFIG_BLK_DEV_IDEPCI=y
|
||||
CONFIG_BLK_DEV_GENERIC=y
|
||||
CONFIG_BLK_DEV_IDEDMA_PCI=y
|
||||
CONFIG_BLK_DEV_IDE_AU1XXX=y
|
||||
CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA=y
|
||||
CONFIG_BLK_DEV_IDEDMA=y
|
||||
|
||||
Also undefine 'IDE_AU1XXX_BURSTMODE' in 'drivers/ide/mips/au1xxx-ide.c' to
|
||||
disable the burst support on DBDMA controller.
|
||||
|
||||
|
||||
Acknowledgments
|
||||
===============
|
||||
|
||||
These drivers wouldn't have been done without the base of kernel 2.4.x AU1XXX
|
||||
IDE driver from AMD.
|
||||
|
||||
Additional input also from:
|
||||
Matthias Lenk <matthias.lenk@amd.com>
|
||||
|
||||
Happy hacking!
|
||||
|
||||
Enrico Walther <enrico.walther@amd.com>
|
||||
@@ -10,8 +10,6 @@ MIPS-specific Documentation
|
||||
|
||||
ingenic-tcu
|
||||
|
||||
au1xxx_ide
|
||||
|
||||
.. only:: subproject and html
|
||||
|
||||
Indices
|
||||
|
||||
@@ -11202,6 +11202,7 @@ S: Maintained
|
||||
F: arch/mips/loongson64/
|
||||
F: arch/mips/include/asm/mach-loongson64/
|
||||
F: drivers/platform/mips/cpu_hwmon.c
|
||||
F: drivers/irqchip/irq-loongson*
|
||||
F: drivers/*/*loongson3*
|
||||
F: drivers/*/*/*loongson3*
|
||||
|
||||
|
||||
+28
-3
@@ -486,9 +486,11 @@ config MACH_LOONGSON64
|
||||
select SYS_SUPPORTS_HIGHMEM
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_SUPPORTS_ZBOOT
|
||||
select LOONGSON_MC146818
|
||||
select ZONE_DMA32
|
||||
select NUMA
|
||||
select COMMON_CLK
|
||||
select USE_OF
|
||||
select BUILTIN_DTB
|
||||
help
|
||||
This enables the support of Loongson-2/3 family of machines.
|
||||
|
||||
@@ -973,6 +975,9 @@ config CAVIUM_OCTEON_SOC
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
select SYS_HAS_CPU_CAVIUM_OCTEON
|
||||
select HAVE_PCI
|
||||
select HAVE_PLAT_DELAY
|
||||
select HAVE_PLAT_FW_INIT_CMDLINE
|
||||
select HAVE_PLAT_MEMCPY
|
||||
select ZONE_DMA32
|
||||
select HOLES_IN_ZONE
|
||||
select GPIOLIB
|
||||
@@ -1229,6 +1234,15 @@ config GENERIC_ISA_DMA_SUPPORT_BROKEN
|
||||
bool
|
||||
select GENERIC_ISA_DMA
|
||||
|
||||
config HAVE_PLAT_DELAY
|
||||
bool
|
||||
|
||||
config HAVE_PLAT_FW_INIT_CMDLINE
|
||||
bool
|
||||
|
||||
config HAVE_PLAT_MEMCPY
|
||||
bool
|
||||
|
||||
config ISA_DMA_API
|
||||
bool
|
||||
|
||||
@@ -2676,7 +2690,7 @@ config NUMA
|
||||
Say Y to compile the kernel to support NUMA (Non-Uniform Memory
|
||||
Access). This option improves performance on systems with more
|
||||
than two nodes; on two node systems it is generally better to
|
||||
leave it disabled; on single node systems disable this option
|
||||
leave it disabled; on single node systems leave this option
|
||||
disabled.
|
||||
|
||||
config SYS_SUPPORTS_NUMA
|
||||
@@ -2758,6 +2772,17 @@ config HW_PERF_EVENTS
|
||||
Enable hardware performance counter support for perf events. If
|
||||
disabled, perf events will use software events only.
|
||||
|
||||
config DMI
|
||||
bool "Enable DMI scanning"
|
||||
depends on MACH_LOONGSON64
|
||||
select DMI_SCAN_MACHINE_NON_EFI_FALLBACK
|
||||
default y
|
||||
help
|
||||
Enabled scanning of DMI to identify machine quirks. Say Y
|
||||
here unless you have verified that your setup is not
|
||||
affected by entries in the DMI blacklist. Required by PNP
|
||||
BIOS code.
|
||||
|
||||
config SMP
|
||||
bool "Multi-Processing support"
|
||||
depends on SYS_SUPPORTS_SMP
|
||||
@@ -3070,7 +3095,7 @@ endchoice
|
||||
choice
|
||||
prompt "Kernel command line type" if !CMDLINE_OVERRIDE
|
||||
default MIPS_CMDLINE_FROM_DTB if USE_OF && !ATH79 && !MACH_INGENIC && \
|
||||
!MIPS_MALTA && \
|
||||
!MACH_LOONGSON64 && !MIPS_MALTA && \
|
||||
!CAVIUM_OCTEON_SOC
|
||||
default MIPS_CMDLINE_FROM_BOOTLOADER
|
||||
|
||||
|
||||
@@ -72,13 +72,6 @@ static struct clock_event_device au1x_rtcmatch2_clockdev = {
|
||||
.cpumask = cpu_possible_mask,
|
||||
};
|
||||
|
||||
static struct irqaction au1x_rtcmatch2_irqaction = {
|
||||
.handler = au1x_rtcmatch2_irq,
|
||||
.flags = IRQF_TIMER,
|
||||
.name = "timer",
|
||||
.dev_id = &au1x_rtcmatch2_clockdev,
|
||||
};
|
||||
|
||||
static int __init alchemy_time_init(unsigned int m2int)
|
||||
{
|
||||
struct clock_event_device *cd = &au1x_rtcmatch2_clockdev;
|
||||
@@ -130,7 +123,9 @@ static int __init alchemy_time_init(unsigned int m2int)
|
||||
cd->min_delta_ns = clockevent_delta2ns(9, cd);
|
||||
cd->min_delta_ticks = 9; /* ~0.28ms */
|
||||
clockevents_register_device(cd);
|
||||
setup_irq(m2int, &au1x_rtcmatch2_irqaction);
|
||||
if (request_irq(m2int, au1x_rtcmatch2_irq, IRQF_TIMER, "timer",
|
||||
&au1x_rtcmatch2_clockdev))
|
||||
pr_err("Failed to register timer interrupt\n");
|
||||
|
||||
printk(KERN_INFO "Alchemy clocksource installed\n");
|
||||
|
||||
|
||||
+8
-8
@@ -83,12 +83,6 @@ static struct irq_chip ar7_sec_irq_type = {
|
||||
.irq_ack = ar7_ack_sec_irq,
|
||||
};
|
||||
|
||||
static struct irqaction ar7_cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "AR7 cascade interrupt",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static void __init ar7_irq_init(int base)
|
||||
{
|
||||
int i;
|
||||
@@ -116,8 +110,14 @@ static void __init ar7_irq_init(int base)
|
||||
handle_level_irq);
|
||||
}
|
||||
|
||||
setup_irq(2, &ar7_cascade_action);
|
||||
setup_irq(ar7_irq_base, &ar7_cascade_action);
|
||||
if (request_irq(2, no_action, IRQF_NO_THREAD, "AR7 cascade interrupt",
|
||||
NULL))
|
||||
pr_err("Failed to request irq 2 (AR7 cascade interrupt)\n");
|
||||
if (request_irq(ar7_irq_base, no_action, IRQF_NO_THREAD,
|
||||
"AR7 cascade interrupt", NULL)) {
|
||||
pr_err("Failed to request irq %d (AR7 cascade interrupt)\n",
|
||||
ar7_irq_base);
|
||||
}
|
||||
set_c0_status(IE_IRQ0);
|
||||
}
|
||||
|
||||
|
||||
@@ -64,11 +64,6 @@ static irqreturn_t ar2315_ahb_err_handler(int cpl, void *dev_id)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction ar2315_ahb_err_interrupt = {
|
||||
.handler = ar2315_ahb_err_handler,
|
||||
.name = "ar2315-ahb-error",
|
||||
};
|
||||
|
||||
static void ar2315_misc_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
u32 pending = ar2315_rst_reg_read(AR2315_ISR) &
|
||||
@@ -159,7 +154,9 @@ void __init ar2315_arch_init_irq(void)
|
||||
panic("Failed to add IRQ domain");
|
||||
|
||||
irq = irq_create_mapping(domain, AR2315_MISC_IRQ_AHB);
|
||||
setup_irq(irq, &ar2315_ahb_err_interrupt);
|
||||
if (request_irq(irq, ar2315_ahb_err_handler, 0, "ar2315-ahb-error",
|
||||
NULL))
|
||||
pr_err("Failed to register ar2315-ahb-error interrupt\n");
|
||||
|
||||
irq_set_chained_handler_and_data(AR2315_IRQ_MISC,
|
||||
ar2315_misc_irq_handler, domain);
|
||||
|
||||
@@ -68,11 +68,6 @@ static irqreturn_t ar5312_ahb_err_handler(int cpl, void *dev_id)
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static struct irqaction ar5312_ahb_err_interrupt = {
|
||||
.handler = ar5312_ahb_err_handler,
|
||||
.name = "ar5312-ahb-error",
|
||||
};
|
||||
|
||||
static void ar5312_misc_irq_handler(struct irq_desc *desc)
|
||||
{
|
||||
u32 pending = ar5312_rst_reg_read(AR5312_ISR) &
|
||||
@@ -154,7 +149,9 @@ void __init ar5312_arch_init_irq(void)
|
||||
panic("Failed to add IRQ domain");
|
||||
|
||||
irq = irq_create_mapping(domain, AR5312_MISC_IRQ_AHB_PROC);
|
||||
setup_irq(irq, &ar5312_ahb_err_interrupt);
|
||||
if (request_irq(irq, ar5312_ahb_err_handler, 0, "ar5312-ahb-error",
|
||||
NULL))
|
||||
pr_err("Failed to register ar5312-ahb-error interrupt\n");
|
||||
|
||||
irq_set_chained_handler_and_data(AR5312_IRQ_MISC,
|
||||
ar5312_misc_irq_handler, domain);
|
||||
|
||||
@@ -15,7 +15,7 @@
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/err.h>
|
||||
#include <linux/clk.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/of_clk.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/irqchip.h>
|
||||
|
||||
|
||||
+16
-25
@@ -399,26 +399,6 @@ static struct irq_chip bcm63xx_external_irq_chip = {
|
||||
.irq_set_type = bcm63xx_external_irq_set_type,
|
||||
};
|
||||
|
||||
static struct irqaction cpu_ip2_cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "cascade_ip2",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
#ifdef CONFIG_SMP
|
||||
static struct irqaction cpu_ip3_cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "cascade_ip3",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
#endif
|
||||
|
||||
static struct irqaction cpu_ext_cascade_action = {
|
||||
.handler = no_action,
|
||||
.name = "cascade_extirq",
|
||||
.flags = IRQF_NO_THREAD,
|
||||
};
|
||||
|
||||
static void bcm63xx_init_irq(void)
|
||||
{
|
||||
int irq_bits;
|
||||
@@ -531,7 +511,7 @@ static void bcm63xx_init_irq(void)
|
||||
|
||||
void __init arch_init_irq(void)
|
||||
{
|
||||
int i;
|
||||
int i, irq;
|
||||
|
||||
bcm63xx_init_irq();
|
||||
mips_cpu_irq_init();
|
||||
@@ -544,14 +524,25 @@ void __init arch_init_irq(void)
|
||||
handle_edge_irq);
|
||||
|
||||
if (!is_ext_irq_cascaded) {
|
||||
for (i = 3; i < 3 + ext_irq_count; ++i)
|
||||
setup_irq(MIPS_CPU_IRQ_BASE + i, &cpu_ext_cascade_action);
|
||||
for (i = 3; i < 3 + ext_irq_count; ++i) {
|
||||
irq = MIPS_CPU_IRQ_BASE + i;
|
||||
if (request_irq(irq, no_action, IRQF_NO_THREAD,
|
||||
"cascade_extirq", NULL)) {
|
||||
pr_err("Failed to request irq %d (cascade_extirq)\n",
|
||||
irq);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
setup_irq(MIPS_CPU_IRQ_BASE + 2, &cpu_ip2_cascade_action);
|
||||
irq = MIPS_CPU_IRQ_BASE + 2;
|
||||
if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade_ip2", NULL))
|
||||
pr_err("Failed to request irq %d (cascade_ip2)\n", irq);
|
||||
#ifdef CONFIG_SMP
|
||||
if (is_ext_irq_cascaded) {
|
||||
setup_irq(MIPS_CPU_IRQ_BASE + 3, &cpu_ip3_cascade_action);
|
||||
irq = MIPS_CPU_IRQ_BASE + 3;
|
||||
if (request_irq(irq, no_action, IRQF_NO_THREAD, "cascade_ip3",
|
||||
NULL))
|
||||
pr_err("Failed to request irq %d (cascade_ip3)\n", irq);
|
||||
bcm63xx_internal_irq_chip.irq_set_affinity =
|
||||
bcm63xx_internal_set_affinity;
|
||||
|
||||
|
||||
@@ -10,11 +10,11 @@
|
||||
#include <linux/init.h>
|
||||
#include <linux/bitops.h>
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/clk-provider.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/io.h>
|
||||
#include <linux/of.h>
|
||||
#include <linux/of_clk.h>
|
||||
#include <linux/of_fdt.h>
|
||||
#include <linux/of_platform.h>
|
||||
#include <linux/libfdt.h>
|
||||
|
||||
@@ -4,6 +4,7 @@ subdir-y += cavium-octeon
|
||||
subdir-y += img
|
||||
subdir-y += ingenic
|
||||
subdir-y += lantiq
|
||||
subdir-y += loongson
|
||||
subdir-y += mscc
|
||||
subdir-y += mti
|
||||
subdir-y += netlogic
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
#include "jz4780.dtsi"
|
||||
#include <dt-bindings/clock/ingenic,tcu.h>
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
#include <dt-bindings/regulator/active-semi,8865-regulator.h>
|
||||
|
||||
@@ -27,6 +28,17 @@
|
||||
0x30000000 0x30000000>;
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
sw1 {
|
||||
label = "ci20:sw1";
|
||||
linux,code = <KEY_F13>;
|
||||
gpios = <&gpd 17 GPIO_ACTIVE_HIGH>;
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
@@ -58,10 +70,17 @@
|
||||
eth0_power: fixedregulator@0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "eth0_power";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
ir: ir {
|
||||
compatible = "gpio-ir-receiver";
|
||||
gpios = <&gpe 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan0_power: fixedregulator@1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "wlan0_power";
|
||||
|
||||
@@ -0,0 +1,4 @@
|
||||
# SPDX_License_Identifier: GPL_2.0
|
||||
dtb-$(CONFIG_MACH_LOONGSON64) += loongson3_4core_rs780e.dtb loongson3_8core_rs780e.dtb
|
||||
|
||||
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
|
||||
@@ -0,0 +1,64 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
#include <dt-bindings/interrupt-controller/irq.h>
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
cpuintc: interrupt-controller {
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupt-controller;
|
||||
compatible = "mti,cpu-interrupt-controller";
|
||||
};
|
||||
|
||||
package0: bus@1fe00000 {
|
||||
compatible = "simple-bus";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0 0x1fe00000 0 0x1fe00000 0x100000
|
||||
0 0x3ff00000 0 0x3ff00000 0x100000
|
||||
/* 3A HT Config Space */
|
||||
0xefd 0xfb000000 0xefd 0xfb000000 0x10000000
|
||||
/* 3B HT Config Space */
|
||||
0x1efd 0xfb000000 0x1efd 0xfb000000 0x10000000>;
|
||||
|
||||
liointc: interrupt-controller@3ff01400 {
|
||||
compatible = "loongson,liointc-1.0";
|
||||
reg = <0 0x3ff01400 0x64>;
|
||||
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <2>;
|
||||
|
||||
interrupt-parent = <&cpuintc>;
|
||||
interrupts = <2>, <3>;
|
||||
interrupt-names = "int0", "int1";
|
||||
|
||||
loongson,parent_int_map = <0xf0ffffff>, /* int0 */
|
||||
<0x0f000000>, /* int1 */
|
||||
<0x00000000>, /* int2 */
|
||||
<0x00000000>; /* int3 */
|
||||
|
||||
};
|
||||
|
||||
cpu_uart0: serial@1fe001e0 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0 0x1fe001e0 0x8>;
|
||||
clock-frequency = <33000000>;
|
||||
interrupt-parent = <&liointc>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
no-loopback-test;
|
||||
};
|
||||
|
||||
cpu_uart1: serial@1fe001e8 {
|
||||
status = "disabled";
|
||||
compatible = "ns16550a";
|
||||
reg = <0 0x1fe001e8 0x8>;
|
||||
clock-frequency = <33000000>;
|
||||
interrupts = <10 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-parent = <&liointc>;
|
||||
no-loopback-test;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,25 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "loongson3-package.dtsi"
|
||||
#include "rs780e-pch.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "loongson,loongson3-4core-rs780e";
|
||||
};
|
||||
|
||||
&package0 {
|
||||
htpic: interrupt-controller@efdfb000080 {
|
||||
compatible = "loongson,htpic-1.0";
|
||||
reg = <0xefd 0xfb000080 0x40>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&liointc>;
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,25 @@
|
||||
// SPDX-License-Identifier: GPL-2.0
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
#include "loongson3-package.dtsi"
|
||||
#include "rs780e-pch.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "loongson,loongson3-8core-rs780e";
|
||||
};
|
||||
|
||||
&package0 {
|
||||
htpic: interrupt-controller@1efdfb000080 {
|
||||
compatible = "loongson,htpic-1.0";
|
||||
reg = <0x1efd 0xfb000080 0x40>;
|
||||
interrupt-controller;
|
||||
#interrupt-cells = <1>;
|
||||
|
||||
interrupt-parent = <&liointc>;
|
||||
interrupts = <24 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<25 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<26 IRQ_TYPE_LEVEL_HIGH>,
|
||||
<27 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
};
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user