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Merge tag 'gpio-updates-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux

Browse Source 
Pull gpio updates from Bartosz Golaszewski:
 "There are two new drivers and some changes to GPIO core but mostly
  just GPIO driver updates across a wide array of files, adding support
  for new models as well as various refactoring changes. Nothing
  controversial and everything has spent a good measure of time in
  linux-next.

  GPIOLIB core:
   - shrink the GPIO bus driver stub code
   - rework software node support for "undefined" software nodes
   - provide and use devm_fwnode_gpiod_get_optional()
   - only compile the OF quirk for MT2701 when needed

  New drivers:
   - add the GPIO driver for ROHM bd72720
   - add the gpio-line-mux driver providing 1-to-many mapping for a
     single real GPIO

  Driver changes:
   - refactor gpio-pca9570: use lock guard, add missing headers, use
     devres consistently
   - add support for a new model (G7 Aspeed sgpiom) to the aspeed-sgpio
     driver along with some prerequisite refactoring
   - use device_get_match_data() where applicable and save some lines
   - add support for more models to gpio-cadence
   - add the compatible property to reset-gpio and use it in shared GPIO
     management
   - drop unnecessary use of irqd_get_trigger_type() in gpio-max77759
   - add support for a new variant to gpio-pca953x
   - extend build coverage with COMPILE_TEST for more drivers
   - constify configfs structures in gpio-sim and gpio-virtuser
   - add support for the K3 SoC to gpio-spacemit
   - implement the missing .get_direction() callback in gpio-max77620
   - add support for Tegra264 to gpio-tegra186
   - drop unneeded MODULE_ALIAS() from gpio-menz127

  DT bindings:
   - document support for the opencores GPIO controller in gpio-mmio
   - document new variants for gpio-pca953x

  Documentation:
   - extensively describe interrupt source detection for gpio-pca953x
     and add more models to the list of supported variants"

* tag 'gpio-updates-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux: (59 commits)
  gpio: tegra186: Add support for Tegra264
  dt-bindings: gpio: Add Tegra264 support
  gpio: spacemit-k1: Use PDR for pin direction, not SDR/CDR
  gpio: max77620: Implement .get_direction() callback
  gpio: aspeed-sgpio: Support G7 Aspeed sgpiom controller
  dt-bindings: gpio: aspeed,sgpio: Support ast2700
  gpio: aspeed-sgpio: Convert IRQ functions to use llops callbacks
  gpio: aspeed-sgpio: Create llops to handle hardware access
  gpio: aspeed-sgpio: Remove unused bank name field
  gpio: aspeed-sgpio: Change the macro to support deferred probe
  regulator: bd71815: switch to devm_fwnode_gpiod_get_optional
  gpiolib: introduce devm_fwnode_gpiod_get_optional() wrapper
  gpio: mmio: Add compatible for opencores GPIO
  dt-bindings: gpio-mmio: Correct opencores GPIO
  gpio: pca9570: use lock guards
  gpio: pca9570: Don't use "proxy" headers
  gpio: pca9570: Use devm_mutex_init() for mutex initialization
  MAINTAINERS: Add ROHM BD72720 PMIC
  power: supply: bd71828-power: Support ROHM BD72720
  power: supply: bd71828: Support wider register addresses
  ...
This commit is contained in:
Linus Torvalds
2026-02-11 10:53:39 -08:00
parent 893ace4df0 af9b4a56f0
commit d701782152
51 changed files with 4172 additions and 432 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/gpio/aspeed,sgpio.yaml
+3 -1
View File
@@ -10,7 +10,8 @@ maintainers:
- Andrew Jeffery <andrew@aj.id.au>
description:
This SGPIO controller is for ASPEED AST2400, AST2500 and AST2600 SoC,
This SGPIO controller is for ASPEED AST2400, AST2500, AST2600 and AST2700 SoC,
AST2700 have two sgpio master both with 256 pins,
AST2600 have two sgpio master one with 128 pins another one with 80 pins,
AST2500/AST2400 have one sgpio master with 80 pins. Each of the Serial
GPIO pins can be programmed to support the following options
@@ -27,6 +28,7 @@ properties:
- aspeed,ast2400-sgpio
- aspeed,ast2500-sgpio
- aspeed,ast2600-sgpiom
- aspeed,ast2700-sgpiom
reg:
maxItems: 1
Documentation/devicetree/bindings/gpio/gpio-line-mux.yaml
+107
View File
@@ -0,0 +1,107 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/gpio/gpio-line-mux.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: GPIO line mux
maintainers:
- Jonas Jelonek <jelonek.jonas@gmail.com>
description: |
A GPIO controller to provide virtual GPIOs for a 1-to-many input-only mapping
backed by a single shared GPIO and a multiplexer. A simple illustrated
example is:
+----- A
IN /
<-----o------- B
/ |\
| | +----- C
| | \
| | +--- D
| |
M1 M0
MUX CONTROL
M1 M0 IN
0 0 A
0 1 B
1 0 C
1 1 D
This can be used in case a real GPIO is connected to multiple inputs and
controlled by a multiplexer, and another subsystem/driver does not work
directly with the multiplexer subsystem.
properties:
compatible:
const: gpio-line-mux
gpio-controller: true
"#gpio-cells":
const: 2
gpio-line-mux-states:
description: Mux states corresponding to the virtual GPIOs.
$ref: /schemas/types.yaml#/definitions/uint32-array
gpio-line-names: true
mux-controls:
maxItems: 1
description:
Phandle to the multiplexer to control access to the GPIOs.
ngpios: false
muxed-gpios:
maxItems: 1
description:
GPIO which is the '1' in 1-to-many and is shared by the virtual GPIOs
and controlled via the mux.
required:
- compatible
- gpio-controller
- gpio-line-mux-states
- mux-controls
- muxed-gpios
additionalProperties: false
examples:
- |
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/mux/mux.h>
sfp_gpio_mux: mux-controller-1 {
compatible = "gpio-mux";
mux-gpios = <&gpio0 0 GPIO_ACTIVE_HIGH>,
<&gpio0 1 GPIO_ACTIVE_HIGH>;
#mux-control-cells = <0>;
idle-state = <MUX_IDLE_AS_IS>;
};
sfp1_gpio: sfp-gpio-1 {
compatible = "gpio-line-mux";
gpio-controller;
#gpio-cells = <2>;
mux-controls = <&sfp_gpio_mux>;
muxed-gpios = <&gpio0 2 GPIO_ACTIVE_HIGH>;
gpio-line-mux-states = <0>, <1>, <3>;
};
sfp1: sfp-p1 {
compatible = "sff,sfp";
i2c-bus = <&sfp1_i2c>;
los-gpios = <&sfp1_gpio 0 GPIO_ACTIVE_HIGH>;
mod-def0-gpios = <&sfp1_gpio 1 GPIO_ACTIVE_LOW>;
tx-fault-gpios = <&sfp1_gpio 2 GPIO_ACTIVE_HIGH>;
};
Documentation/devicetree/bindings/gpio/gpio-mmio.yaml
+3 -2
View File
@@ -20,9 +20,10 @@ properties:
compatible:
enum:
- brcm,bcm6345-gpio
- ni,169445-nand-gpio
- wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
- intel,ixp4xx-expansion-bus-mmio-gpio
- ni,169445-nand-gpio
- opencores,gpio
- wd,mbl-gpio # Western Digital MyBook Live memory-mapped GPIO controller
big-endian: true
Documentation/devicetree/bindings/gpio/gpio-pca95xx.yaml
+2
View File
@@ -74,6 +74,8 @@ properties:
- ti,tca9538
- ti,tca9539
- ti,tca9554
- ti,tcal6408
- ti,tcal6416
reg:
maxItems: 1
Documentation/devicetree/bindings/gpio/nvidia,tegra186-gpio.yaml
+22
View File
@@ -86,6 +86,9 @@ properties:
- nvidia,tegra234-gpio
- nvidia,tegra234-gpio-aon
- nvidia,tegra256-gpio
- nvidia,tegra264-gpio
- nvidia,tegra264-gpio-uphy
- nvidia,tegra264-gpio-aon
reg-names:
items:
@@ -110,6 +113,10 @@ properties:
ports, in the order the HW manual describes them. The number of entries
required varies depending on compatible value.
wakeup-parent:
description: Phandle to the parent interrupt controller used for wake-up. On
Tegra, this typically references the PMC interrupt controller.
gpio-controller: true
gpio-ranges:
@@ -157,6 +164,8 @@ allOf:
- nvidia,tegra194-gpio
- nvidia,tegra234-gpio
- nvidia,tegra256-gpio
- nvidia,tegra264-gpio
- nvidia,tegra264-gpio-uphy
then:
properties:
interrupts:
@@ -171,12 +180,25 @@ allOf:
- nvidia,tegra186-gpio-aon
- nvidia,tegra194-gpio-aon
- nvidia,tegra234-gpio-aon
- nvidia,tegra264-gpio-aon
then:
properties:
interrupts:
minItems: 1
maxItems: 4
- if:
properties:
compatible:
contains:
enum:
- nvidia,tegra264-gpio
- nvidia,tegra264-gpio-uphy
- nvidia,tegra264-gpio-aon
then:
required:
- wakeup-parent
required:
- compatible
- reg
Documentation/devicetree/bindings/gpio/spacemit,k1-gpio.yaml
+3 -1
View File
@@ -19,7 +19,9 @@ properties:
pattern: "^gpio@[0-9a-f]+$"
compatible:
const: spacemit,k1-gpio
enum:
- spacemit,k1-gpio
- spacemit,k3-gpio
reg:
maxItems: 1
Documentation/devicetree/bindings/leds/rohm,bd71828-leds.yaml
+4 -3
View File
@@ -10,11 +10,12 @@ maintainers:
- Matti Vaittinen <mazziesaccount@gmail.com>
description: |
This module is part of the ROHM BD71828 MFD device. For more details
see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml.
This module is part of the ROHM BD71828 and BD72720 MFD device. For more
details see Documentation/devicetree/bindings/mfd/rohm,bd71828-pmic.yaml
and Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml
The LED controller is represented as a sub-node of the PMIC node on the device
tree.
tree. This should be located under "leds" - node in PMIC node.
The device has two LED outputs referred as GRNLED and AMBLED in data-sheet.
Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml
+339
View File
@@ -0,0 +1,339 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/mfd/rohm,bd72720-pmic.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROHM BD72720 Power Management Integrated Circuit
maintainers:
- Matti Vaittinen <mazziesaccount@gmail.com>
description:
BD72720 is a single-chip power management IC for battery-powered portable
devices. The BD72720 integrates 10 bucks and 11 LDOs, and a 3000 mA
switching charger. The IC also includes a Coulomb counter, a real-time
clock (RTC), GPIOs and a 32.768 kHz clock gate.
# In addition to the properties found from the charger node, the ROHM BD72720
# uses properties from a static battery node. Please see the:
# Documentation/devicetree/bindings/power/supply/battery.yaml
#
# Following properties are used
# when present:
#
# charge-full-design-microamp-hours: Battry capacity in mAh
# voltage-max-design-microvolt: Maximum voltage
# voltage-min-design-microvolt: Minimum voltage system is still operating.
# degrade-cycle-microamp-hours: Capacity lost due to aging at each full
# charge cycle.
# ocv-capacity-celsius: Array of OCV table temperatures. 1/table.
# ocv-capacity-table-<N>: Table of OCV voltage/SOC pairs. Corresponds
# N.th temperature in ocv-capacity-celsius
#
# volt-drop-thresh-microvolt: Threshold for starting the VDR correction
# volt-drop-soc: Table of capacity values matching the
# values in VDR tables.
#
# volt-drop-temperatures-millicelsius: Temperatures corresponding to the volage
# drop values given in volt-drop-[0-9]-microvolt
#
# volt-drop-[0-9]-microvolt: VDR table for a temperature specified in
# volt-drop-temperatures-millicelsius
#
# VDR tables are (usually) determined for a specific battery by ROHM.
# The battery node would then be referred from the charger node:
#
# monitored-battery = <&battery>;
properties:
compatible:
const: rohm,bd72720
reg:
description:
I2C slave address.
maxItems: 1
interrupts:
maxItems: 1
gpio-controller: true
"#gpio-cells":
const: 2
description:
The first cell is the pin number and the second cell is used to specify
flags. See the gpio binding document for more information.
clocks:
maxItems: 1
"#clock-cells":
const: 0
clock-output-names:
const: bd71828-32k-out
rohm,clkout-open-drain:
description: clk32kout mode. Set to 1 for "open-drain" or 0 for "cmos".
$ref: /schemas/types.yaml#/definitions/uint32
maximum: 1
rohm,charger-sense-resistor-micro-ohms:
minimum: 10000
maximum: 50000
description:
BD72720 has a SAR ADC for measuring charging currents. External sense
resistor (RSENSE in data sheet) should be used. If some other but
30 mOhm resistor is used the resistance value should be given here in
micro Ohms.
regulators:
$ref: /schemas/regulator/rohm,bd72720-regulator.yaml
description:
List of child nodes that specify the regulators.
leds:
$ref: /schemas/leds/rohm,bd71828-leds.yaml
rohm,pin-fault_b:
$ref: /schemas/types.yaml#/definitions/string
description:
BD72720 has an OTP option to use fault_b-pin for different
purposes. Set this property accordingly. OTP options are
OTP0 - bi-directional FAULT_B or READY indicator depending on a
'sub option'
OTP1 - GPO
OTP2 - Power sequencer output.
enum:
- faultb
- readyind
- gpo
- pwrseq
patternProperties:
"^rohm,pin-dvs[0-1]$":
$ref: /schemas/types.yaml#/definitions/string
description:
BD72720 has 4 different OTP options to determine the use of dvs<X>-pins.
OTP0 - regulator RUN state control.
OTP1 - GPI.
OTP2 - GPO.
OTP3 - Power sequencer output.
This property specifies the use of the pin.
enum:
- dvs-input
- gpi
- gpo
- pwrseq
"^rohm,pin-exten[0-1]$":
$ref: /schemas/types.yaml#/definitions/string
description: BD72720 has an OTP option to use exten0-pin for different
purposes. Set this property accordingly.
OTP0 - GPO
OTP1 - Power sequencer output.
enum:
- gpo
- pwrseq
required:
- compatible
- reg
- interrupts
- clocks
- "#clock-cells"
- regulators
- gpio-controller
- "#gpio-cells"
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/leds/common.h>
i2c {
#address-cells = <1>;
#size-cells = <0>;
pmic: pmic@4b {
compatible = "rohm,bd72720";
reg = <0x4b>;
interrupt-parent = <&gpio1>;
interrupts = <29 IRQ_TYPE_LEVEL_LOW>;
clocks = <&osc 0>;
#clock-cells = <0>;
clock-output-names = "bd71828-32k-out";
gpio-controller;
#gpio-cells = <2>;
rohm,pin-dvs0 = "gpi";
rohm,pin-dvs1 = "gpi";
rohm,pin-exten0 = "gpo";
rohm,pin-exten1 = "gpo";
rohm,pin-fault_b = "faultb";
rohm,charger-sense-resistor-micro-ohms = <10000>;
regulators {
buck1 {
regulator-name = "buck1";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <2500>;
};
buck2 {
regulator-name = "buck2";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <2500>;
};
buck3 {
regulator-name = "buck3";
regulator-min-microvolt = <1200000>;
regulator-max-microvolt = <2000000>;
};
buck4 {
regulator-name = "buck4";
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <1800000>;
};
buck5 {
regulator-name = "buck5";
regulator-min-microvolt = <2500000>;
regulator-max-microvolt = <3300000>;
};
buck6 {
regulator-name = "buck6";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <2500>;
};
buck7 {
regulator-name = "buck7";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <2000000>;
regulator-ramp-delay = <2500>;
};
buck8 {
regulator-name = "buck8";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1700000>;
regulator-ramp-delay = <2500>;
rohm,dvs-run-voltage = <1700000>;
rohm,dvs-idle-voltage = <1>;
rohm,dvs-suspend-voltage = <1>;
rohm,dvs-lpsr-voltage = <0>;
regulator-boot-on;
};
buck9 {
regulator-name = "buck9";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1700000>;
regulator-ramp-delay = <2500>;
rohm,dvs-run-voltage = <1700000>;
rohm,dvs-idle-voltage = <1>;
rohm,dvs-suspend-voltage = <1>;
rohm,dvs-lpsr-voltage = <0>;
regulator-boot-on;
};
buck10 {
regulator-name = "buck10";
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1700000>;
regulator-ramp-delay = <2500>;
rohm,dvs-run-voltage = <1700000>;
rohm,dvs-idle-voltage = <1>;
rohm,dvs-suspend-voltage = <1>;
rohm,dvs-lpsr-voltage = <0>;
regulator-boot-on;
};
ldo1 {
regulator-name = "ldo1";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
ldo2 {
regulator-name = "ldo2";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
ldo3 {
regulator-name = "ldo3";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
ldo4 {
regulator-name = "ldo4";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
ldo5 {
regulator-name = "ldo5";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
ldo6 {
regulator-name = "ldo6";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
ldo7 {
regulator-name = "ldo7";
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
ldo8 {
regulator-name = "ldo8";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3300000>;
rohm,dvs-suspend-voltage = <0>;
rohm,dvs-lpsr-voltage = <1>;
rohm,dvs-run-voltage = <750000>;
};
ldo9 {
regulator-name = "ldo9";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3300000>;
rohm,dvs-suspend-voltage = <0>;
rohm,dvs-lpsr-voltage = <1>;
rohm,dvs-run-voltage = <750000>;
};
ldo10 {
regulator-name = "ldo10";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3300000>;
rohm,dvs-suspend-voltage = <0>;
rohm,dvs-lpsr-voltage = <1>;
rohm,dvs-run-voltage = <750000>;
};
ldo11 {
regulator-name = "ldo11";
regulator-min-microvolt = <750000>;
regulator-max-microvolt = <3300000>;
rohm,dvs-suspend-voltage = <0>;
rohm,dvs-lpsr-voltage = <1>;
rohm,dvs-run-voltage = <750000>;
};
};
leds {
compatible = "rohm,bd71828-leds";
led-1 {
rohm,led-compatible = "bd71828-grnled";
function = LED_FUNCTION_INDICATOR;
color = <LED_COLOR_ID_GREEN>;
};
led-2 {
rohm,led-compatible = "bd71828-ambled";
function = LED_FUNCTION_CHARGING;
color = <LED_COLOR_ID_AMBER>;
};
};
};
};
Documentation/devicetree/bindings/power/supply/battery.yaml
+32 -1
View File
@@ -64,7 +64,16 @@ properties:
description: battery design capacity
trickle-charge-current-microamp:
description: current for trickle-charge phase
description: current for trickle-charge phase.
Please note that the trickle-charging here, refers "wake-up" or
"pre-pre" -charging, for very empty batteries. Similar term is also
used for "maintenance" or "top-off" -charging of batteries (like
NiMh bq24400) - that is different and not controlled by this
property.
tricklecharge-upper-limit-microvolt:
description: limit when to change to precharge from trickle charge
Trickle-charging here refers "wake-up" or "pre-pre" -charging.
precharge-current-microamp:
description: current for pre-charge phase
@@ -119,6 +128,21 @@ properties:
- description: alert when battery temperature is lower than this value
- description: alert when battery temperature is higher than this value
# The volt-drop* -properties describe voltage-drop for a battery, described
# as VDROP in:
# https://patentimages.storage.googleapis.com/6c/f5/17/c1d901c220f6a9/US20150032394A1.pdf
volt-drop-thresh-microvolt:
description: Threshold for starting the VDR correction
maximum: 48000000
volt-drop-soc-bp:
description: Table of capacity values matching the values in VDR tables.
The value should be given as basis points, 1/100 of a percent.
volt-drop-temperatures-millicelsius:
description: An array containing the temperature in milli celsius, for each
of the VDR lookup table.
required:
- compatible
@@ -137,6 +161,13 @@ patternProperties:
- description: battery capacity percent
maximum: 100
'^volt-drop-[0-9]-microvolt':
description: Table of the voltage drop rate (VDR) values. Each entry in the
table should match a capacity value in the volt-drop-soc table.
Furthermore, the values should be obtained for the temperature given in
volt-drop-temperatures-millicelsius table at index matching the
number in this table's name.
additionalProperties: false
examples:
Documentation/devicetree/bindings/regulator/rohm,bd72720-regulator.yaml
+148
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@@ -0,0 +1,148 @@
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
%YAML 1.2
---
$id: http://devicetree.org/schemas/regulator/rohm,bd72720-regulator.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: ROHM BD72720 Power Management Integrated Circuit regulators
maintainers:
- Matti Vaittinen <mazziesaccount@gmail.com>
description: |
This module is part of the ROHM BD72720 MFD device. For more details
see Documentation/devicetree/bindings/mfd/rohm,bd72720-pmic.yaml.
The regulator controller is represented as a sub-node of the PMIC node
on the device tree.
Regulator nodes should be named to BUCK_<number> and LDO_<number>.
The valid names for BD72720 regulator nodes are
buck1, buck2, buck3, buck4, buck5, buck6, buck7, buck8, buck9, buck10
ldo1, ldo2, ldo3, ldo4, ldo5, ldo6, ldo7, ldo8, ldo9, ldo10, ldo11
patternProperties:
"^ldo([1-9]|1[0-1])$":
type: object
description:
Properties for single LDO regulator.
$ref: regulator.yaml#
properties:
regulator-name:
pattern: "^ldo([1-9]|1[0-1])$"
rohm,dvs-run-voltage:
description:
PMIC default "RUN" state voltage in uV. See below table for
LDOs which support this. 0 means disabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
rohm,dvs-idle-voltage:
description:
PMIC default "IDLE" state voltage in uV. See below table for
LDOs which support this. 0 means disabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
rohm,dvs-suspend-voltage:
description:
PMIC default "SUSPEND" state voltage in uV. See below table for
LDOs which support this. 0 means disabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
rohm,dvs-lpsr-voltage:
description:
PMIC default "deep-idle" state voltage in uV. See below table for
LDOs which support this. 0 means disabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
# Supported default DVS states:
# ldo | run | idle | suspend | lpsr
# --------------------------------------------------------------
# 1, 2, 3, and 4 | supported | supported | supported | supported
# --------------------------------------------------------------
# 5 - 11 | supported (*)
# --------------------------------------------------------------
#
# (*) All states use same voltage but have own enable / disable
# settings. Voltage 0 can be specified for a state to make
# regulator disabled on that state.
unevaluatedProperties: false
"^buck([1-9]|10)$":
type: object
description:
Properties for single BUCK regulator.
$ref: regulator.yaml#
properties:
regulator-name:
pattern: "^buck([1-9]|10)$"
rohm,ldon-head-microvolt:
description:
Set this on boards where BUCK10 is used to supply LDOs 1-4. The bucki
voltage will be changed by the PMIC to follow the LDO output voltages
with the offset voltage given here. This will improve the LDO efficiency.
minimum: 50000
maximum: 300000
rohm,dvs-run-voltage:
description:
PMIC default "RUN" state voltage in uV. See below table for
bucks which support this. 0 means disabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
rohm,dvs-idle-voltage:
description:
PMIC default "IDLE" state voltage in uV. See below table for
bucks which support this. 0 means disabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
rohm,dvs-suspend-voltage:
description:
PMIC default "SUSPEND" state voltage in uV. See below table for
bucks which support this. 0 means disabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
rohm,dvs-lpsr-voltage:
description:
PMIC default "deep-idle" state voltage in uV. See below table for
bucks which support this. 0 means disabled.
$ref: /schemas/types.yaml#/definitions/uint32
minimum: 0
maximum: 3300000
# Supported default DVS states:
# buck | run | idle | suspend | lpsr
# --------------------------------------------------------------
# 1, 2, 3, and 4 | supported | supported | supported | supported
# --------------------------------------------------------------
# 5 - 10 | supported (*)
# --------------------------------------------------------------
#
# (*) All states use same voltage but have own enable / disable
# settings. Voltage 0 can be specified for a state to make
# regulator disabled on that state.
required:
- regulator-name
unevaluatedProperties: false
additionalProperties: false
Documentation/driver-api/gpio/pca953x.rst
+87
View File
@@ -178,6 +178,8 @@ pcal9554b 8 yes 00 01 02 03
pcal6416 16 yes 00 02 04 06
pcal9535 16 yes 00 02 04 06
pcal9555a 16 yes 00 02 04 06
tcal6408 8 yes 00 01 02 03
tcal6416 16 yes 00 02 04 06
========== ===== ========= ===== ====== ====== =========
These chips have several additional features:
@@ -196,6 +198,8 @@ pcal9554b 40 42 43 44 45 46 4F
pcal6416 40 44 46 48 4A 4C 4F
pcal9535 40 44 46 48 4A 4C 4F
pcal9555a 40 44 46 48 4A 4C 4F
tcal6408 40 42 43 44 45 46 4F
tcal6416 40 44 46 48 4A 4C 4F
========== ============ ======== ======= ======== ======== ========== ========
Currently the driver has support for the input latch, pull-up/pull-down
@@ -332,6 +336,8 @@ Layouts:
- pcal9554b
- pcal9555a
- pcal6524
- tcal6408
- tcal6416
2. base offset 0x30, bank 5 and 6, closely packed banks
- pcal6534
@@ -383,6 +389,13 @@ disabled.
Currently the driver enables the latch for each line with interrupt
enabled.
An interrupt status register records which pins triggered an interrupt.
However, the status register and the input port register must be read
separately; there is no atomic mechanism to read both simultaneously, so races
are possible. Refer to the chapter `Interrupt source detection`_ to understand
the implications of this and how the driver still makes use of the latching
feature.
1. base offset 0x40, bank 2, bank offsets of 2^n
- pcal6408
- pcal6416
@@ -390,6 +403,8 @@ enabled.
- pcal9554b
- pcal9555a
- pcal6524
- tcal6408
- tcal6416
2. base offset 0x30, bank 2, closely packed banks
- pcal6534
@@ -462,6 +477,8 @@ Layout:
- pcal9535
- pcal9554b
- pcal9555a
- tcal6408
- tcal6416
`PCAL chips with extended interrupt and output configuration functions`_
can set this for each line individually. They have the same per-port out_conf
@@ -505,12 +522,82 @@ bits drive strength
- pcal9554b
- pcal9555a
- pcal6524
- tcal6408
- tcal6416
2. base offset 0x30, bank 0 and 1, closely packed banks
- pcal6534
Currently not supported by the driver.
Interrupt source detection
==========================
When triggered by the GPIO expander's interrupt, the driver determines which
IRQs are pending by reading the input port register.
To be able to filter on specific interrupt events for all compatible devices,
the driver keeps track of the previous input state of the lines, and emits an
IRQ only for the correct edge or level. This system works irrespective of the
number of enabled interrupts. Events will not be missed even if they occur
between the GPIO expander's interrupt and the actual I2C read. Edges could of
course be missed if the related signal level changes back to the value
previously saved by the driver before the I2C read. PCAL variants offer input
latching for that reason.
PCAL input latching
-------------------
The PCAL variants have an input latch and the driver enables this for all
interrupt-enabled lines. The interrupt is then only cleared when the input port
is read out. These variants provide an interrupt status register that records
which pins triggered an interrupt, but the status and input registers cannot be
read atomically. If another interrupt occurs on a different line after the
status register has been read but before the input port register is sampled,
that event will not be reflected in the earlier status snapshot, so relying
solely on the interrupt status register is insufficient.
Thus, the PCAL variants also have to use the existing level-change logic.
For short pulses, the first edge is captured when the input register is read,
but if the signal returns to its previous level before this read, the second
edge is not observed. As a result, successive pulses can produce identical
input values at read time and no level change is detected, causing interrupts
to be missed. Below timing diagram shows this situation where the top signal is
the input pin level and the bottom signal indicates the latched value::
─────┐ ┌──*───────────────┐ ┌──*─────────────────┐ ┌──*───
│ │ . │ │ . │ │ .
│ │ │ │ │ │ │ │ │
└──*──┘ │ └──*──┘ │ └──*──┘ │
Input │ │ │ │ │ │
▼ │ ▼ │ ▼ │
IRQ │ IRQ │ IRQ │
. . .
─────┐ .┌──────────────┐ .┌────────────────┐ .┌──
│ │ │ │ │ │
│ │ │ │ │ │
└────────*┘ └────────*┘ └────────*┘
Latched │ │ │
▼ ▼ ▼
READ 0 READ 0 READ 0
NO CHANGE NO CHANGE
To deal with this, events indicated by the interrupt status register are merged
with events detected through the existing level-change logic. As a result:
- short pulses, whose second edges are invisible, are detected via the
interrupt status register, and
- interrupts that occur between the status and input reads are still
caught by the generic level-change logic.
Note that this is still best-effort: the status and input registers are read
separately, and short pulses on other lines may occur in between those reads.
Such pulses can still be latched as an interrupt without leaving an observable
level change at read time, and may not be attributable to a specific edge. This
does not reduce detection compared to the generic path, but reflects inherent
atomicity limitations.
Datasheets
==========
MAINTAINERS
+8
View File
@@ -10816,6 +10816,12 @@ S: Maintained
F: Documentation/devicetree/bindings/leds/irled/gpio-ir-tx.yaml
F: drivers/media/rc/gpio-ir-tx.c
GPIO LINE MUX
M: Jonas Jelonek <jelonek.jonas@gmail.com>
S: Maintained
F: Documentation/devicetree/bindings/gpio/gpio-line-mux.yaml
F: drivers/gpio/gpio-line-mux.c
GPIO MOCKUP DRIVER
M: Bamvor Jian Zhang <bamv2005@gmail.com>
L: linux-gpio@vger.kernel.org
@@ -22836,6 +22842,7 @@ S: Supported
F: drivers/clk/clk-bd718x7.c
F: drivers/gpio/gpio-bd71815.c
F: drivers/gpio/gpio-bd71828.c
F: drivers/gpio/gpio-bd72720.c
F: drivers/mfd/rohm-bd71828.c
F: drivers/mfd/rohm-bd718x7.c
F: drivers/mfd/rohm-bd9576.c
@@ -22852,6 +22859,7 @@ F: drivers/watchdog/bd96801_wdt.c
F: include/linux/mfd/rohm-bd71815.h
F: include/linux/mfd/rohm-bd71828.h
F: include/linux/mfd/rohm-bd718x7.h
F: include/linux/mfd/rohm-bd72720.h
F: include/linux/mfd/rohm-bd957x.h
F: include/linux/mfd/rohm-bd96801.h
F: include/linux/mfd/rohm-bd96802.h
drivers/clk/Kconfig
+2 -2
View File
@@ -475,8 +475,8 @@ config COMMON_CLK_BD718XX
tristate "Clock driver for 32K clk gates on ROHM PMICs"
depends on MFD_ROHM_BD718XX || MFD_ROHM_BD71828
help
This driver supports ROHM BD71837, BD71847, BD71850, BD71815
and BD71828 PMICs clock gates.
This driver supports ROHM BD71837, BD71847, BD71850, BD71815,
BD71828, and BD72720 PMICs clock gates.
config COMMON_CLK_FIXED_MMIO
bool "Clock driver for Memory Mapped Fixed values"
drivers/clk/clk-bd718x7.c
+8 -2
View File
@@ -19,7 +19,8 @@
#define BD71828_REG_OUT32K 0x4B
/* BD71837 and BD71847 */
#define BD718XX_REG_OUT32K 0x2E
/* BD72720 */
#define BD72720_REG_OUT32K 0x9a
/*
* BD71837, BD71847, and BD71828 all use bit [0] to clk output control
*/
@@ -118,6 +119,10 @@ static int bd71837_clk_probe(struct platform_device *pdev)
c->reg = BD71815_REG_OUT32K;
c->mask = CLK_OUT_EN_MASK;
break;
case ROHM_CHIP_TYPE_BD72720:
c->reg = BD72720_REG_OUT32K;
c->mask = CLK_OUT_EN_MASK;
break;
default:
dev_err(&pdev->dev, "Unknown clk chip\n");
return -EINVAL;
@@ -146,6 +151,7 @@ static const struct platform_device_id bd718x7_clk_id[] = {
{ "bd71847-clk", ROHM_CHIP_TYPE_BD71847 },
{ "bd71828-clk", ROHM_CHIP_TYPE_BD71828 },
{ "bd71815-clk", ROHM_CHIP_TYPE_BD71815 },
{ "bd72720-clk", ROHM_CHIP_TYPE_BD72720 },
{ },
};
MODULE_DEVICE_TABLE(platform, bd718x7_clk_id);
@@ -161,6 +167,6 @@ static struct platform_driver bd71837_clk = {
module_platform_driver(bd71837_clk);
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and chip clk driver");
MODULE_DESCRIPTION("BD718(15/18/28/37/47/50) and BD72720 chip clk driver");
MODULE_LICENSE("GPL");
MODULE_ALIAS("platform:bd718xx-clk");
drivers/gpio/Kconfig
+21 -3
View File
@@ -600,7 +600,7 @@ config GPIO_RDA
config GPIO_REALTEK_OTTO
tristate "Realtek Otto GPIO support"
depends on MACH_REALTEK_RTL
depends on MACH_REALTEK_RTL || COMPILE_TEST
default MACH_REALTEK_RTL
select GPIO_GENERIC
select GPIOLIB_IRQCHIP
@@ -1193,11 +1193,11 @@ config GPIO_PCA953X
8 bits: max7310, max7315, pca6107, pca9534, pca9538, pca9554,
pca9556, pca9557, pca9574, tca6408, tca9554, xra1202,
pcal6408, pcal9554b, tca9538
pcal6408, pcal9554b, tca9538, tcal6408
16 bits: max7312, max7313, pca9535, pca9539, pca9555, pca9575,
tca6416, pca6416, pcal6416, pcal9535, pcal9555a, max7318,
tca9539
tca9539, tcal6416
18 bits: tca6418
@@ -1317,6 +1317,15 @@ config GPIO_BD71828
This driver can also be built as a module. If so, the module
will be called gpio-bd71828.
config GPIO_BD72720
tristate "ROHM BD72720 and BD73900 PMIC GPIO support"
depends on MFD_ROHM_BD71828
help
Support for GPIO on ROHM BD72720 and BD73900 PMICs. There are two
pins which can be configured to GPI or GPO, and three pins which can
be configured to GPO on the ROHM PMIC. The pin configuration is done
on OTP at manufacturing.
config GPIO_BD9571MWV
tristate "ROHM BD9571 GPIO support"
depends on MFD_BD9571MWV
@@ -1994,6 +2003,15 @@ config GPIO_LATCH
Say yes here to enable a driver for GPIO multiplexers based on latches
connected to other GPIOs.
config GPIO_LINE_MUX
tristate "GPIO line mux driver"
depends on OF_GPIO
select MULTIPLEXER
help
Say Y here to support the GPIO line mux, which can provide virtual
GPIOs backed by a shared real GPIO and a multiplexer in a 1-to-many
fashion.
config GPIO_MOCKUP
tristate "GPIO Testing Driver (DEPRECATED)"
select IRQ_SIM
drivers/gpio/Makefile
+2
View File
@@ -46,6 +46,7 @@ obj-$(CONFIG_GPIO_BCM_KONA) += gpio-bcm-kona.o
obj-$(CONFIG_GPIO_BCM_XGS_IPROC) += gpio-xgs-iproc.o
obj-$(CONFIG_GPIO_BD71815) += gpio-bd71815.o
obj-$(CONFIG_GPIO_BD71828) += gpio-bd71828.o
obj-$(CONFIG_GPIO_BD72720) += gpio-bd72720.o
obj-$(CONFIG_GPIO_BD9571MWV) += gpio-bd9571mwv.o
obj-$(CONFIG_GPIO_BLZP1600) += gpio-blzp1600.o
obj-$(CONFIG_GPIO_BRCMSTB) += gpio-brcmstb.o
@@ -90,6 +91,7 @@ obj-$(CONFIG_GPIO_IXP4XX) += gpio-ixp4xx.o
obj-$(CONFIG_GPIO_JANZ_TTL) += gpio-janz-ttl.o
obj-$(CONFIG_GPIO_KEMPLD) += gpio-kempld.o
obj-$(CONFIG_GPIO_LATCH) += gpio-latch.o
obj-$(CONFIG_GPIO_LINE_MUX) += gpio-line-mux.o
obj-$(CONFIG_GPIO_LJCA) += gpio-ljca.o
obj-$(CONFIG_GPIO_LOGICVC) += gpio-logicvc.o
obj-$(CONFIG_GPIO_LOONGSON1) += gpio-loongson1.o
drivers/gpio/gpio-aggregator.c
+4 -4
View File
@@ -1226,7 +1226,7 @@ gpio_aggregator_line_release(struct config_item *item)
kfree(line);
}
static struct configfs_item_operations gpio_aggregator_line_item_ops = {
static const struct configfs_item_operations gpio_aggregator_line_item_ops = {
.release = gpio_aggregator_line_release,
};
@@ -1247,7 +1247,7 @@ static void gpio_aggregator_device_release(struct config_item *item)
gpio_aggregator_free(aggr);
}
static struct configfs_item_operations gpio_aggregator_device_item_ops = {
static const struct configfs_item_operations gpio_aggregator_device_item_ops = {
.release = gpio_aggregator_device_release,
};
@@ -1292,7 +1292,7 @@ gpio_aggregator_device_make_group(struct config_group *group, const char *name)
return &line->group;
}
static struct configfs_group_operations gpio_aggregator_device_group_ops = {
static const struct configfs_group_operations gpio_aggregator_device_group_ops = {
.make_group = gpio_aggregator_device_make_group,
};
@@ -1328,7 +1328,7 @@ gpio_aggregator_make_group(struct config_group *group, const char *name)
return &aggr->group;
}
static struct configfs_group_operations gpio_aggregator_group_ops = {
static const struct configfs_group_operations gpio_aggregator_group_ops = {
.make_group = gpio_aggregator_make_group,
};
drivers/gpio/gpio-aspeed-sgpio.c
+224 -138
View File
File diff suppressed because it is too large Load Diff
drivers/gpio/gpio-aspeed.c
+2 -5
View File
@@ -1302,7 +1302,6 @@ MODULE_DEVICE_TABLE(of, aspeed_gpio_of_table);
static int aspeed_gpio_probe(struct platform_device *pdev)
{
const struct of_device_id *gpio_id;
struct gpio_irq_chip *girq;
struct aspeed_gpio *gpio;
int rc, irq, i, banks, err;
@@ -1320,8 +1319,8 @@ static int aspeed_gpio_probe(struct platform_device *pdev)
raw_spin_lock_init(&gpio->lock);
gpio_id = of_match_node(aspeed_gpio_of_table, pdev->dev.of_node);
if (!gpio_id)
gpio->config = device_get_match_data(&pdev->dev);
if (!gpio->config)
return -EINVAL;
gpio->clk = devm_clk_get_enabled(&pdev->dev, NULL);
@@ -1331,8 +1330,6 @@ static int aspeed_gpio_probe(struct platform_device *pdev)
gpio->clk = NULL;
}
gpio->config = gpio_id->data;
if (!gpio->config->llops->reg_bit_set || !gpio->config->llops->reg_bit_get ||
!gpio->config->llops->reg_bank_get)
return -EINVAL;
drivers/gpio/gpio-bd72720.c
+281
View File
@@ -0,0 +1,281 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Support to GPIOs on ROHM BD72720 and BD79300
* Copyright 2025 ROHM Semiconductors.
* Author: Matti Vaittinen <mazziesaccount@gmail.com>
*/
#include <linux/gpio/driver.h>
#include <linux/init.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <linux/of.h>
#include <linux/platform_device.h>
#include <linux/mfd/rohm-bd72720.h>
#define BD72720_GPIO_OPEN_DRAIN 0
#define BD72720_GPIO_CMOS BIT(1)
#define BD72720_INT_GPIO1_IN_SRC 4
/*
* The BD72720 has several "one time programmable" (OTP) configurations which
* can be set at manufacturing phase. A set of these options allow using pins
* as GPIO. The OTP configuration can't be read at run-time, so drivers rely on
* device-tree to advertise the correct options.
*
* Both DVS[0,1] pins can be configured to be used for:
* - OTP0: regulator RUN state control
* - OTP1: GPI
* - OTP2: GPO
* - OTP3: Power sequencer output
* Data-sheet also states that these PINs can always be used for IRQ but the
* driver limits this by allowing them to be used for IRQs with OTP1 only.
*
* Pins GPIO_EXTEN0 (GPIO3), GPIO_EXTEN1 (GPIO4), GPIO_FAULT_B (GPIO5) have OTP
* options for a specific (non GPIO) purposes, but also an option to configure
* them to be used as a GPO.
*
* OTP settings can be separately configured for each pin.
*
* DT properties:
* "rohm,pin-dvs0" and "rohm,pin-dvs1" can be set to one of the values:
* "dvs-input", "gpi", "gpo".
*
* "rohm,pin-exten0", "rohm,pin-exten1" and "rohm,pin-fault_b" can be set to:
* "gpo"
*/
enum bd72720_gpio_state {
BD72720_PIN_UNKNOWN,
BD72720_PIN_GPI,
BD72720_PIN_GPO,
};
enum {
BD72720_GPIO1,
BD72720_GPIO2,
BD72720_GPIO3,
BD72720_GPIO4,
BD72720_GPIO5,
BD72720_GPIO_EPDEN,
BD72720_NUM_GPIOS
};
struct bd72720_gpio {
/* chip.parent points the MFD which provides DT node and regmap */
struct gpio_chip chip;
/* dev points to the platform device for devm and prints */
struct device *dev;
struct regmap *regmap;
int gpio_is_input;
};
static int bd72720gpi_get(struct bd72720_gpio *bdgpio, unsigned int reg_offset)
{
int ret, val, shift;
ret = regmap_read(bdgpio->regmap, BD72720_REG_INT_ETC1_SRC, &val);
if (ret)
return ret;
shift = BD72720_INT_GPIO1_IN_SRC + reg_offset;
return (val >> shift) & 1;
}
static int bd72720gpo_get(struct bd72720_gpio *bdgpio,
unsigned int offset)
{
const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL,
BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL,
BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL };
int ret, val;
ret = regmap_read(bdgpio->regmap, regs[offset], &val);
if (ret)
return ret;
return val & BD72720_GPIO_HIGH;
}
static int bd72720gpio_get(struct gpio_chip *chip, unsigned int offset)
{
struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
if (BIT(offset) & bdgpio->gpio_is_input)
return bd72720gpi_get(bdgpio, offset);
return bd72720gpo_get(bdgpio, offset);
}
static int bd72720gpo_set(struct gpio_chip *chip, unsigned int offset,
int value)
{
struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL,
BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL,
BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL };
if (BIT(offset) & bdgpio->gpio_is_input) {
dev_dbg(bdgpio->dev, "pin %d not output.\n", offset);
return -EINVAL;
}
if (value)
return regmap_set_bits(bdgpio->regmap, regs[offset],
BD72720_GPIO_HIGH);
return regmap_clear_bits(bdgpio->regmap, regs[offset],
BD72720_GPIO_HIGH);
}
static int bd72720_gpio_set_config(struct gpio_chip *chip, unsigned int offset,
unsigned long config)
{
struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
const int regs[] = { BD72720_REG_GPIO1_CTRL, BD72720_REG_GPIO2_CTRL,
BD72720_REG_GPIO3_CTRL, BD72720_REG_GPIO4_CTRL,
BD72720_REG_GPIO5_CTRL, BD72720_REG_EPDEN_CTRL };
/*
* We can only set the output mode, which makes sense only when output
* OTP configuration is used.
*/
if (BIT(offset) & bdgpio->gpio_is_input)
return -ENOTSUPP;
switch (pinconf_to_config_param(config)) {
case PIN_CONFIG_DRIVE_OPEN_DRAIN:
return regmap_update_bits(bdgpio->regmap,
regs[offset],
BD72720_GPIO_DRIVE_MASK,
BD72720_GPIO_OPEN_DRAIN);
case PIN_CONFIG_DRIVE_PUSH_PULL:
return regmap_update_bits(bdgpio->regmap,
regs[offset],
BD72720_GPIO_DRIVE_MASK,
BD72720_GPIO_CMOS);
default:
break;
}
return -ENOTSUPP;
}
static int bd72720gpo_direction_get(struct gpio_chip *chip,
unsigned int offset)
{
struct bd72720_gpio *bdgpio = gpiochip_get_data(chip);
if (BIT(offset) & bdgpio->gpio_is_input)
return GPIO_LINE_DIRECTION_IN;
return GPIO_LINE_DIRECTION_OUT;
}
static int bd72720_valid_mask(struct gpio_chip *gc,
unsigned long *valid_mask,
unsigned int ngpios)
{
static const char * const properties[] = {
"rohm,pin-dvs0", "rohm,pin-dvs1", "rohm,pin-exten0",
"rohm,pin-exten1", "rohm,pin-fault_b"
};
struct bd72720_gpio *g = gpiochip_get_data(gc);
const char *val;
int i, ret;
*valid_mask = BIT(BD72720_GPIO_EPDEN);
if (!gc->parent)
return 0;
for (i = 0; i < ARRAY_SIZE(properties); i++) {
ret = fwnode_property_read_string(dev_fwnode(gc->parent),
properties[i], &val);
if (ret) {
if (ret == -EINVAL)
continue;
dev_err(g->dev, "pin %d (%s), bad configuration\n", i,
properties[i]);
return ret;
}
if (strcmp(val, "gpi") == 0) {
if (i != BD72720_GPIO1 && i != BD72720_GPIO2) {
dev_warn(g->dev,
"pin %d (%s) does not support INPUT mode",
i, properties[i]);
continue;
}
*valid_mask |= BIT(i);
g->gpio_is_input |= BIT(i);
} else if (strcmp(val, "gpo") == 0) {
*valid_mask |= BIT(i);
}
}
return 0;
}
/* Template for GPIO chip */
static const struct gpio_chip bd72720gpo_chip = {
.label = "bd72720",
.owner = THIS_MODULE,
.get = bd72720gpio_get,
.get_direction = bd72720gpo_direction_get,
.set = bd72720gpo_set,
.set_config = bd72720_gpio_set_config,
.init_valid_mask = bd72720_valid_mask,
.can_sleep = true,
.ngpio = BD72720_NUM_GPIOS,
.base = -1,
};
static int gpo_bd72720_probe(struct platform_device *pdev)
{
struct bd72720_gpio *g;
struct device *parent, *dev;
/*
* Bind devm lifetime to this platform device => use dev for devm.
* also the prints should originate from this device.
*/
dev = &pdev->dev;
/* The device-tree and regmap come from MFD => use parent for that */
parent = dev->parent;
g = devm_kzalloc(dev, sizeof(*g), GFP_KERNEL);
if (!g)
return -ENOMEM;
g->chip = bd72720gpo_chip;
g->dev = dev;
g->chip.parent = parent;
g->regmap = dev_get_regmap(parent, NULL);
return devm_gpiochip_add_data(dev, &g->chip, g);
}
static const struct platform_device_id bd72720_gpio_id[] = {
{ "bd72720-gpio" },
{ },
};
MODULE_DEVICE_TABLE(platform, bd72720_gpio_id);
static struct platform_driver gpo_bd72720_driver = {
.driver = {
.name = "bd72720-gpio",
.probe_type = PROBE_PREFER_ASYNCHRONOUS,
},
.probe = gpo_bd72720_probe,
.id_table = bd72720_gpio_id,
};
module_platform_driver(gpo_bd72720_driver);
MODULE_AUTHOR("Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>");
MODULE_DESCRIPTION("GPIO interface for BD72720 and BD73900");
MODULE_LICENSE("GPL");

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