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arm64: dts: qcom: glymur: Add iris video node

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Add iris video codec to glymur SoC, which comes with significantly
different powering up sequence than previous platforms, thus different
clocks and resets.

Reviewed-by: Vikash Garodia <vikash.garodia@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Tested-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Vishnu Reddy <busanna.reddy@oss.qualcomm.com>
Link: https://patch.msgid.link/20260726-glymur-v10-13-de451559e88b@oss.qualcomm.com
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
This commit is contained in:
Vishnu Reddy
2026-08-05 15:36:02 +03:00
committed by Abel Vesa
parent ae496d8c95
commit d6b2e22f64
1 changed files with 131 additions and 0 deletions
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arch/arm64/boot/dts/qcom/glymur.dtsi
+131
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@@ -666,6 +666,18 @@
hwlocks = <&tcsr_mutex 3>;
no-map;
};
adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x80000000 0x0 0x80000000>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x800000>;
};
iris_resv: reservation-iris {
iommu-addresses = <&iris_non_pixel 0x0 0x0 0x0 0x25800000>;
};
};
smp2p-adsp {
@@ -5029,6 +5041,125 @@
};
};
iris: video-codec@aa00000 {
compatible = "qcom,glymur-iris";
reg = <0x0 0x0aa00000 0x0 0xf0000>;
clocks = <&gcc GCC_VIDEO_AXI0C_CLK>,
<&videocc VIDEO_CC_MVS0C_CLK>,
<&videocc VIDEO_CC_MVS0_CLK>,
<&gcc GCC_VIDEO_AXI0_CLK>,
<&videocc VIDEO_CC_MVS0C_FREERUN_CLK>,
<&videocc VIDEO_CC_MVS0_FREERUN_CLK>,
<&gcc GCC_VIDEO_AXI1_CLK>,
<&videocc VIDEO_CC_MVS1_CLK>,
<&videocc VIDEO_CC_MVS1_FREERUN_CLK>;
clock-names = "core_iface",
"core",
"vcodec0_core",
"vcodec0_iface",
"core_freerun",
"vcodec0_core_freerun",
"vcodec1_iface",
"vcodec1_core",
"vcodec1_core_freerun";
dma-coherent;
interconnects = <&hsc_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY
&config_noc SLAVE_VENUS_CFG QCOM_ICC_TAG_ACTIVE_ONLY>,
<&mmss_noc MASTER_VIDEO QCOM_ICC_TAG_ALWAYS
&mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>;
interconnect-names = "cpu-cfg",
"video-mem";
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
memory-region = <&video_mem>;
operating-points-v2 = <&iris_opp_table>;
power-domains = <&videocc VIDEO_CC_MVS0C_GDSC>,
<&videocc VIDEO_CC_MVS0_GDSC>,
<&rpmhpd RPMHPD_MXC>,
<&rpmhpd RPMHPD_MMCX>,
<&videocc VIDEO_CC_MVS1_GDSC>;
power-domain-names = "venus",
"vcodec0",
"mxc",
"mmcx",
"vcodec1";
resets = <&gcc GCC_VIDEO_AXI0C_CLK_ARES>,
<&gcc GCC_VIDEO_AXI0_CLK_ARES>,
<&videocc VIDEO_CC_MVS0C_FREERUN_CLK_ARES>,
<&videocc VIDEO_CC_MVS0_FREERUN_CLK_ARES>,
<&gcc GCC_VIDEO_AXI1_CLK_ARES>,
<&videocc VIDEO_CC_MVS1_FREERUN_CLK_ARES>;
reset-names = "core_bus",
"vcodec0_bus",
"core",
"vcodec0_core",
"vcodec1_bus",
"vcodec1_core";
#address-cells = <2>;
#size-cells = <2>;
status = "disabled";
iris_non_pixel: non-pixel {
iommus = <&apps_smmu 0x1940 0x0>,
<&apps_smmu 0x1944 0x0>,
<&apps_smmu 0x19e0 0x0>;
memory-region = <&iris_resv>;
};
pixel {
iommus = <&apps_smmu 0x1943 0x0>;
};
iris_opp_table: opp-table {
compatible = "operating-points-v2";
opp-240000000 {
opp-hz = /bits/ 64 <240000000 240000000 360000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_low_svs>;
};
opp-338000000 {
opp-hz = /bits/ 64 <338000000 338000000 507000000>;
required-opps = <&rpmhpd_opp_svs>,
<&rpmhpd_opp_svs>;
};
opp-366000000 {
opp-hz = /bits/ 64 <366000000 366000000 549000000>;
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_svs_l1>;
};
opp-444000000 {
opp-hz = /bits/ 64 <444000000 444000000 666000000>;
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_nom>;
};
opp-533333334 {
opp-hz = /bits/ 64 <533333334 533333334 800000000>;
required-opps = <&rpmhpd_opp_svs_l1>,
<&rpmhpd_opp_turbo>;
};
opp-655000000 {
opp-hz = /bits/ 64 <655000000 655000000 982000000>;
required-opps = <&rpmhpd_opp_nom>,
<&rpmhpd_opp_turbo_l1>;
};
};
};
videocc: clock-controller@aaf0000 {
compatible = "qcom,glymur-videocc";
reg = <0x0 0x0aaf0000 0x0 0x10000>;