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Merge tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl

Browse Source 
Pull pin control updates from Linus Walleij:
 "Nothing special, notably a lot of new Qualcomm hardware is supported,
  a RISC-V reference SoC and then some cleanups both in code and device
  tree bindings.

  Core changes:

   - Add PINCTRL_PINFUNCTION() macro and use it in several drivers

  New drivers:

   - New driver for the StarFive JH7110 SoC "sys" and "aon" (always-on)
     pin controllers. (RISC-V.)

   - New subdriver for the Qualcomm QDU1000/QRU1000 SoC pin controller

   - New subdrivers for the Qualcomm SM8550 SoC and LPASS pin
     controllers

   - New subdriver for the Qualcomm SA8775P SoC pin controller

   - New subdriver for the Qualcomm IPQ5332 SoC pin controller

   - New (trivial) support for Qualcomm PM8550 and PMR735D PMIC pin
     control

   - New subdriver for the Mediatek MT7981 SoC pin controller

  Improvements:

   - Several cleanups and refactorings to the Intel drivers

   - Add 4KOhm bias support to the Intel driver

   - Use the NOIRQ_SYSTEM_SLEEP_PM_OPS for the AT91 driver

   - Support general purpose clocks in the Qualcomm MSM8226 SoC

   - Several conversions to use the new I2C .probe_new() call

   - Massive clean-up of the Qualcomm Device Tree YAML schemas

   - Add VIN[45] pins, groups and functions to the Renesas r8a77950 SoC
     driver"

* tag 'pinctrl-v6.3-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-pinctrl: (118 commits)
  pinctrl: qcom: Add support for i2c specific pull feature
  pinctrl: starfive: Add StarFive JH7110 aon controller driver
  pinctrl: starfive: Add StarFive JH7110 sys controller driver
  dt-bindings: pinctrl: Add StarFive JH7110 aon pinctrl
  dt-bindings: pinctrl: Add StarFive JH7110 sys pinctrl
  pinctrl: add mt7981 pinctrl driver
  dt-bindings: pinctrl: add bindings for MT7981 SoC
  dt-bindings: pinctrl: rockchip,pinctrl: mark gpio sub nodes of pinctrl as deprecated
  pinctrl: qcom: Introduce IPQ5332 TLMM driver
  dt-bindings: pinctrl: qcom: add IPQ5332 pinctrl
  dt-bindings: pinctrl: qcom: lpass-lpi: correct GPIO name pattern
  pinctrl: qcom: pinctrl-sm8550-lpass-lpi: add SM8550 LPASS
  dt-bindings: pinctrl: qcom,sm8550-lpass-lpi-pinctrl: add SM8550 LPASS
  pinctrl: at91: use devm_kasprintf() to avoid potential leaks
  dt-bindings: pinctrl: qcom: correct gpio-ranges in examples
  dt-bindings: pinctrl: qcom,msm8994: correct number of GPIOs
  dt-bindings: pinctrl: qcom,sdx55: correct GPIO name pattern
  dt-bindings: pinctrl: qcom,msm8953: correct GPIO name pattern
  dt-bindings: pinctrl: qcom,sm6375: correct GPIO name pattern and example
  dt-bindings: pinctrl: qcom,msm8909: correct GPIO name pattern and example
  ...
This commit is contained in:
Linus Torvalds
2023-02-22 11:05:56 -08:00
parent 17bbc46fc9 099f37a539
commit d5176cdbf6
147 changed files with 12970 additions and 1380 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/pinctrl/fsl,imx8mm-pinctrl.yaml → Documentation/devicetree/bindings/pinctrl/fsl,imx8m-pinctrl.yaml
+15 -9
View File
@@ -1,13 +1,13 @@
# SPDX-License-Identifier: GPL-2.0
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mm-pinctrl.yaml#
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8m-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IMX8MM IOMUX Controller
title: Freescale IMX8M IOMUX Controller
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
- Peng Fan <peng.fan@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
@@ -15,7 +15,11 @@ description:
properties:
compatible:
const: fsl,imx8mm-iomuxc
enum:
- fsl,imx8mm-iomuxc
- fsl,imx8mn-iomuxc
- fsl,imx8mp-iomuxc
- fsl,imx8mq-iomuxc
reg:
maxItems: 1
@@ -34,9 +38,10 @@ patternProperties:
each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm64/boot/dts/freescale/imx8mm-pinfunc.h>. The last
integer CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX8M Mini Reference Manual for detailed CONFIG settings.
be found in <arch/arm64/boot/dts/freescale/imx8m[m,n,p,q]-pinfunc.h>.
The last integer CONFIG is the pad setting value like pull-up on this
pin. Please refer to i.MX8M Mini/Nano/Plus/Quad Reference Manual for
detailed CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
@@ -51,7 +56,8 @@ patternProperties:
- description: |
"input_val" indicates the select input value to be applied.
- description: |
"pad_setting" indicates the pad configuration value to be applied.
"pad_setting" indicates the pad configuration value to be
applied.
required:
- fsl,pins
Documentation/devicetree/bindings/pinctrl/fsl,imx8mn-pinctrl.yaml
-84
View File
@@ -1,84 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mn-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IMX8MN IOMUX Controller
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
properties:
compatible:
const: fsl,imx8mn-iomuxc
reg:
maxItems: 1
# Client device subnode's properties
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm64/boot/dts/freescale/imx8mn-pinfunc.h>. The last
integer CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX8M Nano Reference Manual for detailed CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"mux_reg" indicates the offset of mux register.
- description: |
"conf_reg" indicates the offset of pad configuration register.
- description: |
"input_reg" indicates the offset of select input register.
- description: |
"mux_val" indicates the mux value to be applied.
- description: |
"input_val" indicates the select input value to be applied.
- description: |
"pad_setting" indicates the pad configuration value to be applied.
required:
- fsl,pins
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
- reg
additionalProperties: false
examples:
# Pinmux controller node
- |
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mn-iomuxc";
reg = <0x30330000 0x10000>;
pinctrl_uart2: uart2grp {
fsl,pins =
<0x23C 0x4A4 0x4FC 0x0 0x0 0x140>,
<0x240 0x4A8 0x000 0x0 0x0 0x140>;
};
};
...
Documentation/devicetree/bindings/pinctrl/fsl,imx8mp-pinctrl.yaml
-84
View File
@@ -1,84 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mp-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IMX8MP IOMUX Controller
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
properties:
compatible:
const: fsl,imx8mp-iomuxc
reg:
maxItems: 1
# Client device subnode's properties
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm64/boot/dts/freescale/imx8mp-pinfunc.h>. The last
integer CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX8M Plus Reference Manual for detailed CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"mux_reg" indicates the offset of mux register.
- description: |
"conf_reg" indicates the offset of pad configuration register.
- description: |
"input_reg" indicates the offset of select input register.
- description: |
"mux_val" indicates the mux value to be applied.
- description: |
"input_val" indicates the select input value to be applied.
- description: |
"pad_setting" indicates the pad configuration value to be applied.
required:
- fsl,pins
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
- reg
additionalProperties: false
examples:
# Pinmux controller node
- |
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mp-iomuxc";
reg = <0x30330000 0x10000>;
pinctrl_uart2: uart2grp {
fsl,pins =
<0x228 0x488 0x5F0 0x0 0x6 0x49>,
<0x228 0x488 0x000 0x0 0x0 0x49>;
};
};
...
Documentation/devicetree/bindings/pinctrl/fsl,imx8mq-pinctrl.yaml
-84
View File
@@ -1,84 +0,0 @@
# SPDX-License-Identifier: GPL-2.0
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/fsl,imx8mq-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Freescale IMX8MQ IOMUX Controller
maintainers:
- Anson Huang <Anson.Huang@nxp.com>
description:
Please refer to fsl,imx-pinctrl.txt and pinctrl-bindings.txt in this directory
for common binding part and usage.
properties:
compatible:
const: fsl,imx8mq-iomuxc
reg:
maxItems: 1
# Client device subnode's properties
patternProperties:
'grp$':
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
properties:
fsl,pins:
description:
each entry consists of 6 integers and represents the mux and config
setting for one pin. The first 5 integers <mux_reg conf_reg input_reg
mux_val input_val> are specified using a PIN_FUNC_ID macro, which can
be found in <arch/arm64/boot/dts/freescale/imx8mq-pinfunc.h>. The last
integer CONFIG is the pad setting value like pull-up on this pin. Please
refer to i.MX8M Quad Reference Manual for detailed CONFIG settings.
$ref: /schemas/types.yaml#/definitions/uint32-matrix
items:
items:
- description: |
"mux_reg" indicates the offset of mux register.
- description: |
"conf_reg" indicates the offset of pad configuration register.
- description: |
"input_reg" indicates the offset of select input register.
- description: |
"mux_val" indicates the mux value to be applied.
- description: |
"input_val" indicates the select input value to be applied.
- description: |
"pad_setting" indicates the pad configuration value to be applied.
required:
- fsl,pins
additionalProperties: false
allOf:
- $ref: "pinctrl.yaml#"
required:
- compatible
- reg
additionalProperties: false
examples:
# Pinmux controller node
- |
iomuxc: pinctrl@30330000 {
compatible = "fsl,imx8mq-iomuxc";
reg = <0x30330000 0x10000>;
pinctrl_uart1: uart1grp {
fsl,pins =
<0x234 0x49C 0x4F4 0x0 0x0 0x49>,
<0x238 0x4A0 0x4F4 0x0 0x0 0x49>;
};
};
...
Documentation/devicetree/bindings/pinctrl/mediatek,mt65xx-pinctrl.yaml
+6 -6
View File
@@ -70,11 +70,11 @@ allOf:
- $ref: "pinctrl.yaml#"
patternProperties:
'-[0-9]+$':
'pins$':
type: object
additionalProperties: false
patternProperties:
'pins':
'(^pins|pins?$)':
type: object
additionalProperties: false
description: |
@@ -158,7 +158,7 @@ examples:
<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
i2c0_pins_a: i2c0-0 {
i2c0_pins_a: i2c0-pins {
pins1 {
pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
<MT8135_PIN_101_SCL0__FUNC_SCL0>;
@@ -166,7 +166,7 @@ examples:
};
};
i2c1_pins_a: i2c1-0 {
i2c1_pins_a: i2c1-pins {
pins {
pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
<MT8135_PIN_196_SCL1__FUNC_SCL1>;
@@ -174,7 +174,7 @@ examples:
};
};
i2c2_pins_a: i2c2-0 {
i2c2_pins_a: i2c2-pins {
pins1 {
pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
bias-pull-down;
@@ -186,7 +186,7 @@ examples:
};
};
i2c3_pins_a: i2c3-0 {
i2c3_pins_a: i2c3-pins {
pins1 {
pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
<MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
Documentation/devicetree/bindings/pinctrl/mediatek,mt7622-pinctrl.yaml
+4 -4
View File
@@ -61,11 +61,11 @@ then:
- "#interrupt-cells"
patternProperties:
'-[0-9]+$':
'-pins(-[a-z]+)?$':
type: object
additionalProperties: false
patternProperties:
'mux':
'^mux(-|$)':
type: object
additionalProperties: false
description: |
@@ -244,7 +244,7 @@ patternProperties:
groups:
enum: [wf0_2g, wf0_5g]
'conf':
'^conf(-|$)':
type: object
additionalProperties: false
description: |
@@ -348,7 +348,7 @@ examples:
gpio-controller;
#gpio-cells = <2>;
pinctrl_eth_default: eth-0 {
pinctrl_eth_default: eth-pins {
mux-mdio {
groups = "mdc_mdio";
function = "eth";
Documentation/devicetree/bindings/pinctrl/mediatek,mt7981-pinctrl.yaml
+475
View File
@@ -0,0 +1,475 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt7981-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT7981 Pin Controller
maintainers:
- Daniel Golle <daniel@makrotopia.org>
description:
The MediaTek's MT7981 Pin controller is used to control SoC pins.
properties:
compatible:
enum:
- mediatek,mt7981-pinctrl
reg:
minItems: 9
maxItems: 9
reg-names:
items:
- const: gpio
- const: iocfg_rt
- const: iocfg_rm
- const: iocfg_rb
- const: iocfg_lb
- const: iocfg_bl
- const: iocfg_tm
- const: iocfg_tl
- const: eint
gpio-controller: true
"#gpio-cells":
const: 2
description: >
Number of cells in GPIO specifier. Since the generic GPIO binding is used,
the amount of cells must be specified as 2. See the below mentioned gpio
binding representation for description of particular cells.
gpio-ranges:
minItems: 1
maxItems: 5
description: GPIO valid number range.
interrupt-controller: true
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
allOf:
- $ref: pinctrl.yaml#
required:
- compatible
- reg
- reg-names
- gpio-controller
- "#gpio-cells"
patternProperties:
'-pins$':
type: object
additionalProperties: false
patternProperties:
'^.*mux.*$':
type: object
additionalProperties: false
description: |
pinmux configuration nodes.
The following table shows the effective values of "group", "function"
properties and chip pinout pins
groups function pins (in pin#)
---------------------------------------------------------------------
"wa_aice1" "wa_aice" 0, 1
"wa_aice2" "wa_aice" 0, 1
"wm_uart_0" "uart" 0, 1
"dfd" "dfd" 0, 1, 4, 5
"watchdog" "watchdog" 2
"pcie_pereset" "pcie" 3
"jtag" "jtag" 4, 5, 6, 7, 8
"wm_jtag_0" "jtag" 4, 5, 6, 7, 8
"wo0_jtag_0" "jtag" 9, 10, 11, 12, 13
"uart2_0" "uart" 4, 5, 6, 7
"gbe_led0" "led" 8
"pta_ext_0" "pta" 4, 5, 6
"pwm2" "pwm" 7
"net_wo0_uart_txd_0" "uart" 8
"spi1_0" "spi" 4, 5, 6, 7
"i2c0_0" "i2c" 6, 7
"dfd_ntrst" "dfd" 8
"wm_aice1" "wa_aice" 9, 10
"pwm0_0" "pwm" 13
"pwm0_1" "pwm" 15
"pwm1_0" "pwm" 14
"pwm1_1" "pwm" 15
"net_wo0_uart_txd_1" "uart" 14
"net_wo0_uart_txd_2" "uart" 15
"gbe_led1" "led" 13
"pcm" "pcm" 9, 10, 11, 12, 13, 25
"watchdog1" "watchdog" 13
"udi" "udi" 9, 10, 11, 12, 13
"drv_vbus" "usb" 14
"emmc_45" "flash" 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25
"snfi" "flash" 16, 17, 18, 19, 20, 21
"spi0" "spi" 16, 17, 18, 19
"spi0_wp_hold" "spi" 20, 21
"spi1_1" "spi" 22, 23, 24, 25
"spi2" "spi" 26, 27, 28, 29
"spi2_wp_hold" "spi" 30, 31
"uart1_0" "uart" 16, 17, 18, 19
"uart1_1" "uart" 26, 27, 28, 29
"uart2_1" "uart" 22, 23, 24, 25
"pta_ext_1" "pta" 22, 23, 24
"wm_aurt_1" "uart" 20, 21
"wm_aurt_2" "uart" 30, 31
"wm_jtag_1" "jtag" 20, 21, 22, 23, 24
"wo0_jtag_1" "jtag" 25, 26, 27, 28, 29
"wa_aice3" "wa_aice" 28, 20
"wm_aice2" "wa_aice" 30, 31
"i2c0_1" "i2c" 30, 31
"u2_phy_i2c" "i2c" 30, 31
"uart0" "uart" 32, 33
"sgmii1_phy_i2c" "i2c" 32, 33
"u3_phy_i2c" "i2c" 32, 33
"sgmii0_phy_i2c" "i2c" 32, 33
"pcie_clk" "pcie" 34
"pcie_wake" "pcie" 35
"i2c0_2" "i2c" 36, 37
"smi_mdc_mdio" "eth" 36, 37
"gbe_ext_mdc_mdio" "eth" 36, 37
"wf0_mode1" "eth" 40, 41, 42, 43, 44, 45, 46, 47, 48,
49, 50, 51, 52, 53, 54, 55, 56
"wf0_mode3" "eth" 45, 46, 47, 48, 49, 51
"wf2g_led0" "led" 30
"wf2g_led1" "led" 34
"wf5g_led0" "led" 31
"wf5g_led1" "led" 35
"mt7531_int" "eth" 38
"ant_sel" "ant" 14, 15, 16, 17, 18, 19, 20, 21, 22
23, 24, 25, 34, 35
$ref: /schemas/pinctrl/pinmux-node.yaml
properties:
function:
description:
A string containing the name of the function to mux to the group.
enum: [wa_aice, dfd, jtag, pta, pcm, udi, usb, ant, eth, i2c, led,
pwm, spi, uart, watchdog, flash, pcie]
groups:
description:
An array of strings. Each string contains the name of a group.
required:
- function
- groups
allOf:
- if:
properties:
function:
const: wa_aice
then:
properties:
groups:
enum: [wa_aice1, wa_aice2, wm_aice1_1, wa_aice3, wm_aice1_2]
- if:
properties:
function:
const: dfd
then:
properties:
groups:
enum: [dfd, dfd_ntrst]
- if:
properties:
function:
const: jtag
then:
properties:
groups:
enum: [jtag, wm_jtag_0, wo0_jtag_0, wo0_jtag_1, wm_jtag_1]
- if:
properties:
function:
const: pta
then:
properties:
groups:
enum: [pta_ext_0, pta_ext_1]
- if:
properties:
function:
const: pcm
then:
properties:
groups:
enum: [pcm]
- if:
properties:
function:
const: udi
then:
properties:
groups:
enum: [udi]
- if:
properties:
function:
const: usb
then:
properties:
groups:
enum: [drv_vbus]
- if:
properties:
function:
const: ant
then:
properties:
groups:
enum: [ant_sel]
- if:
properties:
function:
const: eth
then:
properties:
groups:
enum: [smi_mdc_mdio, gbe_ext_mdc_mdio, wf0_mode1, wf0_mode3,
mt7531_int]
- if:
properties:
function:
const: i2c
then:
properties:
groups:
enum: [i2c0_0, i2c0_1, u2_phy_i2c, sgmii1_phy_i2c, u3_phy_i2c,
sgmii0_phy_i2c, i2c0_2]
- if:
properties:
function:
const: led
then:
properties:
groups:
enum: [gbe_led0, gbe_led1, wf2g_led0, wf2g_led1, wf5g_led0, wf5g_led1]
- if:
properties:
function:
const: pwm
then:
properties:
groups:
items:
enum: [pwm2, pwm0_0, pwm0_1, pwm1_0, pwm1_1]
maxItems: 3
- if:
properties:
function:
const: spi
then:
properties:
groups:
items:
enum: [spi1_0, spi0, spi0_wp_hold, spi1_1, spi2, spi2_wp_hold]
maxItems: 4
- if:
properties:
function:
const: uart
then:
properties:
groups:
items:
enum: [wm_uart_0, uart2_0, net_wo0_uart_txd_0,
net_wo0_uart_txd_1, net_wo0_uart_txd_2, uart1_0,
uart1_1, uart2_1, wm_aurt_1, wm_aurt_2, uart0]
- if:
properties:
function:
const: watchdog
then:
properties:
groups:
enum: [watchdog]
- if:
properties:
function:
const: flash
then:
properties:
groups:
items:
enum: [emmc_45, snfi]
maxItems: 1
- if:
properties:
function:
const: pcie
then:
properties:
groups:
items:
enum: [pcie_clk, pcie_wake, pcie_pereset]
maxItems: 3
'^.*conf.*$':
type: object
additionalProperties: false
description: pinconf configuration nodes.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pins:
description:
An array of strings. Each string contains the name of a pin.
items:
enum: [GPIO_WPS, GPIO_RESET, SYS_WATCHDOG, PCIE_PERESET_N,
JTAG_JTDO, JTAG_JTDI, JTAG_JTMS, JTAG_JTCLK, JTAG_JTRST_N,
WO_JTAG_JTDO, WO_JTAG_JTDI, WO_JTAG_JTMS, WO_JTAG_JTCLK,
WO_JTAG_JTRST_N, USB_VBUS, PWM0, SPI0_CLK, SPI0_MOSI,
SPI0_MISO, SPI0_CS, SPI0_HOLD, SPI0_WP, SPI1_CLK, SPI1_MOSI,
SPI1_MISO, SPI1_CS, SPI2_CLK, SPI2_MOSI, SPI2_MISO, SPI2_CS,
SPI2_HOLD, SPI2_WP, UART0_RXD, UART0_TXD, PCIE_CLK_REQ,
PCIE_WAKE_N, SMI_MDC, SMI_MDIO, GBE_INT, GBE_RESET,
WF_DIG_RESETB, WF_CBA_RESETB, WF_XO_REQ, WF_TOP_CLK,
WF_TOP_DATA, WF_HB1, WF_HB2, WF_HB3, WF_HB4, WF_HB0,
WF_HB0_B, WF_HB5, WF_HB6, WF_HB7, WF_HB8, WF_HB9, WF_HB10]
maxItems: 57
bias-disable: true
bias-pull-up:
oneOf:
- type: boolean
description: normal pull up.
- enum: [100, 101, 102, 103]
description: >
PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
dt-bindings/pinctrl/mt65xx.h.
bias-pull-down:
oneOf:
- type: boolean
description: normal pull down.
- enum: [100, 101, 102, 103]
description: >
PUPD/R1/R0 pull down type. See MTK_PUPD_SET_R1R0 defines in
dt-bindings/pinctrl/mt65xx.h.
input-enable: true
input-disable: true
output-enable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
drive-strength:
enum: [2, 4, 6, 8, 10, 12, 14, 16]
mediatek,pull-up-adv:
description: |
Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
Pull up setings for 2 pull resistors, R0 and R1. Valid arguments
are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Valid arguments for 'mediatek,pull-up-adv' are '0', '1', '2', '3'
Pull down setings for 2 pull resistors, R0 and R1. Valid arguments
are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
required:
- pins
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt65xx.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@11d00000 {
compatible = "mediatek,mt7981-pinctrl";
reg = <0 0x11d00000 0 0x1000>,
<0 0x11c00000 0 0x1000>,
<0 0x11c10000 0 0x1000>,
<0 0x11d20000 0 0x1000>,
<0 0x11e00000 0 0x1000>,
<0 0x11e20000 0 0x1000>,
<0 0x11f00000 0 0x1000>,
<0 0x11f10000 0 0x1000>,
<0 0x1000b000 0 0x1000>;
reg-names = "gpio", "iocfg_rt", "iocfg_rm",
"iocfg_rb", "iocfg_lb", "iocfg_bl",
"iocfg_tm", "iocfg_tl", "eint";
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&pio 0 0 56>;
interrupt-controller;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&gic>;
#interrupt-cells = <2>;
mdio_pins: mdio-pins {
mux {
function = "eth";
groups = "smi_mdc_mdio";
};
};
spi0_flash_pins: spi0-pins {
mux {
function = "spi";
groups = "spi0", "spi0_wp_hold";
};
conf-pu {
pins = "SPI0_CS", "SPI0_HOLD", "SPI0_WP";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-up = <MTK_PUPD_SET_R1R0_11>;
};
conf-pd {
pins = "SPI0_CLK", "SPI0_MOSI", "SPI0_MISO";
drive-strength = <MTK_DRIVE_8mA>;
bias-pull-down = <MTK_PUPD_SET_R1R0_11>;
};
};
pcie_pins: pcie-pins {
mux {
function = "pcie";
groups = "pcie_clk", "pcie_wake", "pcie_pereset";
};
};
};
};
Documentation/devicetree/bindings/pinctrl/mediatek,mt8183-pinctrl.yaml
+4 -4
View File
@@ -67,11 +67,11 @@ required:
- gpio-ranges
patternProperties:
'-[0-9]+$':
'-pins(-[a-z]+)?$':
type: object
additionalProperties: false
patternProperties:
'pins':
'^pins':
type: object
additionalProperties: false
description: |
@@ -210,7 +210,7 @@ examples:
interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>;
#interrupt-cells = <2>;
i2c0_pins_a: i2c-0 {
i2c0_pins_a: i2c0-pins {
pins1 {
pinmux = <PINMUX_GPIO48__FUNC_SCL5>,
<PINMUX_GPIO49__FUNC_SDA5>;
@@ -219,7 +219,7 @@ examples:
};
};
i2c1_pins_a: i2c-1 {
i2c1_pins_a: i2c1-pins {
pins {
pinmux = <PINMUX_GPIO50__FUNC_SCL3>,
<PINMUX_GPIO51__FUNC_SDA3>;
Documentation/devicetree/bindings/pinctrl/mediatek,mt8365-pinctrl.yaml
+197
View File
@@ -0,0 +1,197 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/mediatek,mt8365-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek MT8365 Pin Controller
maintainers:
- Zhiyong Tao <zhiyong.tao@mediatek.com>
- Bernhard Rosenkränzer <bero@baylibre.com>
description: |
The MediaTek's MT8365 Pin controller is used to control SoC pins.
properties:
compatible:
const: mediatek,mt8365-pinctrl
reg:
maxItems: 1
mediatek,pctl-regmap:
$ref: /schemas/types.yaml#/definitions/phandle-array
items:
maxItems: 1
minItems: 1
maxItems: 2
description: |
Should be phandles of the syscfg node.
gpio-controller: true
"#gpio-cells":
const: 2
description: |
Number of cells in GPIO specifier. Since the generic GPIO
binding is used, the amount of cells must be specified as 2. See the below
mentioned gpio binding representation for description of particular cells.
interrupt-controller: true
interrupts:
maxItems: 1
"#interrupt-cells":
const: 2
patternProperties:
"-pins$":
type: object
additionalProperties: false
patternProperties:
"pins$":
type: object
additionalProperties: false
description: |
A pinctrl node should contain at least one subnode representing the
pinctrl groups available on the machine. Each subnode will list the
pins it needs, and how they should be configured, with regard to muxer
configuration, pullups, drive strength, input enable/disable and input
schmitt.
$ref: /schemas/pinctrl/pincfg-node.yaml
properties:
pinmux:
description:
integer array, represents gpio pin number and mux setting.
Supported pin number and mux varies for different SoCs, and are
defined as macros in <soc>-pinfunc.h directly.
bias-disable: true
bias-pull-up:
description: |
Besides generic pinconfig options, it can be used as the pull up
settings for 2 pull resistors, R0 and R1. User can configure those
special pins.
bias-pull-down: true
input-enable: true
input-disable: true
output-low: true
output-high: true
input-schmitt-enable: true
input-schmitt-disable: true
mediatek,drive-strength-adv:
description: |
Describe the specific driving setup property.
For I2C pins, the existing generic driving setup can only support
2/4/6/8/10/12/14/16mA driving. But in specific driving setup, they
can support 0.125/0.25/0.5/1mA adjustment. If we enable specific
driving setup, the existing generic setup will be disabled.
The specific driving setup is controlled by E1E0EN.
When E1=0/E0=0, the strength is 0.125mA.
When E1=0/E0=1, the strength is 0.25mA.
When E1=1/E0=0, the strength is 0.5mA.
When E1=1/E0=1, the strength is 1mA.
EN is used to enable or disable the specific driving setup.
Valid arguments are described as below:
0: (E1, E0, EN) = (0, 0, 0)
1: (E1, E0, EN) = (0, 0, 1)
2: (E1, E0, EN) = (0, 1, 0)
3: (E1, E0, EN) = (0, 1, 1)
4: (E1, E0, EN) = (1, 0, 0)
5: (E1, E0, EN) = (1, 0, 1)
6: (E1, E0, EN) = (1, 1, 0)
7: (E1, E0, EN) = (1, 1, 1)
So the valid arguments are from 0 to 7.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3, 4, 5, 6, 7]
mediatek,pull-up-adv:
description: |
Pull up setings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,pull-down-adv:
description: |
Pull down settings for 2 pull resistors, R0 and R1. User can
configure those special pins. Valid arguments are described as below:
0: (R1, R0) = (0, 0) which means R1 disabled and R0 disabled.
1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled.
2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled.
3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled.
$ref: /schemas/types.yaml#/definitions/uint32
enum: [0, 1, 2, 3]
mediatek,tdsel:
description: |
An integer describing the steps for output level shifter duty
cycle when asserted (high pulse width adjustment). Valid arguments
are from 0 to 15.
$ref: /schemas/types.yaml#/definitions/uint32
mediatek,rdsel:
description: |
An integer describing the steps for input level shifter duty cycle
when asserted (high pulse width adjustment). Valid arguments are
from 0 to 63.
$ref: /schemas/types.yaml#/definitions/uint32
required:
- pinmux
required:
- compatible
- reg
- gpio-controller
- "#gpio-cells"
allOf:
- $ref: pinctrl.yaml#
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/pinctrl/mt8365-pinfunc.h>
soc {
#address-cells = <2>;
#size-cells = <2>;
pio: pinctrl@1000b000 {
compatible = "mediatek,mt8365-pinctrl";
reg = <0 0x1000b000 0 0x1000>;
mediatek,pctl-regmap = <&syscfg_pctl>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
pio-pins {
pins {
pinmux = <MT8365_PIN_59_SDA1__FUNC_SDA1_0>, <MT8365_PIN_60_SCL1__FUNC_SCL1_0>;
mediatek,pull-up-adv = <3>;
mediatek,drive-strength-adv = <00>;
bias-pull-up;
};
};
};
};
Documentation/devicetree/bindings/pinctrl/qcom,ipq5332-tlmm.yaml
+134
View File
@@ -0,0 +1,134 @@
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
%YAML 1.2
---
$id: http://devicetree.org/schemas/pinctrl/qcom,ipq5332-tlmm.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#
title: Qualcomm IPQ5332 TLMM pin controller
maintainers:
- Bjorn Andersson <andersson@kernel.org>
- Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
description: |
Top Level Mode Multiplexer pin controller in Qualcomm IPQ5332 SoC.
allOf:
- $ref: /schemas/pinctrl/qcom,tlmm-common.yaml#
properties:
compatible:
const: qcom,ipq5332-tlmm
reg:
maxItems: 1
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
"#gpio-cells": true
gpio-ranges: true
wakeup-parent: true
gpio-reserved-ranges:
minItems: 1
maxItems: 27
gpio-line-names:
maxItems: 53
patternProperties:
"-state$":
oneOf:
- $ref: "#/$defs/qcom-ipq5332-tlmm-state"
- patternProperties:
"-pins$":
$ref: "#/$defs/qcom-ipq5332-tlmm-state"
additionalProperties: false
$defs:
qcom-ipq5332-tlmm-state:
type: object
description:
Pinctrl node's client devices use subnodes for desired pin configuration.
Client device subnodes use below standard properties.
$ref: qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state
properties:
pins:
description:
List of gpio pins affected by the properties specified in this
subnode.
items:
pattern: "^gpio([0-9]|[1-4][0-9]|5[0-2])$"
minItems: 1
maxItems: 36
function:
description:
Specify the alternative function to be configured for the specified
pins.
enum: [ atest_char, atest_char0, atest_char1, atest_char2, atest_char3,
atest_tic, audio_pri, audio_pri0, audio_pri1, audio_sec,
audio_sec0, audio_sec1, blsp0_i2c, blsp0_spi, blsp0_uart0,
blsp0_uart1, blsp1_i2c0, blsp1_i2c1, blsp1_spi0, blsp1_spi1,
blsp1_uart0, blsp1_uart1, blsp1_uart2, blsp2_i2c0, blsp2_i2c1,
blsp2_spi, blsp2_spi0, blsp2_spi1, core_voltage, cri_trng0,
cri_trng1, cri_trng2, cri_trng3, cxc_clk, cxc_data, dbg_out,
gcc_plltest, gcc_tlmm, gpio, lock_det, mac0, mac1, mdc0, mdc1,
mdio0, mdio1, pc, pcie0_clk, pcie0_wake, pcie1_clk, pcie1_wake,
pcie2_clk, pcie2_wake, pll_test, prng_rosc0, prng_rosc1,
prng_rosc2, prng_rosc3, pta, pwm0, pwm1, pwm2, pwm3,
qdss_cti_trig_in_a0, qdss_cti_trig_in_a1, qdss_cti_trig_in_b0,
qdss_cti_trig_in_b1, qdss_cti_trig_out_a0,
qdss_cti_trig_out_a1, qdss_cti_trig_out_b0,
qdss_cti_trig_out_b1, qdss_traceclk_a, qdss_traceclk_b,
qdss_tracectl_a, qdss_tracectl_b, qdss_tracedata_a,
qdss_tracedata_b, qspi_data, qspi_clk, qspi_cs, resout, rx0,
rx1, sdc_data, sdc_clk, sdc_cmd, tsens_max, wci_txd, wci_rxd,
wsi_clk, wsi_clk3, wsi_data, wsi_data3, wsis_reset, xfem ]
bias-pull-down: true
bias-pull-up: true
bias-disable: true
drive-strength: true
input-enable: true
output-high: true
output-low: true
required:
- pins
additionalProperties: false
required:
- compatible
- reg
additionalProperties: false
examples:
- |
#include <dt-bindings/interrupt-controller/arm-gic.h>
tlmm: pinctrl@1000000 {
compatible = "qcom,ipq5332-tlmm";
reg = <0x01000000 0x300000>;
gpio-controller;
#gpio-cells = <0x2>;
gpio-ranges = <&tlmm 0 0 53>;
interrupts = <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <0x2>;
serial0-state {
pins = "gpio18", "gpio19";
function = "blsp0_uart0";
drive-strength = <8>;
bias-pull-up;
};
};
Documentation/devicetree/bindings/pinctrl/qcom,ipq6018-pinctrl.yaml
+3 -1
View File
@@ -19,7 +19,9 @@ properties:
reg:
maxItems: 1
interrupts: true
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
Documentation/devicetree/bindings/pinctrl/qcom,ipq8074-pinctrl.yaml
+3 -1
View File
@@ -20,7 +20,9 @@ properties:
reg:
maxItems: 1
interrupts: true
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
Documentation/devicetree/bindings/pinctrl/qcom,mdm9607-tlmm.yaml
+3 -1
View File
@@ -22,7 +22,9 @@ properties:
reg:
maxItems: 1
interrupts: true
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
Documentation/devicetree/bindings/pinctrl/qcom,mdm9615-pinctrl.yaml
+3 -1
View File
@@ -20,7 +20,9 @@ properties:
reg:
maxItems: 1
interrupts: true
interrupts:
maxItems: 1
interrupt-controller: true
'#interrupt-cells': true
gpio-controller: true
Documentation/devicetree/bindings/pinctrl/qcom,msm8226-pinctrl.yaml
+6 -4
View File
@@ -20,7 +20,9 @@ properties:
description: Specifies the base address and size of the TLMM register space
maxItems: 1
interrupts: true
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
@@ -54,7 +56,7 @@ $defs:
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-1][0-6])$"
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-6])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd, sdc2_data ]
minItems: 1
maxItems: 36
@@ -66,8 +68,8 @@ $defs:
enum: [ gpio, cci_i2c0, blsp_uim1, blsp_uim2, blsp_uim3, blsp_uim5,
blsp_i2c1, blsp_i2c2, blsp_i2c3, blsp_i2c4, blsp_i2c5, blsp_spi1,
blsp_spi2, blsp_spi3, blsp_spi5, blsp_uart1, blsp_uart2,
blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1, sdc3,
wlan ]
blsp_uart3, blsp_uart4, blsp_uart5, cam_mclk0, cam_mclk1,
gp0_clk, gp1_clk, sdc3, wlan ]
bias-pull-down: true
bias-pull-up: true
Documentation/devicetree/bindings/pinctrl/qcom,msm8660-pinctrl.yaml
+3 -1
View File
@@ -20,7 +20,9 @@ properties:
reg:
maxItems: 1
interrupts: true
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
Documentation/devicetree/bindings/pinctrl/qcom,msm8909-tlmm.yaml
+5 -3
View File
@@ -22,7 +22,9 @@ properties:
reg:
maxItems: 1
interrupts: true
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
@@ -61,7 +63,7 @@ $defs:
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-7])$"
- pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc2_clk, sdc2_cmd,
sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0, qdsd_data1,
qdsd_data2, qdsd_data3 ]
@@ -125,7 +127,7 @@ examples:
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
gpio-ranges = <&tlmm 0 0 117>;
gpio-ranges = <&tlmm 0 0 113>;
interrupt-controller;
#interrupt-cells = <2>;
Documentation/devicetree/bindings/pinctrl/qcom,msm8916-pinctrl.yaml
+3 -1
View File
@@ -20,7 +20,9 @@ properties:
reg:
maxItems: 1
interrupts: true
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
Documentation/devicetree/bindings/pinctrl/qcom,msm8953-pinctrl.yaml
+4 -2
View File
@@ -19,7 +19,9 @@ properties:
reg:
maxItems: 1
interrupts: true
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true
@@ -51,7 +53,7 @@ $defs:
subnode.
items:
oneOf:
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-7][0-9])$"
- pattern: "^gpio([0-9]|[1-9][0-9]|1[0-3][0-9]|14[01])$"
- enum: [ sdc1_clk, sdc1_cmd, sdc1_data, sdc1_rclk, sdc2_clk,
sdc2_cmd, sdc2_data, qdsd_clk, qdsd_cmd, qdsd_data0,
qdsd_data1, qdsd_data2, qdsd_data3 ]
Documentation/devicetree/bindings/pinctrl/qcom,msm8960-pinctrl.yaml
+3 -1
View File
@@ -20,7 +20,9 @@ properties:
reg:
maxItems: 1
interrupts: true
interrupts:
maxItems: 1
interrupt-controller: true
"#interrupt-cells": true
gpio-controller: true

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