mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: (71 commits) powerpc/44x: Update ppc44x_defconfig powerpc/watchdog: Make default timeout for Book-E watchdog a Kconfig option fsl_rio: Add comments for sRIO registers. powerpc/fsl-booke: Add e55xx (64-bit) smp defconfig powerpc/fsl-booke: Add p5020 DS board support powerpc/fsl-booke64: Use TLB CAMs to cover linear mapping on FSL 64-bit chips powerpc/fsl-booke: Add support for FSL Arch v1.0 MMU in setup_page_sizes powerpc/fsl-booke: Add support for FSL 64-bit e5500 core powerpc/85xx: add cache-sram support powerpc/85xx: add ngPIXIS FPGA device tree node to the P1022DS board powerpc: Fix compile error with paca code on ppc64e powerpc/fsl-booke: Add p3041 DS board support oprofile/fsl emb: Don't set MSR[PMM] until after clearing the interrupt. powerpc/fsl-booke: Add PCI device ids for P2040/P3041/P5010/P5020 QoirQ chips powerpc/mpc8xxx_gpio: Add support for 'qoriq-gpio' controllers powerpc/fsl_booke: Add support to boot from core other than 0 powerpc/p1022: Add probing for individual DMA channels powerpc/fsl_soc: Search all global-utilities nodes for rstccr powerpc: Fix invalid page flags in create TLB CAM path for PTE_64BIT powerpc/mpc83xx: Support for MPC8308 P1M board ... Fix up conflict with the generic irq_work changes in arch/powerpc/kernel/time.c
This commit is contained in:
Linus Torvalds
@@ -20,7 +20,7 @@
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#include <string.h>
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/* CHRP note section */
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||||
char arch[] = "PowerPC";
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static const char arch[] = "PowerPC";
|
||||
|
||||
#define N_DESCR 6
|
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unsigned int descr[N_DESCR] = {
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||||
@@ -33,7 +33,7 @@ unsigned int descr[N_DESCR] = {
|
||||
};
|
||||
|
||||
/* RPA note section */
|
||||
char rpaname[] = "IBM,RPA-Client-Config";
|
||||
static const char rpaname[] = "IBM,RPA-Client-Config";
|
||||
|
||||
/*
|
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* Note: setting ignore_my_client_config *should* mean that OF ignores
|
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|
||||
@@ -0,0 +1,254 @@
|
||||
/*
|
||||
* Device Tree for Bluestone (APM821xx) board.
|
||||
*
|
||||
* Copyright (c) 2010, Applied Micro Circuits Corporation
|
||||
* Author: Tirumala R Marri <tmarri@apm.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or
|
||||
* modify it under the terms of the GNU General Public License as
|
||||
* published by the Free Software Foundation; either version 2 of
|
||||
* the License, or (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
|
||||
* MA 02111-1307 USA
|
||||
*
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||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
model = "apm,bluestone";
|
||||
compatible = "apm,bluestone";
|
||||
dcr-parent = <&{/cpus/cpu@0}>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &EMAC0;
|
||||
serial0 = &UART0;
|
||||
serial1 = &UART1;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu@0 {
|
||||
device_type = "cpu";
|
||||
model = "PowerPC,apm821xx";
|
||||
reg = <0x00000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
timebase-frequency = <0>; /* Filled in by U-Boot */
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-size = <32768>;
|
||||
d-cache-size = <32768>;
|
||||
dcr-controller;
|
||||
dcr-access-method = "native";
|
||||
next-level-cache = <&L2C0>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x00000000 0x00000000>; /* Filled in by U-Boot */
|
||||
};
|
||||
|
||||
UIC0: interrupt-controller0 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <0>;
|
||||
dcr-reg = <0x0c0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
UIC1: interrupt-controller1 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <1>;
|
||||
dcr-reg = <0x0d0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x1e 0x4 0x1f 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC2: interrupt-controller2 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <2>;
|
||||
dcr-reg = <0x0e0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0xa 0x4 0xb 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
UIC3: interrupt-controller3 {
|
||||
compatible = "ibm,uic";
|
||||
interrupt-controller;
|
||||
cell-index = <3>;
|
||||
dcr-reg = <0x0f0 0x009>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
interrupts = <0x10 0x4 0x11 0x4>; /* cascade */
|
||||
interrupt-parent = <&UIC0>;
|
||||
};
|
||||
|
||||
SDR0: sdr {
|
||||
compatible = "ibm,sdr-apm821xx";
|
||||
dcr-reg = <0x00e 0x002>;
|
||||
};
|
||||
|
||||
CPR0: cpr {
|
||||
compatible = "ibm,cpr-apm821xx";
|
||||
dcr-reg = <0x00c 0x002>;
|
||||
};
|
||||
|
||||
plb {
|
||||
compatible = "ibm,plb4";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
ranges;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
SDRAM0: sdram {
|
||||
compatible = "ibm,sdram-apm821xx";
|
||||
dcr-reg = <0x010 0x002>;
|
||||
};
|
||||
|
||||
MAL0: mcmal {
|
||||
compatible = "ibm,mcmal2";
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descriptor-memory = "ocm";
|
||||
dcr-reg = <0x180 0x062>;
|
||||
num-tx-chans = <1>;
|
||||
num-rx-chans = <1>;
|
||||
#address-cells = <0>;
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||||
#size-cells = <0>;
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interrupt-parent = <&UIC2>;
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||||
interrupts = < /*TXEOB*/ 0x6 0x4
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/*RXEOB*/ 0x7 0x4
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/*SERR*/ 0x3 0x4
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/*TXDE*/ 0x4 0x4
|
||||
/*RXDE*/ 0x5 0x4
|
||||
};
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||||
|
||||
POB0: opb {
|
||||
compatible = "ibm,opb";
|
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#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0xb0000000 0x00000004 0xb0000000 0x50000000>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
|
||||
EBC0: ebc {
|
||||
compatible = "ibm,ebc";
|
||||
dcr-reg = <0x012 0x002>;
|
||||
#address-cells = <2>;
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||||
#size-cells = <1>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
/* ranges property is supplied by U-Boot */
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||||
ranges = < 0x00000003 0x00000000 0xe0000000 0x8000000>;
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interrupts = <0x6 0x4>;
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interrupt-parent = <&UIC1>;
|
||||
|
||||
nor_flash@0,0 {
|
||||
compatible = "amd,s29gl512n", "cfi-flash";
|
||||
bank-width = <2>;
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||||
reg = <0x00000000 0x00000000 0x00400000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
partition@0 {
|
||||
label = "kernel";
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||||
reg = <0x00000000 0x00180000>;
|
||||
};
|
||||
partition@180000 {
|
||||
label = "env";
|
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reg = <0x00180000 0x00020000>;
|
||||
};
|
||||
partition@1a0000 {
|
||||
label = "u-boot";
|
||||
reg = <0x001a0000 0x00060000>;
|
||||
};
|
||||
};
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||||
}
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||||
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||||
UART0: serial@ef600300 {
|
||||
device_type = "serial";
|
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compatible = "ns16550";
|
||||
reg = <0xef600300 0x00000008>;
|
||||
virtual-reg = <0xef600300>;
|
||||
clock-frequency = <0>; /* Filled in by U-Boot */
|
||||
current-speed = <0>; /* Filled in by U-Boot */
|
||||
interrupt-parent = <&UIC1>;
|
||||
interrupts = <0x1 0x4>;
|
||||
};
|
||||
|
||||
IIC0: i2c@ef600700 {
|
||||
compatible = "ibm,iic";
|
||||
reg = <0xef600700 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x2 0x4>;
|
||||
};
|
||||
|
||||
IIC1: i2c@ef600800 {
|
||||
compatible = "ibm,iic";
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reg = <0xef600800 0x00000014>;
|
||||
interrupt-parent = <&UIC0>;
|
||||
interrupts = <0x3 0x4>;
|
||||
};
|
||||
|
||||
RGMII0: emac-rgmii@ef601500 {
|
||||
compatible = "ibm,rgmii";
|
||||
reg = <0xef601500 0x00000008>;
|
||||
has-mdio;
|
||||
};
|
||||
|
||||
TAH0: emac-tah@ef601350 {
|
||||
compatible = "ibm,tah";
|
||||
reg = <0xef601350 0x00000030>;
|
||||
};
|
||||
|
||||
EMAC0: ethernet@ef600c00 {
|
||||
device_type = "network";
|
||||
compatible = "ibm,emac4sync";
|
||||
interrupt-parent = <&EMAC0>;
|
||||
interrupts = <0x0 0x1>;
|
||||
#interrupt-cells = <1>;
|
||||
#address-cells = <0>;
|
||||
#size-cells = <0>;
|
||||
interrupt-map = </*Status*/ 0x0 &UIC2 0x10 0x4
|
||||
/*Wake*/ 0x1 &UIC2 0x14 0x4>;
|
||||
reg = <0xef600c00 0x000000c4>;
|
||||
local-mac-address = [000000000000]; /* Filled in by U-Boot */
|
||||
mal-device = <&MAL0>;
|
||||
mal-tx-channel = <0>;
|
||||
mal-rx-channel = <0>;
|
||||
cell-index = <0>;
|
||||
max-frame-size = <9000>;
|
||||
rx-fifo-size = <16384>;
|
||||
tx-fifo-size = <2048>;
|
||||
phy-mode = "rgmii";
|
||||
phy-map = <0x00000000>;
|
||||
rgmii-device = <&RGMII0>;
|
||||
rgmii-channel = <0>;
|
||||
tah-device = <&TAH0>;
|
||||
tah-channel = <0>;
|
||||
has-inverted-stacr-oc;
|
||||
has-new-stacr-staopc;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,332 @@
|
||||
/*
|
||||
* mpc8308_p1m Device Tree Source
|
||||
*
|
||||
* Copyright 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "denx,mpc8308_p1m";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
aliases {
|
||||
ethernet0 = &enet0;
|
||||
ethernet1 = &enet1;
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
pci0 = &pci0;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
PowerPC,8308@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0x0>;
|
||||
d-cache-line-size = <32>;
|
||||
i-cache-line-size = <32>;
|
||||
d-cache-size = <16384>;
|
||||
i-cache-size = <16384>;
|
||||
timebase-frequency = <0>; // from bootloader
|
||||
bus-frequency = <0>; // from bootloader
|
||||
clock-frequency = <0>; // from bootloader
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>; // 128MB at 0
|
||||
};
|
||||
|
||||
localbus@e0005000 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,mpc8315-elbc", "fsl,elbc", "simple-bus";
|
||||
reg = <0xe0005000 0x1000>;
|
||||
interrupts = <77 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
|
||||
ranges = <0x0 0x0 0xfc000000 0x04000000
|
||||
0x1 0x0 0xfbff0000 0x00008000
|
||||
0x2 0x0 0xfbff8000 0x00008000>;
|
||||
|
||||
flash@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x4000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
|
||||
u-boot@0 {
|
||||
reg = <0x0 0x60000>;
|
||||
read-only;
|
||||
};
|
||||
env@60000 {
|
||||
reg = <0x60000 0x20000>;
|
||||
};
|
||||
env1@80000 {
|
||||
reg = <0x80000 0x20000>;
|
||||
};
|
||||
kernel@a0000 {
|
||||
reg = <0xa0000 0x200000>;
|
||||
};
|
||||
dtb@2a0000 {
|
||||
reg = <0x2a0000 0x20000>;
|
||||
};
|
||||
ramdisk@2c0000 {
|
||||
reg = <0x2c0000 0x640000>;
|
||||
};
|
||||
user@700000 {
|
||||
reg = <0x700000 0x3900000>;
|
||||
};
|
||||
};
|
||||
|
||||
can@1,0 {
|
||||
compatible = "nxp,sja1000";
|
||||
reg = <0x1 0x0 0x80>;
|
||||
interrupts = <18 0x8>;
|
||||
interrups-parent = <&ipic>;
|
||||
};
|
||||
|
||||
cpld@2,0 {
|
||||
compatible = "denx,mpc8308_p1m-cpld";
|
||||
reg = <0x2 0x0 0x8>;
|
||||
interrupts = <48 0x8>;
|
||||
interrups-parent = <&ipic>;
|
||||
};
|
||||
};
|
||||
|
||||
immr@e0000000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "fsl,mpc8308-immr", "simple-bus";
|
||||
ranges = <0 0xe0000000 0x00100000>;
|
||||
reg = <0xe0000000 0x00000200>;
|
||||
bus-frequency = <0>;
|
||||
|
||||
i2c@3000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3000 0x100>;
|
||||
interrupts = <14 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
fram@50 {
|
||||
compatible = "ramtron,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
};
|
||||
|
||||
i2c@3100 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl-i2c";
|
||||
reg = <0x3100 0x100>;
|
||||
interrupts = <15 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
dfsrr;
|
||||
pwm@28 {
|
||||
compatible = "maxim,ds1050";
|
||||
reg = <0x28>;
|
||||
};
|
||||
sensor@48 {
|
||||
compatible = "maxim,max6625";
|
||||
reg = <0x48>;
|
||||
};
|
||||
sensor@49 {
|
||||
compatible = "maxim,max6625";
|
||||
reg = <0x49>;
|
||||
};
|
||||
sensor@4b {
|
||||
compatible = "maxim,max6625";
|
||||
reg = <0x4b>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@23000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x23000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <38 0x8>;
|
||||
dr_mode = "peripheral";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
enet0: ethernet@24000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x24000 0x1000>;
|
||||
|
||||
cell-index = <0>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x24000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <32 0x8 33 0x8 34 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = < &phy1 >;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-mdio";
|
||||
reg = <0x520 0x20>;
|
||||
phy1: ethernet-phy@1 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <17 0x8>;
|
||||
reg = <0x1>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
phy2: ethernet-phy@2 {
|
||||
interrupt-parent = <&ipic>;
|
||||
interrupts = <19 0x8>;
|
||||
reg = <0x2>;
|
||||
device_type = "ethernet-phy";
|
||||
};
|
||||
tbi0: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
enet1: ethernet@25000 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
cell-index = <1>;
|
||||
device_type = "network";
|
||||
model = "eTSEC";
|
||||
compatible = "gianfar";
|
||||
reg = <0x25000 0x1000>;
|
||||
ranges = <0x0 0x25000 0x1000>;
|
||||
local-mac-address = [ 00 00 00 00 00 00 ];
|
||||
interrupts = <35 0x8 36 0x8 37 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
phy-handle = < &phy2 >;
|
||||
|
||||
mdio@520 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "fsl,gianfar-tbi";
|
||||
reg = <0x520 0x20>;
|
||||
tbi1: tbi-phy@11 {
|
||||
reg = <0x11>;
|
||||
device_type = "tbi-phy";
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
serial0: serial@4500 {
|
||||
cell-index = <0>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4500 0x100>;
|
||||
clock-frequency = <133333333>;
|
||||
interrupts = <9 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
serial1: serial@4600 {
|
||||
cell-index = <1>;
|
||||
device_type = "serial";
|
||||
compatible = "ns16550";
|
||||
reg = <0x4600 0x100>;
|
||||
clock-frequency = <133333333>;
|
||||
interrupts = <10 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
|
||||
gpio@c00 {
|
||||
#gpio-cells = <2>;
|
||||
compatible = "fsl,mpc8308-gpio", "fsl,mpc8349-gpio";
|
||||
reg = <0xc00 0x18>;
|
||||
interrupts = <74 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
gpio-controller;
|
||||
};
|
||||
|
||||
timer@500 {
|
||||
compatible = "fsl,mpc8308-gtm", "fsl,gtm";
|
||||
reg = <0x500 0x100>;
|
||||
interrupts = <90 8 78 8 84 8 72 8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
clock-frequency = <133333333>;
|
||||
};
|
||||
|
||||
/* IPIC
|
||||
* interrupts cell = <intr #, sense>
|
||||
* sense values match linux IORESOURCE_IRQ_* defines:
|
||||
* sense == 8: Level, low assertion
|
||||
* sense == 2: Edge, high-to-low change
|
||||
*/
|
||||
ipic: interrupt-controller@700 {
|
||||
compatible = "fsl,ipic";
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <2>;
|
||||
reg = <0x700 0x100>;
|
||||
device_type = "ipic";
|
||||
};
|
||||
|
||||
ipic-msi@7c0 {
|
||||
compatible = "fsl,ipic-msi";
|
||||
reg = <0x7c0 0x40>;
|
||||
msi-available-ranges = <0x0 0x100>;
|
||||
interrupts = < 0x43 0x8
|
||||
0x4 0x8
|
||||
0x51 0x8
|
||||
0x52 0x8
|
||||
0x56 0x8
|
||||
0x57 0x8
|
||||
0x58 0x8
|
||||
0x59 0x8 >;
|
||||
interrupt-parent = < &ipic >;
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci0: pcie@e0009000 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
#interrupt-cells = <1>;
|
||||
device_type = "pci";
|
||||
compatible = "fsl,mpc8308-pcie", "fsl,mpc8314-pcie";
|
||||
reg = <0xe0009000 0x00001000
|
||||
0xb0000000 0x01000000>;
|
||||
ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xb1000000 0 0x00800000>;
|
||||
bus-range = <0 0>;
|
||||
interrupt-map-mask = <0 0 0 0>;
|
||||
interrupt-map = <0 0 0 0 &ipic 1 8>;
|
||||
interrupts = <0x1 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
clock-frequency = <0>;
|
||||
|
||||
pcie@0 {
|
||||
#address-cells = <3>;
|
||||
#size-cells = <2>;
|
||||
device_type = "pci";
|
||||
reg = <0 0 0 0 0>;
|
||||
ranges = <0x02000000 0 0xa0000000
|
||||
0x02000000 0 0xa0000000
|
||||
0 0x10000000
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00800000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -148,6 +148,17 @@
|
||||
label = "reserved-nand";
|
||||
};
|
||||
};
|
||||
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,p1022ds-pixis";
|
||||
reg = <3 0 0x30>;
|
||||
interrupt-parent = <&mpic>;
|
||||
/*
|
||||
* IRQ8 is generated if the "EVENT" switch is pressed
|
||||
* and PX_CTL[EVESEL] is set to 00.
|
||||
*/
|
||||
interrupts = <8 8>;
|
||||
};
|
||||
};
|
||||
|
||||
soc@fffe00000 {
|
||||
|
||||
@@ -0,0 +1,68 @@
|
||||
CONFIG_44x=y
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_PCI_QUIRKS is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_BLUESTONE=y
|
||||
# CONFIG_EBONY is not set
|
||||
# CONFIG_KVM_GUEST is not set
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
CONFIG_CMDLINE=""
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
CONFIG_INET=y
|
||||
CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
CONFIG_IP_PNP_BOOTP=y
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_CONNECTOR=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=35000
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_NET_ETHERNET=y
|
||||
CONFIG_IBM_NEW_EMAC=y
|
||||
CONFIG_IBM_NEW_EMAC_RXB=256
|
||||
CONFIG_IBM_NEW_EMAC_TXB=256
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_NR_UARTS=2
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=2
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_SHARE_IRQ=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_IBM_IIC=y
|
||||
CONFIG_SENSORS_AD7414=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_RTC_CLASS=y
|
||||
CONFIG_RTC_DRV_M41T80=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS=y
|
||||
@@ -0,0 +1,84 @@
|
||||
CONFIG_PPC64=y
|
||||
CONFIG_PPC_BOOK3E_64=y
|
||||
# CONFIG_VIRT_CPU_ACCOUNTING is not set
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
CONFIG_SYSFS_DEPRECATED_V2=y
|
||||
CONFIG_BLK_DEV_INITRD=y
|
||||
# CONFIG_CC_OPTIMIZE_FOR_SIZE is not set
|
||||
CONFIG_EMBEDDED=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_KALLSYMS_EXTRA_PASS=y
|
||||
CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODULE_FORCE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_P5020_DS=y
|
||||
# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_SPARSE_IRQ=y
|
||||
# CONFIG_PCI is not set
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
CONFIG_BLK_DEV_RAM_SIZE=131072
|
||||
CONFIG_EEPROM_LEGACY=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_SERIO_LIBPS2=y
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
CONFIG_SERIAL_8250_EXTENDED=y
|
||||
CONFIG_SERIAL_8250_MANY_PORTS=y
|
||||
CONFIG_SERIAL_8250_DETECT_IRQ=y
|
||||
CONFIG_SERIAL_8250_RSA=y
|
||||
CONFIG_I2C=y
|
||||
# CONFIG_HWMON is not set
|
||||
CONFIG_VIDEO_OUTPUT_CONTROL=y
|
||||
# CONFIG_HID_SUPPORT is not set
|
||||
# CONFIG_USB_SUPPORT is not set
|
||||
CONFIG_DMADEVICES=y
|
||||
CONFIG_FSL_DMA=y
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=y
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_UTF8=m
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRC_ITU_T=m
|
||||
CONFIG_LIBCRC32C=m
|
||||
CONFIG_FRAME_WARN=1024
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_DEBUG_BUGVERBOSE is not set
|
||||
CONFIG_DEBUG_INFO=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_VIRQ_DEBUG=y
|
||||
CONFIG_CRYPTO=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_HMAC=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_SHA1=m
|
||||
CONFIG_CRYPTO_DES=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_DEV_TALITOS=y
|
||||
@@ -12,6 +12,7 @@ CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_BAMBOO=y
|
||||
CONFIG_BLUESTONE=y
|
||||
CONFIG_SAM440EP=y
|
||||
CONFIG_SEQUOIA=y
|
||||
CONFIG_TAISHAN=y
|
||||
@@ -97,14 +98,17 @@ CONFIG_USB_STORAGE=m
|
||||
CONFIG_EXT2_FS=y
|
||||
CONFIG_EXT3_FS=m
|
||||
# CONFIG_EXT3_DEFAULTS_TO_ORDERED is not set
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_VFAT_FS=m
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_UBIFS_FS=m
|
||||
CONFIG_UBIFS_FS_XATTR=y
|
||||
CONFIG_LOGFS=m
|
||||
CONFIG_CRAMFS=y
|
||||
CONFIG_SQUASHFS=m
|
||||
CONFIG_SQUASHFS_XATTR=y
|
||||
CONFIG_SQUASHFS_LZO=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V3=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
@@ -116,11 +120,8 @@ CONFIG_DEBUG_KERNEL=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
# CONFIG_RCU_CPU_STALL_DETECTOR is not set
|
||||
CONFIG_SYSCTL_SYSCALL_CHECK=y
|
||||
CONFIG_CRYPTO_CBC=y
|
||||
CONFIG_CRYPTO_ECB=y
|
||||
CONFIG_CRYPTO_PCBC=y
|
||||
CONFIG_CRYPTO_MD5=y
|
||||
CONFIG_CRYPTO_DES=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
# CONFIG_CRYPTO_HW is not set
|
||||
CONFIG_VIRTUALIZATION=y
|
||||
|
||||
@@ -18,6 +18,7 @@ CONFIG_MODULES=y
|
||||
CONFIG_MODULE_UNLOAD=y
|
||||
CONFIG_MODVERSIONS=y
|
||||
CONFIG_MODULE_SRCVERSION_ALL=y
|
||||
CONFIG_P5020_DS=y
|
||||
CONFIG_CPU_FREQ=y
|
||||
CONFIG_CPU_FREQ_GOV_POWERSAVE=y
|
||||
CONFIG_CPU_FREQ_GOV_USERSPACE=y
|
||||
@@ -256,7 +257,6 @@ CONFIG_HID_ZEROPLUS=y
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_DEVICEFS=y
|
||||
CONFIG_USB_EHCI_HCD=y
|
||||
CONFIG_USB_EHCI_TT_NEWSCHED=y
|
||||
# CONFIG_USB_EHCI_HCD_PPC_OF is not set
|
||||
CONFIG_USB_OHCI_HCD=y
|
||||
CONFIG_USB_STORAGE=m
|
||||
@@ -290,7 +290,6 @@ CONFIG_JFS_POSIX_ACL=y
|
||||
CONFIG_JFS_SECURITY=y
|
||||
CONFIG_XFS_FS=m
|
||||
CONFIG_XFS_POSIX_ACL=y
|
||||
CONFIG_INOTIFY=y
|
||||
CONFIG_AUTOFS4_FS=m
|
||||
CONFIG_ISO9660_FS=y
|
||||
CONFIG_UDF_FS=m
|
||||
@@ -384,7 +383,6 @@ CONFIG_CRYPTO_TGR192=m
|
||||
CONFIG_CRYPTO_WP512=m
|
||||
CONFIG_CRYPTO_AES=m
|
||||
CONFIG_CRYPTO_ANUBIS=m
|
||||
CONFIG_CRYPTO_ARC4=m
|
||||
CONFIG_CRYPTO_BLOWFISH=m
|
||||
CONFIG_CRYPTO_CAST6=m
|
||||
CONFIG_CRYPTO_KHAZAD=m
|
||||
|
||||
@@ -52,12 +52,22 @@ extern __wsum csum_partial(const void *buff, int len, __wsum sum);
|
||||
extern __wsum csum_partial_copy_generic(const void *src, void *dst,
|
||||
int len, __wsum sum,
|
||||
int *src_err, int *dst_err);
|
||||
|
||||
#ifdef __powerpc64__
|
||||
#define _HAVE_ARCH_COPY_AND_CSUM_FROM_USER
|
||||
extern __wsum csum_and_copy_from_user(const void __user *src, void *dst,
|
||||
int len, __wsum sum, int *err_ptr);
|
||||
#define HAVE_CSUM_COPY_USER
|
||||
extern __wsum csum_and_copy_to_user(const void *src, void __user *dst,
|
||||
int len, __wsum sum, int *err_ptr);
|
||||
#else
|
||||
/*
|
||||
* the same as csum_partial, but copies from src to dst while it
|
||||
* checksums.
|
||||
*/
|
||||
#define csum_partial_copy_from_user(src, dst, len, sum, errp) \
|
||||
csum_partial_copy_generic((__force const void *)(src), (dst), (len), (sum), (errp), NULL)
|
||||
#endif
|
||||
|
||||
#define csum_partial_copy_nocheck(src, dst, len, sum) \
|
||||
csum_partial_copy_generic((src), (dst), (len), (sum), NULL, NULL)
|
||||
|
||||
@@ -143,7 +143,7 @@ static inline void __user *arch_compat_alloc_user_space(long len)
|
||||
* We cant access below the stack pointer in the 32bit ABI and
|
||||
* can access 288 bytes in the 64bit ABI
|
||||
*/
|
||||
if (!(test_thread_flag(TIF_32BIT)))
|
||||
if (!is_32bit_task())
|
||||
usp -= 288;
|
||||
|
||||
return (void __user *) (usp - len);
|
||||
@@ -213,7 +213,7 @@ struct compat_shmid64_ds {
|
||||
|
||||
static inline int is_compat_task(void)
|
||||
{
|
||||
return test_thread_flag(TIF_32BIT);
|
||||
return is_32bit_task();
|
||||
}
|
||||
|
||||
#endif /* __KERNEL__ */
|
||||
|
||||
@@ -198,6 +198,7 @@ extern const char *powerpc_base_platform;
|
||||
#define CPU_FTR_CP_USE_DCBTZ LONG_ASM_CONST(0x0040000000000000)
|
||||
#define CPU_FTR_UNALIGNED_LD_STD LONG_ASM_CONST(0x0080000000000000)
|
||||
#define CPU_FTR_ASYM_SMT LONG_ASM_CONST(0x0100000000000000)
|
||||
#define CPU_FTR_STCX_CHECKS_ADDRESS LONG_ASM_CONST(0x0200000000000000)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
@@ -392,28 +393,31 @@ extern const char *powerpc_base_platform;
|
||||
CPU_FTR_MMCRA | CPU_FTR_CTRL)
|
||||
#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
||||
CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ)
|
||||
CPU_FTR_MMCRA | CPU_FTR_CP_USE_DCBTZ | \
|
||||
CPU_FTR_STCX_CHECKS_ADDRESS)
|
||||
#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
||||
CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA | \
|
||||
CPU_FTR_CP_USE_DCBTZ)
|
||||
CPU_FTR_CP_USE_DCBTZ | CPU_FTR_STCX_CHECKS_ADDRESS)
|
||||
#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
||||
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
||||
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
|
||||
CPU_FTR_PURR)
|
||||
CPU_FTR_PURR | CPU_FTR_STCX_CHECKS_ADDRESS)
|
||||
#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
||||
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
||||
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
|
||||
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
|
||||
CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD)
|
||||
CPU_FTR_DSCR | CPU_FTR_UNALIGNED_LD_STD | \
|
||||
CPU_FTR_STCX_CHECKS_ADDRESS)
|
||||
#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
||||
CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
||||
CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
|
||||
CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
|
||||
CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT)
|
||||
CPU_FTR_DSCR | CPU_FTR_SAO | CPU_FTR_ASYM_SMT | \
|
||||
CPU_FTR_STCX_CHECKS_ADDRESS)
|
||||
#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
|
||||
CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
|
||||
CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
|
||||
|
||||
@@ -127,19 +127,7 @@ static inline int dma_supported(struct device *dev, u64 mask)
|
||||
return dma_ops->dma_supported(dev, mask);
|
||||
}
|
||||
|
||||
static inline int dma_set_mask(struct device *dev, u64 dma_mask)
|
||||
{
|
||||
struct dma_map_ops *dma_ops = get_dma_ops(dev);
|
||||
|
||||
if (unlikely(dma_ops == NULL))
|
||||
return -EIO;
|
||||
if (dma_ops->set_dma_mask != NULL)
|
||||
return dma_ops->set_dma_mask(dev, dma_mask);
|
||||
if (!dev->dma_mask || !dma_supported(dev, dma_mask))
|
||||
return -EIO;
|
||||
*dev->dma_mask = dma_mask;
|
||||
return 0;
|
||||
}
|
||||
extern int dma_set_mask(struct device *dev, u64 dma_mask);
|
||||
|
||||
static inline void *dma_alloc_coherent(struct device *dev, size_t size,
|
||||
dma_addr_t *dma_handle, gfp_t flag)
|
||||
|
||||
@@ -250,7 +250,7 @@ do { \
|
||||
* the 64bit ABI has never had these issues dont enable the workaround
|
||||
* even if we have an executable stack.
|
||||
*/
|
||||
# define elf_read_implies_exec(ex, exec_stk) (test_thread_flag(TIF_32BIT) ? \
|
||||
# define elf_read_implies_exec(ex, exec_stk) (is_32bit_task() ? \
|
||||
(exec_stk == EXSTACK_DEFAULT) : 0)
|
||||
#else
|
||||
# define SET_PERSONALITY(ex) \
|
||||
|
||||
@@ -137,7 +137,8 @@
|
||||
li r10,0; \
|
||||
ld r11,exception_marker@toc(r2); \
|
||||
std r10,RESULT(r1); /* clear regs->result */ \
|
||||
std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */
|
||||
std r11,STACK_FRAME_OVERHEAD-16(r1); /* mark the frame */ \
|
||||
ACCOUNT_STOLEN_TIME
|
||||
|
||||
/*
|
||||
* Exception vectors.
|
||||
|
||||
@@ -0,0 +1,48 @@
|
||||
/*
|
||||
* Copyright 2009 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Cache SRAM handling for QorIQ platform
|
||||
*
|
||||
* Author: Vivek Mahajan <vivek.mahajan@freescale.com>
|
||||
|
||||
* This file is derived from the original work done
|
||||
* by Sylvain Munaut for the Bestcomm SRAM allocator.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
|
||||
*/
|
||||
|
||||
#ifndef __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
|
||||
#define __ASM_POWERPC_FSL_85XX_CACHE_SRAM_H__
|
||||
|
||||
#include <asm/rheap.h>
|
||||
#include <linux/spinlock.h>
|
||||
|
||||
/*
|
||||
* Cache-SRAM
|
||||
*/
|
||||
|
||||
struct mpc85xx_cache_sram {
|
||||
phys_addr_t base_phys;
|
||||
void *base_virt;
|
||||
unsigned int size;
|
||||
rh_info_t *rh;
|
||||
spinlock_t lock;
|
||||
};
|
||||
|
||||
extern void mpc85xx_cache_sram_free(void *ptr);
|
||||
extern void *mpc85xx_cache_sram_alloc(unsigned int size,
|
||||
phys_addr_t *phys, unsigned int align);
|
||||
|
||||
#endif /* __AMS_POWERPC_FSL_85XX_CACHE_SRAM_H__ */
|
||||
@@ -91,6 +91,7 @@ extern void machine_kexec_simple(struct kimage *image);
|
||||
extern void crash_kexec_secondary(struct pt_regs *regs);
|
||||
extern int overlaps_crashkernel(unsigned long start, unsigned long size);
|
||||
extern void reserve_crashkernel(void);
|
||||
extern void machine_kexec_mask_interrupts(void);
|
||||
|
||||
#else /* !CONFIG_KEXEC */
|
||||
static inline int kexec_sr_activated(int cpu) { return 0; }
|
||||
|
||||
@@ -82,7 +82,7 @@ FPD_THREE_IN(fmadd)
|
||||
FPD_THREE_IN(fnmsub)
|
||||
FPD_THREE_IN(fnmadd)
|
||||
|
||||
extern void kvm_cvt_fd(u32 *from, u64 *to, u64 *fpscr);
|
||||
extern void kvm_cvt_df(u64 *from, u32 *to, u64 *fpscr);
|
||||
extern void kvm_cvt_fd(u32 *from, u64 *to);
|
||||
extern void kvm_cvt_df(u64 *from, u32 *to);
|
||||
|
||||
#endif
|
||||
|
||||
@@ -153,6 +153,8 @@ struct lppaca {
|
||||
|
||||
extern struct lppaca lppaca[];
|
||||
|
||||
#define lppaca_of(cpu) (*paca[cpu].lppaca_ptr)
|
||||
|
||||
/*
|
||||
* SLB shadow buffer structure as defined in the PAPR. The save_area
|
||||
* contains adjacent ESID and VSID pairs for each shadowed SLB. The
|
||||
@@ -170,6 +172,33 @@ struct slb_shadow {
|
||||
|
||||
extern struct slb_shadow slb_shadow[];
|
||||
|
||||
/*
|
||||
* Layout of entries in the hypervisor's dispatch trace log buffer.
|
||||
*/
|
||||
struct dtl_entry {
|
||||
u8 dispatch_reason;
|
||||
u8 preempt_reason;
|
||||
u16 processor_id;
|
||||
u32 enqueue_to_dispatch_time;
|
||||
u32 ready_to_enqueue_time;
|
||||
u32 waiting_to_ready_time;
|
||||
u64 timebase;
|
||||
u64 fault_addr;
|
||||
u64 srr0;
|
||||
u64 srr1;
|
||||
};
|
||||
|
||||
#define DISPATCH_LOG_BYTES 4096 /* bytes per cpu */
|
||||
#define N_DISPATCH_LOG (DISPATCH_LOG_BYTES / sizeof(struct dtl_entry))
|
||||
|
||||
/*
|
||||
* When CONFIG_VIRT_CPU_ACCOUNTING = y, the cpu accounting code controls
|
||||
* reading from the dispatch trace log. If other code wants to consume
|
||||
* DTL entries, it can set this pointer to a function that will get
|
||||
* called once for each DTL entry that gets processed.
|
||||
*/
|
||||
extern void (*dtl_consumer)(struct dtl_entry *entry, u64 index);
|
||||
|
||||
#endif /* CONFIG_PPC_BOOK3S */
|
||||
#endif /* __KERNEL__ */
|
||||
#endif /* _ASM_POWERPC_LPPACA_H */
|
||||
|
||||
@@ -102,6 +102,9 @@ struct machdep_calls {
|
||||
void (*pci_dma_dev_setup)(struct pci_dev *dev);
|
||||
void (*pci_dma_bus_setup)(struct pci_bus *bus);
|
||||
|
||||
/* Platform set_dma_mask override */
|
||||
int (*dma_set_mask)(struct device *dev, u64 dma_mask);
|
||||
|
||||
int (*probe)(void);
|
||||
void (*setup_arch)(void); /* Optional, may be NULL */
|
||||
void (*init_early)(void);
|
||||
|
||||
@@ -114,6 +114,17 @@
|
||||
|
||||
#define MAS7_RPN 0xFFFFFFFF
|
||||
|
||||
/* Bit definitions for MMUCFG */
|
||||
#define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
|
||||
#define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
|
||||
#define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
|
||||
#define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
|
||||
#define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
|
||||
#define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
|
||||
#define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
|
||||
#define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
|
||||
#define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
|
||||
|
||||
/* Bit definitions for MMUCSR0 */
|
||||
#define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
|
||||
#define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
|
||||
@@ -133,6 +144,10 @@
|
||||
#define TLBnCFG_GTWE 0x00010000 /* Guest can write */
|
||||
#define TLBnCFG_IND 0x00020000 /* IND entries supported */
|
||||
#define TLBnCFG_PT 0x00040000 /* Can load from page table */
|
||||
#define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
|
||||
#define TLBnCFG_MINSIZE_SHIFT 20
|
||||
#define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
|
||||
#define TLBnCFG_MAXSIZE_SHIFT 16
|
||||
#define TLBnCFG_ASSOC 0xff000000 /* Associativity */
|
||||
|
||||
/* TLBnPS encoding */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user