mirror of
https://github.com/linux-msm/laptops-kernel.git
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Merge branch 'next' of https://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc.git
This commit is contained in:
Mark Brown
@@ -145,6 +145,11 @@ properties:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: platform specific settings for DLL_CONFIG reg.
|
||||
|
||||
qcom,ice:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
phandle to the Inline Crypto Engine (ICE) hardware block for this controller.
|
||||
|
||||
iommus:
|
||||
minItems: 1
|
||||
maxItems: 8
|
||||
@@ -198,35 +203,69 @@ allOf:
|
||||
enum:
|
||||
- qcom,sdhci-msm-v4
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: Host controller register map
|
||||
- description: SD Core register map
|
||||
- description: CQE register map
|
||||
- description: Inline Crypto Engine register map
|
||||
reg-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: hc
|
||||
- const: core
|
||||
- const: cqhci
|
||||
- const: ice
|
||||
if:
|
||||
required:
|
||||
- qcom,ice
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: Host controller register map
|
||||
- description: SD Core register map
|
||||
- description: CQE register map
|
||||
reg-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: hc
|
||||
- const: core
|
||||
- const: cqhci
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
items:
|
||||
- description: Host controller register map
|
||||
- description: SD Core register map
|
||||
- description: CQE register map
|
||||
- description: Inline Crypto Engine register map
|
||||
reg-names:
|
||||
minItems: 2
|
||||
items:
|
||||
- const: hc
|
||||
- const: core
|
||||
- const: cqhci
|
||||
- const: ice
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Host controller register map
|
||||
- description: CQE register map
|
||||
- description: Inline Crypto Engine register map
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: hc
|
||||
- const: cqhci
|
||||
- const: ice
|
||||
if:
|
||||
required:
|
||||
- qcom,ice
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Host controller register map
|
||||
- description: CQE register map
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: hc
|
||||
- const: cqhci
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Host controller register map
|
||||
- description: CQE register map
|
||||
- description: Inline Crypto Engine register map
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: hc
|
||||
- const: cqhci
|
||||
- const: ice
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
|
||||
@@ -43,6 +43,7 @@ properties:
|
||||
- rockchip,rk3562-dw-mshc
|
||||
- rockchip,rk3568-dw-mshc
|
||||
- rockchip,rk3588-dw-mshc
|
||||
- rockchip,rv1106-dw-mshc
|
||||
- rockchip,rv1108-dw-mshc
|
||||
- rockchip,rv1126-dw-mshc
|
||||
- const: rockchip,rk3288-dw-mshc
|
||||
|
||||
@@ -1,110 +0,0 @@
|
||||
* STMicroelectronics sdhci-st MMC/SD controller
|
||||
|
||||
This file documents the differences between the core properties in
|
||||
Documentation/devicetree/bindings/mmc/mmc.txt and the properties
|
||||
used by the sdhci-st driver.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
|
||||
to set the internal glue logic used for configuring the MMC
|
||||
subsystem (mmcss) inside the FlashSS (available in STiH407 SoC
|
||||
family).
|
||||
|
||||
- clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
|
||||
See: Documentation/devicetree/bindings/resource-names.txt
|
||||
- clocks: Phandle to the clock.
|
||||
See: Documentation/devicetree/bindings/clock/clock-bindings.txt
|
||||
|
||||
- interrupts: One mmc interrupt should be described here.
|
||||
- interrupt-names: Should be "mmcirq".
|
||||
|
||||
- pinctrl-names: A pinctrl state names "default" must be defined.
|
||||
- pinctrl-0: Phandle referencing pin configuration of the sd/emmc controller.
|
||||
See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
|
||||
|
||||
- reg: This must provide the host controller base address and it can also
|
||||
contain the FlashSS Top register for TX/RX delay used by the driver
|
||||
to configure DLL inside the flashSS, if so reg-names must also be
|
||||
specified.
|
||||
|
||||
Optional properties:
|
||||
- reg-names: Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional
|
||||
for eMMC on stih407 family silicon to configure DLL inside FlashSS.
|
||||
|
||||
- non-removable: Non-removable slot. Also used for configuring mmcss in STiH407 SoC
|
||||
family.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- bus-width: Number of data lines.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for
|
||||
configuring the CCONFIG3 in the mmcss.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- resets: Phandle and reset specifier pair to softreset line of HC IP.
|
||||
See: Documentation/devicetree/bindings/reset/reset.txt
|
||||
|
||||
- vqmmc-supply: Phandle to the regulator dt node, mentioned as the vcc/vdd
|
||||
supply in eMMC/SD specs.
|
||||
|
||||
- sd-uhs-sdr50: To enable the SDR50 in the mmcss.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- sd-uhs-sdr104: To enable the SDR104 in the mmcss.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
- sd-uhs-ddr50: To enable the DDR50 in the mmcss.
|
||||
See: Documentation/devicetree/bindings/mmc/mmc.txt.
|
||||
|
||||
Example:
|
||||
|
||||
/* Example stih416e eMMC configuration */
|
||||
|
||||
mmc0: sdhci@fe81e000 {
|
||||
compatible = "st,sdhci";
|
||||
reg = <0xfe81e000 0x1000>;
|
||||
interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "mmcirq";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc0>;
|
||||
clock-names = "mmc";
|
||||
clocks = <&clk_s_a1_ls 1>;
|
||||
bus-width = <8>
|
||||
|
||||
/* Example SD stih407 family configuration */
|
||||
|
||||
mmc1: sdhci@9080000 {
|
||||
compatible = "st,sdhci-stih407", "st,sdhci";
|
||||
reg = <0x09080000 0x7ff>;
|
||||
reg-names = "mmc";
|
||||
interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "mmcirq";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_sd1>;
|
||||
clock-names = "mmc";
|
||||
clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
|
||||
resets = <&softreset STIH407_MMC1_SOFTRESET>;
|
||||
bus-width = <4>;
|
||||
};
|
||||
|
||||
/* Example eMMC stih407 family configuration */
|
||||
|
||||
mmc0: sdhci@9060000 {
|
||||
compatible = "st,sdhci-stih407", "st,sdhci";
|
||||
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
|
||||
reg-names = "mmc", "top-mmc-delay";
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
|
||||
interrupt-names = "mmcirq";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc0>;
|
||||
clock-names = "mmc";
|
||||
clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
|
||||
vqmmc-supply = <&vmmc_reg>;
|
||||
max-frequency = <200000000>;
|
||||
bus-width = <8>;
|
||||
non-removable;
|
||||
sd-uhs-sdr50;
|
||||
sd-uhs-sdr104;
|
||||
sd-uhs-ddr50;
|
||||
};
|
||||
@@ -0,0 +1,105 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/st,sdhci.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: STMicroelectronics SDHCI-ST MMC/SD Controller
|
||||
|
||||
maintainers:
|
||||
- Peter Griffin <peter.griffin@linaro.org>
|
||||
|
||||
description:
|
||||
The STMicroelectronics SDHCI-ST MMC/SD host controller is compliant with
|
||||
the SD Host Controller Interface (SDHCI) specification and is used to
|
||||
interface with MMC, SD and SDIO cards. The ST SDHCI controller extends the
|
||||
standard SDHCI capabilities with platform-specific configurations such as
|
||||
additional register regions, clock inputs, and delay control mechanisms
|
||||
required for signal timing adjustments to support high-speed modes across
|
||||
different ST SoCs.
|
||||
|
||||
allOf:
|
||||
- $ref: mmc-controller.yaml#
|
||||
- if:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
required:
|
||||
- reg
|
||||
then:
|
||||
required:
|
||||
- reg-names
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
- const: st,sdhci
|
||||
- items:
|
||||
- const: st,sdhci-stih407
|
||||
- const: st,sdhci
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: MMC controller base registers
|
||||
- description: FlashSS Top registers for TX/RX DLL delay configuration
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mmc
|
||||
- const: top-mmc-delay
|
||||
|
||||
clocks:
|
||||
minItems: 1
|
||||
items:
|
||||
- description: Clock for the MMC controller
|
||||
- description: Interconnect (ICN) clock
|
||||
|
||||
clock-names:
|
||||
minItems: 1
|
||||
items:
|
||||
- const: mmc
|
||||
- const: icn
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-names:
|
||||
const: mmcirq
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
max-frequency:
|
||||
enum: [200000000, 100000000, 50000000]
|
||||
default: 50000000
|
||||
|
||||
required:
|
||||
- reg
|
||||
- compatible
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
- interrupt-names
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
#include <dt-bindings/clock/stih407-clks.h>
|
||||
mmc@9060000 {
|
||||
compatible = "st,sdhci-stih407", "st,sdhci";
|
||||
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
|
||||
reg-names = "mmc", "top-mmc-delay";
|
||||
interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>;
|
||||
interrupt-names = "mmcirq";
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pinctrl_mmc0>;
|
||||
clock-names = "mmc", "icn";
|
||||
clocks = <&clk_s_c0_flexgen CLK_MMC_0>,
|
||||
<&clk_s_c0_flexgen CLK_RX_ICN_HVA>;
|
||||
bus-width = <8>;
|
||||
};
|
||||
...
|
||||
@@ -0,0 +1,60 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/mmc/ti,omap2420-mmc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Texas Instruments MMC host controller for OMAP1 and 2420
|
||||
|
||||
maintainers:
|
||||
- Eduard Bostina <egbostina@gmail.com>
|
||||
|
||||
description: |
|
||||
The MMC Host Controller on TI OMAP1 and 2420 family provides
|
||||
an interface for MMC, SD, and SDIO types of memory cards.
|
||||
|
||||
allOf:
|
||||
- $ref: /schemas/mmc/mmc-controller.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: ti,omap2420-mmc
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
ti,hwmods:
|
||||
description: |
|
||||
Name of the hwmod associated to the MMC controller. Must be
|
||||
"msdi<n>" where n is the controller instance starting from 1.
|
||||
$ref: /schemas/types.yaml#/definitions/string
|
||||
pattern: "^msdi([1-9]|[1-9][0-9]+)$"
|
||||
|
||||
dmas:
|
||||
maxItems: 2
|
||||
|
||||
dma-names:
|
||||
items:
|
||||
- const: tx
|
||||
- const: rx
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupts
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
mmc@4809c000 {
|
||||
compatible = "ti,omap2420-mmc";
|
||||
ti,hwmods = "msdi1";
|
||||
reg = <0x4809c000 0x80>;
|
||||
interrupts = <83>;
|
||||
dmas = <&sdma 61 &sdma 62>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
@@ -1,26 +0,0 @@
|
||||
* TI MMC host controller for OMAP1 and 2420
|
||||
|
||||
The MMC Host Controller on TI OMAP1 and 2420 family provides
|
||||
an interface for MMC, SD, and SDIO types of memory cards.
|
||||
|
||||
This file documents differences between the core properties described
|
||||
by mmc.txt and the properties used by the omap mmc driver.
|
||||
|
||||
Note that this driver will not work with omap2430 or later omaps,
|
||||
please see the omap hsmmc driver for the current omaps.
|
||||
|
||||
Required properties:
|
||||
- compatible: Must be "ti,omap2420-mmc", for OMAP2420 controllers
|
||||
- ti,hwmods: For 2420, must be "msdi<n>", where n is controller
|
||||
instance starting 1
|
||||
|
||||
Examples:
|
||||
|
||||
msdi1: mmc@4809c000 {
|
||||
compatible = "ti,omap2420-mmc";
|
||||
ti,hwmods = "msdi1";
|
||||
reg = <0x4809c000 0x80>;
|
||||
interrupts = <83>;
|
||||
dmas = <&sdma 61 &sdma 62>;
|
||||
dma-names = "tx", "rx";
|
||||
};
|
||||
@@ -27067,6 +27067,13 @@ Q: http://patchwork.linuxtv.org/project/linux-media/list/
|
||||
T: git git://linuxtv.org/mhadli/v4l-dvb-davinci_devices.git
|
||||
F: drivers/media/platform/ti/am437x/
|
||||
|
||||
TI AM654 SDHCI DRIVER
|
||||
M: Judith Mendez <jm@ti.com>
|
||||
L: linux-mmc@vger.kernel.org
|
||||
S: Supported
|
||||
F: Documentation/devicetree/bindings/mmc/sdhci-am654.yaml
|
||||
F: drivers/mmc/host/sdhci_am654.c
|
||||
|
||||
TI BANDGAP AND THERMAL DRIVER
|
||||
M: Eduardo Valentin <edubezval@gmail.com>
|
||||
M: Keerthy <j-keerthy@ti.com>
|
||||
|
||||
@@ -596,7 +596,7 @@
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmc0: sdhci@9060000 {
|
||||
mmc0: mmc@9060000 {
|
||||
compatible = "st,sdhci-stih407", "st,sdhci";
|
||||
status = "disabled";
|
||||
reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
|
||||
@@ -611,7 +611,7 @@
|
||||
bus-width = <8>;
|
||||
};
|
||||
|
||||
mmc1: sdhci@9080000 {
|
||||
mmc1: mmc@9080000 {
|
||||
compatible = "st,sdhci-stih407", "st,sdhci";
|
||||
status = "disabled";
|
||||
reg = <0x09080000 0x7ff>;
|
||||
|
||||
@@ -141,14 +141,14 @@
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: sdhci@9060000 {
|
||||
mmc0: mmc@9060000 {
|
||||
pinctrl-0 = <&pinctrl_sd0>;
|
||||
bus-width = <4>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
/* high speed expansion connector */
|
||||
mmc1: sdhci@9080000 {
|
||||
mmc1: mmc@9080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
|
||||
@@ -82,11 +82,11 @@
|
||||
st,i2c-min-sda-pulse-width-us = <5>;
|
||||
};
|
||||
|
||||
mmc1: sdhci@9080000 {
|
||||
mmc1: mmc@9080000 {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
mmc0: sdhci@9060000 {
|
||||
mmc0: mmc@9060000 {
|
||||
status = "okay";
|
||||
max-frequency = <200000000>;
|
||||
sd-uhs-sdr50;
|
||||
|
||||
@@ -136,7 +136,7 @@
|
||||
phy-names = "usb";
|
||||
};
|
||||
|
||||
mmc0: sdhci@9060000 {
|
||||
mmc0: mmc@9060000 {
|
||||
assigned-clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
|
||||
assigned-clock-parents = <&clk_s_c0_pll1 0>;
|
||||
assigned-clock-rates = <200000000>;
|
||||
|
||||
@@ -312,6 +312,9 @@ int rtsx_usb_get_card_status(struct rtsx_ucr *ucr, u16 *status)
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
|
||||
ucr->card_status_cache = *status;
|
||||
ucr->card_status_valid = true;
|
||||
|
||||
return 0;
|
||||
}
|
||||
EXPORT_SYMBOL_GPL(rtsx_usb_get_card_status);
|
||||
@@ -623,6 +626,7 @@ static int rtsx_usb_probe(struct usb_interface *intf,
|
||||
{
|
||||
struct usb_device *usb_dev = interface_to_usbdev(intf);
|
||||
struct rtsx_ucr *ucr;
|
||||
u16 status;
|
||||
int ret;
|
||||
|
||||
dev_dbg(&intf->dev,
|
||||
@@ -659,6 +663,9 @@ static int rtsx_usb_probe(struct usb_interface *intf,
|
||||
if (ret)
|
||||
goto out_init_fail;
|
||||
|
||||
/* Prime cached status for runtime autosuspend decisions. */
|
||||
rtsx_usb_get_card_status(ucr, &status);
|
||||
|
||||
/* initialize USB SG transfer timer */
|
||||
timer_setup(&ucr->sg_timer, rtsx_usb_sg_timed_out, 0);
|
||||
|
||||
@@ -713,22 +720,29 @@ static int rtsx_usb_suspend(struct usb_interface *intf, pm_message_t message)
|
||||
struct rtsx_ucr *ucr =
|
||||
(struct rtsx_ucr *)usb_get_intfdata(intf);
|
||||
u16 val = 0;
|
||||
bool valid = false;
|
||||
|
||||
dev_dbg(&intf->dev, "%s called with pm message 0x%04x\n",
|
||||
__func__, message.event);
|
||||
|
||||
if (PMSG_IS_AUTO(message)) {
|
||||
if (mutex_trylock(&ucr->dev_mutex)) {
|
||||
rtsx_usb_get_card_status(ucr, &val);
|
||||
valid = ucr->card_status_valid;
|
||||
if (valid)
|
||||
val = ucr->card_status_cache;
|
||||
mutex_unlock(&ucr->dev_mutex);
|
||||
|
||||
/* Defer the autosuspend if card exists */
|
||||
if (val & (SD_CD | MS_CD)) {
|
||||
/*
|
||||
* Do not issue USB commands from runtime autosuspend.
|
||||
* Raw SD_CD is not authoritative on tray-based readers,
|
||||
* while a real SD card is protected by the SD/MMC child
|
||||
* runtime-PM reference once the card is powered. Keep
|
||||
* the historical Memory Stick autosuspend deferral when
|
||||
* the cached status says MS media is present.
|
||||
*/
|
||||
if (valid && (val & MS_CD)) {
|
||||
device_for_each_child(&intf->dev, NULL, rtsx_usb_resume_child);
|
||||
return -EAGAIN;
|
||||
} else {
|
||||
/* if the card does not exists, clear OCP status */
|
||||
rtsx_usb_write_register(ucr, OCPCTL, MS_OCP_CLEAR, MS_OCP_CLEAR);
|
||||
}
|
||||
} else {
|
||||
/* There is an ongoing operation*/
|
||||
|
||||
@@ -3337,6 +3337,11 @@ static int __init mmc_blk_init(void)
|
||||
{
|
||||
int res;
|
||||
|
||||
if (perdev_minors <= 0) {
|
||||
pr_err("mmcblk: invalid minors per device: %d\n", perdev_minors);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
res = bus_register(&mmc_rpmb_bus_type);
|
||||
if (res < 0) {
|
||||
pr_err("mmcblk: could not register RPMB bus type\n");
|
||||
|
||||
@@ -1379,15 +1379,10 @@ out:
|
||||
|
||||
static int sd_enable_cache(struct mmc_card *card)
|
||||
{
|
||||
u8 *reg_buf;
|
||||
int err;
|
||||
|
||||
card->ext_perf.feature_enabled &= ~SD_EXT_PERF_CACHE;
|
||||
|
||||
reg_buf = kzalloc(512, GFP_KERNEL);
|
||||
if (!reg_buf)
|
||||
return -ENOMEM;
|
||||
|
||||
/*
|
||||
* Set Cache Enable at bit 0 in the performance enhancement register at
|
||||
* 260 bytes offset.
|
||||
@@ -1397,7 +1392,7 @@ static int sd_enable_cache(struct mmc_card *card)
|
||||
if (err) {
|
||||
pr_warn("%s: error %d writing Cache Enable bit\n",
|
||||
mmc_hostname(card->host), err);
|
||||
goto out;
|
||||
return err;
|
||||
}
|
||||
|
||||
err = mmc_poll_for_busy(card, SD_WRITE_EXTR_SINGLE_TIMEOUT_MS, false,
|
||||
@@ -1405,8 +1400,6 @@ static int sd_enable_cache(struct mmc_card *card)
|
||||
if (!err)
|
||||
card->ext_perf.feature_enabled |= SD_EXT_PERF_CACHE;
|
||||
|
||||
out:
|
||||
kfree(reg_buf);
|
||||
return err;
|
||||
}
|
||||
|
||||
|
||||
@@ -1103,8 +1103,7 @@ static int alcor_pci_sdmmc_drv_probe(struct platform_device *pdev)
|
||||
alcor_irq, alcor_irq_thread, IRQF_SHARED,
|
||||
DRV_NAME_ALCOR_PCI_SDMMC, host);
|
||||
if (ret)
|
||||
return dev_err_probe(&pdev->dev, ret,
|
||||
"Failed to get irq for data line\n");
|
||||
return ret;
|
||||
|
||||
mutex_init(&host->cmd_mutex);
|
||||
INIT_DELAYED_WORK(&host->timeout_work, alcor_timeout_timer);
|
||||
|
||||
+19
-18
@@ -188,7 +188,7 @@ struct bcm2835_host {
|
||||
u32 drain_words;
|
||||
struct page *drain_page;
|
||||
u32 drain_offset;
|
||||
bool use_dma;
|
||||
struct device *dma_dev;
|
||||
};
|
||||
|
||||
static void bcm2835_dumpcmd(struct bcm2835_host *host, struct mmc_command *cmd,
|
||||
@@ -494,8 +494,7 @@ void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data)
|
||||
&host->dma_cfg_rx :
|
||||
&host->dma_cfg_tx);
|
||||
|
||||
sg_len = dma_map_sg(dma_chan->device->dev, data->sg, data->sg_len,
|
||||
dir_data);
|
||||
sg_len = dma_map_sg(host->dma_dev, data->sg, data->sg_len, dir_data);
|
||||
if (!sg_len)
|
||||
return;
|
||||
|
||||
@@ -503,8 +502,7 @@ void bcm2835_prepare_dma(struct bcm2835_host *host, struct mmc_data *data)
|
||||
DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
|
||||
|
||||
if (!desc) {
|
||||
dma_unmap_sg(dma_chan->device->dev, data->sg, data->sg_len,
|
||||
dir_data);
|
||||
dma_unmap_sg(host->dma_dev, data->sg, data->sg_len, dir_data);
|
||||
return;
|
||||
}
|
||||
|
||||
@@ -1057,7 +1055,7 @@ static void bcm2835_dma_complete_work(struct work_struct *work)
|
||||
data = host->data;
|
||||
|
||||
if (host->dma_chan) {
|
||||
dma_unmap_sg(host->dma_chan->device->dev,
|
||||
dma_unmap_sg(host->dma_dev,
|
||||
data->sg, data->sg_len,
|
||||
host->dma_dir);
|
||||
|
||||
@@ -1201,7 +1199,7 @@ static void bcm2835_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
||||
return;
|
||||
}
|
||||
|
||||
if (host->use_dma && mrq->data && (mrq->data->blocks > PIO_THRESHOLD))
|
||||
if (host->dma_dev && mrq->data && (mrq->data->blocks > PIO_THRESHOLD))
|
||||
bcm2835_prepare_dma(host, mrq->data);
|
||||
|
||||
host->use_sbc = !!mrq->sbc && host->mrq->data &&
|
||||
@@ -1281,10 +1279,7 @@ static int bcm2835_add_host(struct bcm2835_host *host)
|
||||
|
||||
if (!host->dma_chan_rxtx) {
|
||||
dev_warn(dev, "unable to initialise DMA channel. Falling back to PIO\n");
|
||||
host->use_dma = false;
|
||||
} else {
|
||||
host->use_dma = true;
|
||||
|
||||
host->dma_cfg_tx.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
host->dma_cfg_tx.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
|
||||
host->dma_cfg_tx.direction = DMA_MEM_TO_DEV;
|
||||
@@ -1297,15 +1292,21 @@ static int bcm2835_add_host(struct bcm2835_host *host)
|
||||
host->dma_cfg_rx.src_addr = host->phys_addr + SDDATA;
|
||||
host->dma_cfg_rx.dst_addr = 0;
|
||||
|
||||
if (dmaengine_slave_config(host->dma_chan_rxtx,
|
||||
&host->dma_cfg_tx) != 0 ||
|
||||
dmaengine_slave_config(host->dma_chan_rxtx,
|
||||
&host->dma_cfg_rx) != 0)
|
||||
host->use_dma = false;
|
||||
if (!dmaengine_slave_config(host->dma_chan_rxtx,
|
||||
&host->dma_cfg_tx) &&
|
||||
!dmaengine_slave_config(host->dma_chan_rxtx,
|
||||
&host->dma_cfg_rx)) {
|
||||
host->dma_dev =
|
||||
dmaengine_get_dma_device(host->dma_chan_rxtx);
|
||||
}
|
||||
}
|
||||
|
||||
mmc->max_segs = 128;
|
||||
mmc->max_req_size = min_t(size_t, 524288, dma_max_mapping_size(dev));
|
||||
mmc->max_req_size = 524288;
|
||||
if (host->dma_dev) {
|
||||
mmc->max_req_size = min_t(size_t, mmc->max_req_size,
|
||||
dma_max_mapping_size(host->dma_dev));
|
||||
}
|
||||
mmc->max_seg_size = mmc->max_req_size;
|
||||
mmc->max_blk_size = 1024;
|
||||
mmc->max_blk_count = 65535;
|
||||
@@ -1336,10 +1337,10 @@ static int bcm2835_add_host(struct bcm2835_host *host)
|
||||
}
|
||||
|
||||
pio_limit_string[0] = '\0';
|
||||
if (host->use_dma && (PIO_THRESHOLD > 0))
|
||||
if (host->dma_dev && (PIO_THRESHOLD > 0))
|
||||
sprintf(pio_limit_string, " (>%d)", PIO_THRESHOLD);
|
||||
dev_info(dev, "loaded - DMA %s%s\n",
|
||||
host->use_dma ? "enabled" : "disabled", pio_limit_string);
|
||||
host->dma_dev ? "enabled" : "disabled", pio_limit_string);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@@ -240,21 +240,15 @@ static int octeon_mmc_probe(struct platform_device *pdev)
|
||||
ret = devm_request_irq(&pdev->dev, mmc_irq[i],
|
||||
cvm_mmc_interrupt,
|
||||
0, cvm_mmc_irq_names[i], host);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Error: devm_request_irq %d\n",
|
||||
mmc_irq[i]);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
} else {
|
||||
ret = devm_request_irq(&pdev->dev, mmc_irq[0],
|
||||
cvm_mmc_interrupt, 0, KBUILD_MODNAME,
|
||||
host);
|
||||
if (ret < 0) {
|
||||
dev_err(&pdev->dev, "Error: devm_request_irq %d\n",
|
||||
mmc_irq[0]);
|
||||
if (ret < 0)
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
host->global_pwr_gpiod = devm_gpiod_get_optional(&pdev->dev,
|
||||
|
||||
@@ -484,11 +484,11 @@ void cqhci_set_tran_desc(u8 *desc, dma_addr_t addr, int len, bool end,
|
||||
{
|
||||
__le32 *attr = (__le32 __force *)desc;
|
||||
|
||||
*attr = (CQHCI_VALID(1) |
|
||||
CQHCI_END(end ? 1 : 0) |
|
||||
CQHCI_INT(0) |
|
||||
CQHCI_ACT(0x4) |
|
||||
CQHCI_DAT_LENGTH(len));
|
||||
*attr = cpu_to_le32((CQHCI_VALID(1) |
|
||||
CQHCI_END(end ? 1 : 0) |
|
||||
CQHCI_INT(0) |
|
||||
CQHCI_ACT(0x4) |
|
||||
CQHCI_DAT_LENGTH(len)));
|
||||
|
||||
if (dma64) {
|
||||
__le64 *dataddr = (__le64 __force *)(desc + 4);
|
||||
@@ -542,7 +542,7 @@ static int cqhci_prep_tran_desc(struct mmc_request *mrq,
|
||||
static void cqhci_prep_dcmd_desc(struct mmc_host *mmc,
|
||||
struct mmc_request *mrq)
|
||||
{
|
||||
u64 *task_desc = NULL;
|
||||
__le64 *task_desc = NULL;
|
||||
u64 data = 0;
|
||||
u8 resp_type;
|
||||
u8 *desc;
|
||||
@@ -574,7 +574,7 @@ static void cqhci_prep_dcmd_desc(struct mmc_host *mmc,
|
||||
CQHCI_CMD_TIMING(timing) | CQHCI_RESP_TYPE(resp_type));
|
||||
if (cq_host->ops->update_dcmd_desc)
|
||||
cq_host->ops->update_dcmd_desc(mmc, mrq, &data);
|
||||
*task_desc |= data;
|
||||
*task_desc |= cpu_to_le64(data);
|
||||
desc = (u8 *)task_desc;
|
||||
pr_debug("%s: cqhci: dcmd: cmd: %d timing: %d resp: %d\n",
|
||||
mmc_hostname(mmc), mrq->cmd->opcode, timing, resp_type);
|
||||
@@ -819,8 +819,7 @@ static void cqhci_finish_mrq(struct mmc_host *mmc, unsigned int tag)
|
||||
mmc_cqe_request_done(mmc, mrq);
|
||||
}
|
||||
|
||||
irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
|
||||
int data_error)
|
||||
irqreturn_t cqhci_irq(struct mmc_host *mmc, int cmd_error, int data_error)
|
||||
{
|
||||
u32 status;
|
||||
unsigned long tag = 0, comp_status;
|
||||
|
||||
@@ -315,8 +315,7 @@ static inline u32 cqhci_readl(struct cqhci_host *host, int reg)
|
||||
|
||||
struct platform_device;
|
||||
|
||||
irqreturn_t cqhci_irq(struct mmc_host *mmc, u32 intmask, int cmd_error,
|
||||
int data_error);
|
||||
irqreturn_t cqhci_irq(struct mmc_host *mmc, int cmd_error, int data_error);
|
||||
int cqhci_init(struct cqhci_host *cq_host, struct mmc_host *mmc, bool dma64);
|
||||
struct cqhci_host *cqhci_pltfm_init(struct platform_device *pdev);
|
||||
int cqhci_deactivate(struct mmc_host *mmc);
|
||||
|
||||
@@ -11,6 +11,5 @@
|
||||
extern int dw_mci_pltfm_register(struct platform_device *pdev,
|
||||
const struct dw_mci_drv_data *drv_data);
|
||||
extern void dw_mci_pltfm_remove(struct platform_device *pdev);
|
||||
extern const struct dev_pm_ops dw_mci_pmops;
|
||||
|
||||
#endif /* _DW_MMC_PLTFM_H_ */
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user