mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'mips_6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer: - add support for Realtek RTL9302C - add support for Mobileye EyeQ6H - add support for Mobileye EyeQ OLB system controller - improve r4k clocksource - add mode for emulating ieee754 NAN2008 - rework for BMIPS CBR address handling - fixes for Loongson 2K1000 - defconfig updates - cleanups and fixes * tag 'mips_6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (58 commits) MIPS: config: Add ip30_defconfig MIPS: config: lemote2f: Regenerate defconfig MIPS: config: generic: Add board-litex MIPS: config: Enable MSA and virtualization for MIPS64R6 MIPS: Fix fallback march for SB1 mips: dts: realtek: Add RTL9302C board mips: generic: add fdt fixup for Realtek reference board mips: select REALTEK_OTTO_TIMER for Realtek platforms dt-bindings: interrupt-controller: realtek,rtl-intc: Add rtl9300-intc dt-bindings: mips: realtek: Add rtl930x-soc compatible dt-bindings: vendor-prefixes: Add Cameo Communications mips: dts: realtek: add device_type property to cpu node mips: dts: realtek: use "serial" instead of "uart" in node name MIPS: Implement ieee754 NAN2008 emulation mode MIPS: lantiq: improve USB initialization MIPS: GIC: Generate redirect block accessors MIPS: CPS: Add a couple of multi-cluster utility functions MIPS: Octeron: remove source file executable bit MAINTAINERS: Mobileye: add OLB drivers and dt-bindings MIPS: mobileye: eyeq5: add OLB system-controller node ...
This commit is contained in:
Linus Torvalds
@@ -2003,7 +2003,7 @@
|
||||
for the device. By default it is set to false (0).
|
||||
|
||||
ieee754= [MIPS] Select IEEE Std 754 conformance mode
|
||||
Format: { strict | legacy | 2008 | relaxed }
|
||||
Format: { strict | legacy | 2008 | relaxed | emulated }
|
||||
Default: strict
|
||||
|
||||
Choose which programs will be accepted for execution
|
||||
@@ -2023,6 +2023,8 @@
|
||||
by the FPU
|
||||
relaxed accept any binaries regardless of whether
|
||||
supported by the FPU
|
||||
emulated accept any binaries but enable FPU emulator
|
||||
if binary mode is unsupported by the FPU.
|
||||
|
||||
The FPU emulator is always able to support both NaN
|
||||
encodings, so if no FPU hardware is present or it has
|
||||
|
||||
@@ -25,6 +25,7 @@ properties:
|
||||
- items:
|
||||
- enum:
|
||||
- realtek,rtl8380-intc
|
||||
- realtek,rtl9300-intc
|
||||
- const: realtek,rtl-intc
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- const: realtek,rtl-intc
|
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deprecated: true
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||||
@@ -35,7 +36,10 @@ properties:
|
||||
const: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
minItems: 1
|
||||
items:
|
||||
- description: vpe0 registers
|
||||
- description: vpe1 registers
|
||||
|
||||
interrupts:
|
||||
minItems: 1
|
||||
@@ -71,6 +75,20 @@ allOf:
|
||||
else:
|
||||
required:
|
||||
- interrupts
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: realtek,rtl9300-intc
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||||
then:
|
||||
properties:
|
||||
reg:
|
||||
minItems: 2
|
||||
maxItems: 2
|
||||
else:
|
||||
properties:
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
additionalProperties: false
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||||
|
||||
|
||||
@@ -55,6 +55,16 @@ properties:
|
||||
under the "cpus" node.
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||||
$ref: /schemas/types.yaml#/definitions/uint32
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||||
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||||
brcm,bmips-cbr-reg:
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||||
description: Reference address of the CBR.
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||||
Some SoC suffer from a BUG where CBR(Core Base Register)
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||||
address might be badly or never initialized by the Bootloader
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||||
or reading it from co-processor registers, if the system boots
|
||||
from secondary CPU, results in invalid address.
|
||||
The CBR address is always the same on the SoC hence it
|
||||
can be provided in DT to handle these broken case.
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||||
$ref: /schemas/types.yaml#/definitions/uint32
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||||
|
||||
patternProperties:
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||||
"^cpu@[0-9]$":
|
||||
type: object
|
||||
@@ -64,6 +74,20 @@ properties:
|
||||
required:
|
||||
- mips-hpt-frequency
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||||
|
||||
if:
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||||
properties:
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||||
compatible:
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||||
contains:
|
||||
enum:
|
||||
- brcm,bcm6358
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||||
- brcm,bcm6368
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||||
|
||||
then:
|
||||
properties:
|
||||
cpus:
|
||||
required:
|
||||
- brcm,bmips-cbr-reg
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||||
|
||||
additionalProperties: true
|
||||
|
||||
examples:
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||||
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||||
@@ -26,6 +26,11 @@ properties:
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||||
- enum:
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- mobileye,eyeq5-epm5
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- const: mobileye,eyeq5
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- description: Boards with Mobileye EyeQ6H SoC
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||||
items:
|
||||
- enum:
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||||
- mobileye,eyeq6h-epm6
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||||
- const: mobileye,eyeq6h
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||||
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additionalProperties: true
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||||
|
||||
|
||||
@@ -20,5 +20,9 @@ properties:
|
||||
- enum:
|
||||
- cisco,sg220-26
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||||
- const: realtek,rtl8382-soc
|
||||
- items:
|
||||
- enum:
|
||||
- cameo,rtl9302c-2x-rtl8224-2xge
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||||
- const: realtek,rtl9302-soc
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
@@ -0,0 +1,374 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
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||||
%YAML 1.2
|
||||
---
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$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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||||
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||||
title: Mobileye EyeQ SoC system controller
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||||
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maintainers:
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||||
- Grégory Clement <gregory.clement@bootlin.com>
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- Théo Lebrun <theo.lebrun@bootlin.com>
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- Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
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||||
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description:
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OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks,
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resets, pinctrl are being handled from here. EyeQ5 and EyeQ6L host a single
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||||
instance. EyeQ6H hosts seven instances.
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||||
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||||
properties:
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||||
compatible:
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||||
items:
|
||||
- enum:
|
||||
- mobileye,eyeq5-olb
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- mobileye,eyeq6l-olb
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||||
- mobileye,eyeq6h-acc-olb
|
||||
- mobileye,eyeq6h-central-olb
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||||
- mobileye,eyeq6h-east-olb
|
||||
- mobileye,eyeq6h-west-olb
|
||||
- mobileye,eyeq6h-south-olb
|
||||
- mobileye,eyeq6h-ddr0-olb
|
||||
- mobileye,eyeq6h-ddr1-olb
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||||
- const: syscon
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||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#reset-cells':
|
||||
description:
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||||
First cell is domain and optional if compatible has a single reset domain.
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||||
Second cell is reset index inside that domain.
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||||
enum: [ 1, 2 ]
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||||
|
||||
'#clock-cells':
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||||
description:
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||||
Cell is clock index. Optional if compatible has a single clock.
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||||
enum: [ 0, 1 ]
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||||
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||||
clocks:
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||||
maxItems: 1
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||||
description:
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||||
Input parent clock to all PLLs. Expected to be the main crystal.
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||||
|
||||
clock-names:
|
||||
const: ref
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||||
|
||||
patternProperties:
|
||||
'-pins?$':
|
||||
type: object
|
||||
description: Pin muxing configuration.
|
||||
$ref: /schemas/pinctrl/pinmux-node.yaml#
|
||||
additionalProperties: false
|
||||
properties:
|
||||
pins: true
|
||||
function:
|
||||
enum: [gpio,
|
||||
# Bank A
|
||||
timer0, timer1, timer2, timer5, uart0, uart1, can0, can1, spi0,
|
||||
spi1, refclk0,
|
||||
# Bank B
|
||||
timer3, timer4, timer6, uart2, can2, spi2, spi3, mclk0]
|
||||
bias-disable: true
|
||||
bias-pull-down: true
|
||||
bias-pull-up: true
|
||||
drive-strength: true
|
||||
required:
|
||||
- pins
|
||||
- function
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: gpio
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items: # PA0 - PA28, PB0 - PB22
|
||||
pattern: '^(P(A|B)1?[0-9]|PA2[0-8]|PB2[0-2])$'
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: timer0
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA0, PA1]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: timer1
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA2, PA3]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: timer2
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA4, PA5]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: timer5
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA6, PA7, PA8, PA9]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uart0
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA10, PA11]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uart1
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA12, PA13]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: can0
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA14, PA15]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: can1
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA16, PA17]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi0
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA18, PA19, PA20, PA21, PA22]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi1
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA23, PA24, PA25, PA26, PA27]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: refclk0
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PA28]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: timer3
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PB0, PB1]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: timer4
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PB2, PB3]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: timer6
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PB4, PB5, PB6, PB7]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: uart2
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PB8, PB9]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: can2
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PB10, PB11]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi2
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PB12, PB13, PB14, PB15, PB16]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: spi3
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PB17, PB18, PB19, PB20, PB21]
|
||||
- if:
|
||||
properties:
|
||||
function:
|
||||
const: mclk0
|
||||
then:
|
||||
properties:
|
||||
pins:
|
||||
items:
|
||||
enum: [PB22]
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
allOf:
|
||||
# Compatibles exposing a single reset domain.
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- mobileye,eyeq6h-acc-olb
|
||||
- mobileye,eyeq6h-east-olb
|
||||
- mobileye,eyeq6h-west-olb
|
||||
then:
|
||||
properties:
|
||||
'#reset-cells':
|
||||
const: 1
|
||||
required:
|
||||
- '#reset-cells'
|
||||
|
||||
# Compatibles exposing two reset domains.
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- mobileye,eyeq5-olb
|
||||
- mobileye,eyeq6l-olb
|
||||
then:
|
||||
properties:
|
||||
'#reset-cells':
|
||||
const: 2
|
||||
required:
|
||||
- '#reset-cells'
|
||||
|
||||
# Compatibles not exposing resets.
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- mobileye,eyeq6h-central-olb
|
||||
- mobileye,eyeq6h-south-olb
|
||||
- mobileye,eyeq6h-ddr0-olb
|
||||
- mobileye,eyeq6h-ddr1-olb
|
||||
then:
|
||||
properties:
|
||||
'#reset-cells': false
|
||||
|
||||
# Compatibles exposing a single clock.
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- mobileye,eyeq6h-central-olb
|
||||
- mobileye,eyeq6h-east-olb
|
||||
- mobileye,eyeq6h-west-olb
|
||||
- mobileye,eyeq6h-ddr0-olb
|
||||
- mobileye,eyeq6h-ddr1-olb
|
||||
then:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 0
|
||||
else:
|
||||
properties:
|
||||
'#clock-cells':
|
||||
const: 1
|
||||
|
||||
# Only EyeQ5 has pinctrl in OLB.
|
||||
- if:
|
||||
not:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: mobileye,eyeq5-olb
|
||||
then:
|
||||
patternProperties:
|
||||
'-pins?$': false
|
||||
|
||||
examples:
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
system-controller@e00000 {
|
||||
compatible = "mobileye,eyeq5-olb", "syscon";
|
||||
reg = <0 0xe00000 0x0 0x400>;
|
||||
#reset-cells = <2>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
};
|
||||
- |
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
||||
system-controller@d2003000 {
|
||||
compatible = "mobileye,eyeq6h-acc-olb", "syscon";
|
||||
reg = <0x0 0xd2003000 0x0 0x1000>;
|
||||
#reset-cells = <1>;
|
||||
#clock-cells = <1>;
|
||||
clocks = <&xtal>;
|
||||
clock-names = "ref";
|
||||
};
|
||||
};
|
||||
@@ -246,6 +246,8 @@ patternProperties:
|
||||
description: CALAO Systems SAS
|
||||
"^calxeda,.*":
|
||||
description: Calxeda
|
||||
"^cameo,.*":
|
||||
description: Cameo Communications, Inc
|
||||
"^canaan,.*":
|
||||
description: Canaan, Inc.
|
||||
"^caninos,.*":
|
||||
|
||||
@@ -15406,9 +15406,14 @@ M: Théo Lebrun <theo.lebrun@bootlin.com>
|
||||
L: linux-mips@vger.kernel.org
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/mips/mobileye.yaml
|
||||
F: Documentation/devicetree/bindings/soc/mobileye/
|
||||
F: arch/mips/boot/dts/mobileye/
|
||||
F: arch/mips/configs/eyeq5_defconfig
|
||||
F: arch/mips/mobileye/board-epm5.its.S
|
||||
F: drivers/clk/clk-eyeq.c
|
||||
F: drivers/pinctrl/pinctrl-eyeq5.c
|
||||
F: drivers/reset/reset-eyeq.c
|
||||
F: include/dt-bindings/clock/mobileye,eyeq5-clk.h
|
||||
|
||||
MODULE SUPPORT
|
||||
M: Luis Chamberlain <mcgrof@kernel.org>
|
||||
|
||||
@@ -8,6 +8,7 @@ platform-$(CONFIG_BCM47XX) += bcm47xx/
|
||||
platform-$(CONFIG_BCM63XX) += bcm63xx/
|
||||
platform-$(CONFIG_BMIPS_GENERIC) += bmips/
|
||||
platform-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon/
|
||||
platform-$(CONFIG_EYEQ) += mobileye/
|
||||
platform-$(CONFIG_MIPS_COBALT) += cobalt/
|
||||
platform-$(CONFIG_MACH_DECSTATION) += dec/
|
||||
platform-$(CONFIG_MIPS_GENERIC) += generic/
|
||||
@@ -17,7 +18,6 @@ platform-$(CONFIG_MACH_LOONGSON2EF) += loongson2ef/
|
||||
platform-$(CONFIG_MACH_LOONGSON32) += loongson32/
|
||||
platform-$(CONFIG_MACH_LOONGSON64) += loongson64/
|
||||
platform-$(CONFIG_MIPS_MALTA) += mti-malta/
|
||||
platform-$(CONFIG_MACH_EYEQ5) += mobileye/
|
||||
platform-$(CONFIG_MACH_NINTENDO64) += n64/
|
||||
platform-$(CONFIG_PIC32MZDA) += pic32/
|
||||
platform-$(CONFIG_RALINK) += ralink/
|
||||
|
||||
+7
-4
@@ -30,7 +30,7 @@ config MIPS
|
||||
select BUILDTIME_TABLE_SORT
|
||||
select CLONE_BACKWARDS
|
||||
select CPU_NO_EFFICIENT_FFS if (TARGET_ISA_REV < 1)
|
||||
select CPU_PM if CPU_IDLE
|
||||
select CPU_PM if CPU_IDLE || SUSPEND
|
||||
select GENERIC_ATOMIC64 if !64BIT
|
||||
select GENERIC_CMOS_UPDATE
|
||||
select GENERIC_CPU_AUTOPROBE
|
||||
@@ -575,8 +575,8 @@ config MACH_PIC32
|
||||
Microchip PIC32 is a family of general-purpose 32 bit MIPS core
|
||||
microcontrollers.
|
||||
|
||||
config MACH_EYEQ5
|
||||
bool "Mobileye EyeQ5 SoC"
|
||||
config EYEQ
|
||||
bool "Mobileye EyeQ SoC"
|
||||
select MACH_GENERIC_CORE
|
||||
select ARM_AMBA
|
||||
select PHYSICAL_START_BOOL
|
||||
@@ -615,7 +615,7 @@ config MACH_EYEQ5
|
||||
select USB_UHCI_BIG_ENDIAN_MMIO if CPU_BIG_ENDIAN
|
||||
select USE_OF
|
||||
help
|
||||
Select this to build a kernel supporting EyeQ5 SoC from Mobileye.
|
||||
Select this to build a kernel supporting EyeQ SoC from Mobileye.
|
||||
|
||||
bool
|
||||
|
||||
@@ -667,6 +667,7 @@ config MACH_REALTEK_RTL
|
||||
select BOOT_RAW
|
||||
select PINCTRL
|
||||
select USE_OF
|
||||
select REALTEK_OTTO_TIMER
|
||||
|
||||
config SGI_IP22
|
||||
bool "SGI IP22 (Indy/Indigo2)"
|
||||
@@ -1021,6 +1022,7 @@ source "arch/mips/generic/Kconfig"
|
||||
source "arch/mips/ingenic/Kconfig"
|
||||
source "arch/mips/jazz/Kconfig"
|
||||
source "arch/mips/lantiq/Kconfig"
|
||||
source "arch/mips/mobileye/Kconfig"
|
||||
source "arch/mips/pic32/Kconfig"
|
||||
source "arch/mips/ralink/Kconfig"
|
||||
source "arch/mips/sgi-ip27/Kconfig"
|
||||
@@ -1083,6 +1085,7 @@ config CSRC_IOASIC
|
||||
|
||||
config CSRC_R4K
|
||||
select CLOCKSOURCE_WATCHDOG if CPU_FREQ
|
||||
select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT
|
||||
bool
|
||||
|
||||
config CSRC_SB1250
|
||||
|
||||
+1
-1
@@ -170,7 +170,7 @@ cflags-$(CONFIG_CPU_NEVADA) += $(call cc-option,-march=rm5200,-march=mips4) \
|
||||
-Wa,--trap
|
||||
cflags-$(CONFIG_CPU_RM7000) += $(call cc-option,-march=rm7000,-march=mips4) \
|
||||
-Wa,--trap
|
||||
cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=mips64r1) \
|
||||
cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-march=sb1,-march=mips64) \
|
||||
-Wa,--trap
|
||||
cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mdmx)
|
||||
cflags-$(CONFIG_CPU_SB1) += $(call cc-option,-mno-mips3d)
|
||||
|
||||
@@ -409,8 +409,8 @@ static void __init alchemy_setup_macs(int ctype)
|
||||
if (alchemy_get_macs(ctype) < 1)
|
||||
return;
|
||||
|
||||
macres = kmemdup(au1xxx_eth0_resources[ctype],
|
||||
sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
|
||||
macres = kmemdup_array(au1xxx_eth0_resources[ctype], MAC_RES_COUNT,
|
||||
sizeof(*macres), GFP_KERNEL);
|
||||
if (!macres) {
|
||||
printk(KERN_INFO "Alchemy: no memory for MAC0 resources\n");
|
||||
return;
|
||||
@@ -430,8 +430,8 @@ static void __init alchemy_setup_macs(int ctype)
|
||||
if (alchemy_get_macs(ctype) < 2)
|
||||
return;
|
||||
|
||||
macres = kmemdup(au1xxx_eth1_resources[ctype],
|
||||
sizeof(struct resource) * MAC_RES_COUNT, GFP_KERNEL);
|
||||
macres = kmemdup_array(au1xxx_eth1_resources[ctype], MAC_RES_COUNT,
|
||||
sizeof(*macres), GFP_KERNEL);
|
||||
if (!macres) {
|
||||
printk(KERN_INFO "Alchemy: no memory for MAC1 resources\n");
|
||||
return;
|
||||
|
||||
@@ -10,15 +10,16 @@
|
||||
#include <linux/dma-mapping.h>
|
||||
#include <linux/gpio.h>
|
||||
#include <linux/gpio/machine.h>
|
||||
#include <linux/gpio/property.h>
|
||||
#include <linux/init.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/leds.h>
|
||||
#include <linux/mmc/host.h>
|
||||
#include <linux/platform_device.h>
|
||||
#include <linux/property.h>
|
||||
#include <linux/pm.h>
|
||||
#include <linux/spi/spi.h>
|
||||
#include <linux/spi/spi_gpio.h>
|
||||
#include <linux/spi/ads7846.h>
|
||||
#include <asm/mach-au1x00/au1000.h>
|
||||
#include <asm/mach-au1x00/gpio-au1000.h>
|
||||
#include <asm/mach-au1x00/au1000_dma.h>
|
||||
@@ -374,22 +375,20 @@ static struct platform_device db1100_mmc1_dev = {
|
||||
|
||||
/******************************************************************************/
|
||||
|
||||
static struct ads7846_platform_data db1100_touch_pd = {
|
||||
.model = 7846,
|
||||
.vref_mv = 3300,
|
||||
static const struct software_node db1100_alchemy2_gpiochip = {
|
||||
.name = "alchemy-gpio2",
|
||||
};
|
||||
|
||||
static struct spi_gpio_platform_data db1100_spictl_pd = {
|
||||
.num_chipselect = 1,
|
||||
static const struct property_entry db1100_ads7846_properties[] = {
|
||||
PROPERTY_ENTRY_U16("ti,vref_min", 3300),
|
||||
PROPERTY_ENTRY_GPIO("pendown-gpios",
|
||||
&db1100_alchemy2_gpiochip, 21, GPIO_ACTIVE_LOW),
|
||||
{ }
|
||||
};
|
||||
|
||||
static struct gpiod_lookup_table db1100_touch_gpio_table = {
|
||||
.dev_id = "spi0.0",
|
||||
.table = {
|
||||
GPIO_LOOKUP("alchemy-gpio2", 21,
|
||||
"pendown", GPIO_ACTIVE_LOW),
|
||||
{ }
|
||||
},
|
||||
static const struct software_node db1100_ads7846_swnode = {
|
||||
.name = "ads7846",
|
||||
.properties = db1100_ads7846_properties,
|
||||
};
|
||||
|
||||
static struct spi_board_info db1100_spi_info[] __initdata = {
|
||||
@@ -400,37 +399,37 @@ static struct spi_board_info db1100_spi_info[] __initdata = {
|
||||
.chip_select = 0,
|
||||
.mode = 0,
|
||||
.irq = AU1100_GPIO21_INT,
|
||||
.platform_data = &db1100_touch_pd,
|
||||
.swnode = &db1100_ads7846_swnode,
|
||||
},
|
||||
};
|
||||
|
||||
static struct platform_device db1100_spi_dev = {
|
||||
.name = "spi_gpio",
|
||||
.id = 0,
|
||||
.dev = {
|
||||
.platform_data = &db1100_spictl_pd,
|
||||
.dma_mask = &au1xxx_all_dmamask,
|
||||
.coherent_dma_mask = DMA_BIT_MASK(32),
|
||||
},
|
||||
static const struct spi_gpio_platform_data db1100_spictl_pd __initconst = {
|
||||
.num_chipselect = 1,
|
||||
};
|
||||
|
||||
/*
|
||||
* Alchemy GPIO 2 has its base at 200 so the GPIO lines
|
||||
* 207 thru 210 are GPIOs at offset 7 thru 10 at this chip.
|
||||
*/
|
||||
static struct gpiod_lookup_table db1100_spi_gpiod_table = {
|
||||
.dev_id = "spi_gpio",
|
||||
.table = {
|
||||
GPIO_LOOKUP("alchemy-gpio2", 9,
|
||||
"sck", GPIO_ACTIVE_HIGH),
|
||||
GPIO_LOOKUP("alchemy-gpio2", 8,
|
||||
"mosi", GPIO_ACTIVE_HIGH),
|
||||
GPIO_LOOKUP("alchemy-gpio2", 7,
|
||||
"miso", GPIO_ACTIVE_HIGH),
|
||||
GPIO_LOOKUP("alchemy-gpio2", 10,
|
||||
"cs", GPIO_ACTIVE_HIGH),
|
||||
{ },
|
||||
},
|
||||
static const struct property_entry db1100_spi_dev_properties[] __initconst = {
|
||||
PROPERTY_ENTRY_GPIO("miso-gpios",
|
||||
&db1100_alchemy2_gpiochip, 7, GPIO_ACTIVE_HIGH),
|
||||
PROPERTY_ENTRY_GPIO("mosi-gpios",
|
||||
&db1100_alchemy2_gpiochip, 8, GPIO_ACTIVE_HIGH),
|
||||
PROPERTY_ENTRY_GPIO("sck-gpios",
|
||||
&db1100_alchemy2_gpiochip, 9, GPIO_ACTIVE_HIGH),
|
||||
PROPERTY_ENTRY_GPIO("cs-gpios",
|
||||
&db1100_alchemy2_gpiochip, 10, GPIO_ACTIVE_HIGH),
|
||||
{ }
|
||||
};
|
||||
|
||||
static const struct platform_device_info db1100_spi_dev_info __initconst = {
|
||||
.name = "spi_gpio",
|
||||
.id = 0,
|
||||
.data = &db1100_spictl_pd,
|
||||
.size_data = sizeof(db1100_spictl_pd),
|
||||
.dma_mask = DMA_BIT_MASK(32),
|
||||
.properties = db1100_spi_dev_properties,
|
||||
};
|
||||
|
||||
static struct platform_device *db1x00_devs[] = {
|
||||
@@ -452,8 +451,10 @@ int __init db1000_dev_setup(void)
|
||||
{
|
||||
int board = BCSR_WHOAMI_BOARD(bcsr_read(BCSR_WHOAMI));
|
||||
int c0, c1, d0, d1, s0, s1, flashsize = 32, twosocks = 1;
|
||||
int err;
|
||||
unsigned long pfc;
|
||||
struct clk *c, *p;
|
||||
struct platform_device *spi_dev;
|
||||
|
||||
if (board == BCSR_WHOAMI_DB1500) {
|
||||
c0 = AU1500_GPIO2_INT;
|
||||
@@ -480,7 +481,7 @@ int __init db1000_dev_setup(void)
|
||||
pfc |= (1 << 0); /* SSI0 pins as GPIOs */
|
||||
alchemy_wrsys(pfc, AU1000_SYS_PINFUNC);
|
||||
|
||||
gpiod_add_lookup_table(&db1100_touch_gpio_table);
|
||||
software_node_register(&db1100_alchemy2_gpiochip);
|
||||
spi_register_board_info(db1100_spi_info,
|
||||
ARRAY_SIZE(db1100_spi_info));
|
||||
|
||||
@@ -497,8 +498,11 @@ int __init db1000_dev_setup(void)
|
||||
clk_put(p);
|
||||
|
||||
platform_add_devices(db1100_devs, ARRAY_SIZE(db1100_devs));
|
||||
gpiod_add_lookup_table(&db1100_spi_gpiod_table);
|
||||
platform_device_register(&db1100_spi_dev);
|
||||
|
||||
spi_dev = platform_device_register_full(&db1100_spi_dev_info);
|
||||
err = PTR_ERR_OR_ZERO(spi_dev);
|
||||
if (err)
|
||||
pr_err("failed to register SPI controller: %d\n", err);
|
||||
} else if (board == BCSR_WHOAMI_DB1000) {
|
||||
c0 = AU1000_GPIO2_INT;
|
||||
c1 = AU1000_GPIO5_INT;
|
||||
|
||||
@@ -32,6 +32,7 @@
|
||||
#include <linux/ssb/ssb_driver_chipcommon.h>
|
||||
#include <linux/ssb/ssb_regs.h>
|
||||
#include <linux/smp.h>
|
||||
#include <asm/bmips.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <bcm47xx.h>
|
||||
#include <bcm47xx_board.h>
|
||||
@@ -110,6 +111,8 @@ static __init void prom_init_mem(void)
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
/* Cache CBR addr before CPU/DMA setup */
|
||||
bmips_cbr_addr = BMIPS_GET_CBR();
|
||||
prom_init_mem();
|
||||
setup_8250_early_printk_port(CKSEG1ADDR(BCM47XX_SERIAL_ADDR), 0, 0);
|
||||
}
|
||||
|
||||
@@ -37,6 +37,7 @@
|
||||
#include <linux/ssb/ssb.h>
|
||||
#include <linux/ssb/ssb_embedded.h>
|
||||
#include <linux/bcma/bcma_soc.h>
|
||||
#include <asm/bmips.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/idle.h>
|
||||
#include <asm/prom.h>
|
||||
@@ -45,6 +46,13 @@
|
||||
#include <bcm47xx.h>
|
||||
#include <bcm47xx_board.h>
|
||||
|
||||
/*
|
||||
* CBR addr doesn't change and we can cache it.
|
||||
* For broken SoC/Bootloader CBR addr might also be provided via DT
|
||||
* with "brcm,bmips-cbr-reg" in the "cpus" node.
|
||||
*/
|
||||
void __iomem *bmips_cbr_addr __read_mostly;
|
||||
|
||||
union bcm47xx_bus bcm47xx_bus;
|
||||
EXPORT_SYMBOL(bcm47xx_bus);
|
||||
|
||||
|
||||
@@ -22,6 +22,9 @@ void __init prom_init(void)
|
||||
{
|
||||
u32 reg, mask;
|
||||
|
||||
/* Cache CBR addr before CPU/DMA setup */
|
||||
bmips_cbr_addr = BMIPS_GET_CBR();
|
||||
|
||||
bcm63xx_cpu_init();
|
||||
|
||||
/* stop any running watchdog */
|
||||
|
||||
@@ -12,6 +12,7 @@
|
||||
#include <linux/memblock.h>
|
||||
#include <linux/ioport.h>
|
||||
#include <linux/pm.h>
|
||||
#include <asm/bmips.h>
|
||||
#include <asm/bootinfo.h>
|
||||
#include <asm/time.h>
|
||||
#include <asm/reboot.h>
|
||||
@@ -22,6 +23,13 @@
|
||||
#include <bcm63xx_io.h>
|
||||
#include <bcm63xx_gpio.h>
|
||||
|
||||
/*
|
||||
* CBR addr doesn't change and we can cache it.
|
||||
* For broken SoC/Bootloader CBR addr might also be provided via DT
|
||||
* with "brcm,bmips-cbr-reg" in the "cpus" node.
|
||||
*/
|
||||
void __iomem *bmips_cbr_addr __read_mostly;
|
||||
|
||||
void bcm63xx_machine_halt(void)
|
||||
{
|
||||
pr_info("System halted\n");
|
||||
|
||||
@@ -9,7 +9,7 @@ bool bmips_rac_flush_disable;
|
||||
|
||||
void arch_sync_dma_for_cpu_all(void)
|
||||
{
|
||||
void __iomem *cbr = BMIPS_GET_CBR();
|
||||
void __iomem *cbr = bmips_cbr_addr;
|
||||
u32 cfg;
|
||||
|
||||
if (boot_cpu_type() != CPU_BMIPS3300 &&
|
||||
|
||||
+33
-2
@@ -34,6 +34,13 @@
|
||||
#define REG_BCM6328_OTP ((void __iomem *)CKSEG1ADDR(0x1000062c))
|
||||
#define BCM6328_TP1_DISABLED BIT(9)
|
||||
|
||||
/*
|
||||
* CBR addr doesn't change and we can cache it.
|
||||
* For broken SoC/Bootloader CBR addr might also be provided via DT
|
||||
* with "brcm,bmips-cbr-reg" in the "cpus" node.
|
||||
*/
|
||||
void __iomem *bmips_cbr_addr __read_mostly;
|
||||
|
||||
extern bool bmips_rac_flush_disable;
|
||||
|
||||
static const unsigned long kbase = VMLINUX_LOAD_ADDRESS & 0xfff00000;
|
||||
@@ -111,7 +118,7 @@ static void bcm6358_quirks(void)
|
||||
* because the bootloader is not initializing it properly.
|
||||
*/
|
||||
bmips_rac_flush_disable = !!(read_c0_brcm_cmt_local() & (1 << 31)) ||
|
||||
!!BMIPS_GET_CBR();
|
||||
!!bmips_cbr_addr;
|
||||
}
|
||||
|
||||
static void bcm6368_quirks(void)
|
||||
@@ -144,6 +151,8 @@ static void __init bmips_init_cfe(void)
|
||||
|
||||
void __init prom_init(void)
|
||||
{
|
||||
/* Cache CBR addr before CPU/DMA setup */
|
||||
bmips_cbr_addr = BMIPS_GET_CBR();
|
||||
bmips_init_cfe();
|
||||
bmips_cpu_setup();
|
||||
register_bmips_smp_ops();
|
||||
@@ -203,13 +212,35 @@ void __init plat_mem_setup(void)
|
||||
void __init device_tree_init(void)
|
||||
{
|
||||
struct device_node *np;
|
||||
u32 addr;
|
||||
|
||||
unflatten_and_copy_device_tree();
|
||||
|
||||
/* Disable SMP boot unless both CPUs are listed in DT and !disabled */
|
||||
np = of_find_node_by_name(NULL, "cpus");
|
||||
if (np && of_get_available_child_count(np) <= 1)
|
||||
if (!np)
|
||||
return;
|
||||
|
||||
if (of_get_available_child_count(np) <= 1)
|
||||
bmips_smp_enabled = 0;
|
||||
|
||||
/* Check if DT provide a CBR address */
|
||||
if (of_property_read_u32(np, "brcm,bmips-cbr-reg", &addr))
|
||||
goto exit;
|
||||
|
||||
/* Make sure CBR address is outside DRAM window */
|
||||
if (addr >= (u32)memblock_start_of_DRAM() &&
|
||||
addr < (u32)memblock_end_of_DRAM()) {
|
||||
WARN(1, "DT CBR %x inside DRAM window. Ignoring DT CBR.\n",
|
||||
addr);
|
||||
goto exit;
|
||||
}
|
||||
|
||||
bmips_cbr_addr = (void __iomem *)addr;
|
||||
/* Since CBR is provided by DT, enable RAC flush */
|
||||
bmips_rac_flush_disable = false;
|
||||
|
||||
exit:
|
||||
of_node_put(np);
|
||||
}
|
||||
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
subdir-$(CONFIG_BMIPS_GENERIC) += brcm
|
||||
subdir-$(CONFIG_CAVIUM_OCTEON_SOC) += cavium-octeon
|
||||
subdir-$(CONFIG_EYEQ) += mobileye
|
||||
subdir-$(CONFIG_FIT_IMAGE_FDT_MARDUK) += img
|
||||
subdir-$(CONFIG_FIT_IMAGE_FDT_BOSTON) += img
|
||||
subdir-$(CONFIG_MACH_INGENIC) += ingenic
|
||||
@@ -8,7 +9,6 @@ subdir-$(CONFIG_LANTIQ) += lantiq
|
||||
subdir-$(CONFIG_MACH_LOONGSON64) += loongson
|
||||
subdir-$(CONFIG_SOC_VCOREIII) += mscc
|
||||
subdir-$(CONFIG_MIPS_MALTA) += mti
|
||||
subdir-$(CONFIG_MACH_EYEQ5) += mobileye
|
||||
subdir-$(CONFIG_LEGACY_BOARD_SEAD3) += mti
|
||||
subdir-$(CONFIG_FIT_IMAGE_FDT_NI169445) += ni
|
||||
subdir-$(CONFIG_MACH_PIC32) += pic32
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user