mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'phy-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy
Pull phy updates from Vinod Koul:
"As usual featuring couple of new driver and bunch of new device
support and some driver changes to Freescale, rockchip driver along
with couple of yaml binding conversions.
New Support:
- Qualcomm IPQ5424 qusb2 support, IPQ5018 uniphy-pcie driver
- Rockchip usb2 support for RK3562, RK3036 usb2 phy support
- Samsung exynos2200 eusb2 phy support and driver refactoring for
this support, exynos7870 USBDRD support
- Mediatek MT7988 xs-phy support
- Broadcom BCM74110 usb phy support
- Renesas RZ/V2H(P) usb2 phy support
Updates:
- Freescale phy rate claculation updates, i.MX95 tuning support
- Better error handling for amlogic pcie phy
- Rockchip color depth configuration and management support
- Yaml binding conversion for RK3399 Type-C and PCIe Phy"
* tag 'phy-for-6.16' of git://git.kernel.org/pub/scm/linux/kernel/git/phy/linux-phy: (77 commits)
phy: tegra: p2u: Broaden architecture dependency
phy: rockchip: inno-usb2: Add usb2 phy support for rk3562
dt-bindings: phy: rockchip,inno-usb2phy: add rk3562
phy: rockchip: inno-usb2: add phy definition for rk3036
dt-bindings: phy: rockchip,inno-usb2phy: add rk3036 compatible
phy: freescale: fsl-samsung-hdmi: Improve LUT search for best clock
phy: freescale: fsl-samsung-hdmi: Refactor finding PHY settings
phy: freescale: fsl-samsung-hdmi: Rename phy_clk_round_rate
phy: renesas: phy-rcar-gen3-usb2: Add USB2.0 PHY support for RZ/V2H(P)
phy: renesas: phy-rcar-gen3-usb2: Sort compatible entries by SoC part number
dt-bindings: phy: renesas,usb2-phy: Document RZ/V2H(P) SoC
dt-bindings: phy: renesas,usb2-phy: Add clock constraint for RZ/G2L family
phy: exynos5-usbdrd: support Exynos USBDRD 3.2 4nm controller
phy: phy-snps-eusb2: add support for exynos2200
phy: phy-snps-eusb2: refactor reference clock init
phy: phy-snps-eusb2: make reset control optional
phy: phy-snps-eusb2: make repeater optional
phy: phy-snps-eusb2: split phy init code
phy: phy-snps-eusb2: refactor constructs names
phy: move phy-qcom-snps-eusb2 out of its vendor sub-directory
...
This commit is contained in:
Linus Torvalds
@@ -18,6 +18,7 @@ properties:
|
||||
- brcm,bcm4908-usb-phy
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- brcm,bcm7211-usb-phy
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||||
- brcm,bcm7216-usb-phy
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||||
- brcm,bcm74110-usb-phy
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- brcm,brcmstb-usb-phy
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||||
|
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reg:
|
||||
@@ -139,7 +140,9 @@ allOf:
|
||||
properties:
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||||
compatible:
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contains:
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const: brcm,bcm7216-usb-phy
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||||
enum:
|
||||
- brcm,bcm7216-usb-phy
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- brcm,bcm74110-usb-phy
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then:
|
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properties:
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reg:
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||||
|
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@@ -43,15 +43,15 @@ properties:
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||||
fsl,phy-tx-vref-tune-percent:
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description:
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Tunes the HS DC level relative to the nominal level
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minimum: 94
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minimum: 90
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maximum: 124
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fsl,phy-tx-rise-tune-percent:
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description:
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Adjusts the rise/fall time duration of the HS waveform relative to
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its nominal value
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minimum: 97
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maximum: 103
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minimum: 90
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maximum: 120
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fsl,phy-tx-preemp-amp-tune-microamp:
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description:
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@@ -63,8 +63,7 @@ properties:
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fsl,phy-tx-vboost-level-microvolt:
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description:
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Adjust the boosted transmit launch pk-pk differential amplitude
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minimum: 880
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maximum: 1120
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enum: [844, 1008, 1156]
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fsl,phy-comp-dis-tune-percent:
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description:
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@@ -112,6 +111,34 @@ allOf:
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reg:
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maxItems: 1
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||||
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- if:
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properties:
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compatible:
|
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enum:
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- fsl,imx8mq-usb-phy
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- fsl,imx8mp-usb-phy
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then:
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properties:
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fsl,phy-tx-vref-tune-percent:
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minimum: 94
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fsl,phy-tx-rise-tune-percent:
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minimum: 97
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maximum: 103
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- if:
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properties:
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compatible:
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contains:
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enum:
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- fsl,imx95-usb-phy
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then:
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properties:
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fsl,phy-tx-vref-tune-percent:
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maximum: 108
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fsl,phy-comp-dis-tune-percent:
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minimum: 94
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maximum: 104
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|
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- if:
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required:
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- orientation-switch
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@@ -30,6 +30,7 @@ properties:
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- const: mediatek,mt8173-mipi-tx
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- items:
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- enum:
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- mediatek,mt6893-mipi-tx
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- mediatek,mt8188-mipi-tx
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- mediatek,mt8195-mipi-tx
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- mediatek,mt8365-mipi-tx
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@@ -78,6 +78,7 @@ properties:
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- items:
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- enum:
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- mediatek,mt2712-tphy
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- mediatek,mt6893-tphy
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- mediatek,mt7629-tphy
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- mediatek,mt7986-tphy
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- mediatek,mt8183-tphy
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|
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@@ -49,6 +49,7 @@ properties:
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- enum:
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- mediatek,mt3611-xsphy
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- mediatek,mt3612-xsphy
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- mediatek,mt7988-xsphy
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- const: mediatek,xsphy
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|
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reg:
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||||
@@ -150,6 +151,21 @@ patternProperties:
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minimum: 1
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maximum: 31
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mediatek,syscon-type:
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$ref: /schemas/types.yaml#/definitions/phandle-array
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description:
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A phandle to syscon used to access the register of type switch,
|
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the field should always be 3 cells long.
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items:
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- items:
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- description:
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Phandle to phy type configuration system controller
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- description:
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Phy type configuration register offset
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- description:
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Index of config segment
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enum: [0, 1, 2, 3]
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|
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required:
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- reg
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- clocks
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@@ -99,8 +99,7 @@ patternProperties:
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Specifies the type of PHY for which the group of PHY lanes is used.
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Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 9
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enum: [1, 2, 3, 4, 5, 6, 7, 8, 9, 12]
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cdns,num-lanes:
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description:
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||||
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@@ -42,6 +42,9 @@ properties:
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- const: phy
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- const: apb
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phy-supply:
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description: Single PHY regulator
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rockchip,enable-ssc:
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type: boolean
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description:
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@@ -1,84 +0,0 @@
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* ROCKCHIP type-c PHY
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---------------------
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Required properties:
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- compatible : must be "rockchip,rk3399-typec-phy"
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- reg: Address and length of the usb phy control register set
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- rockchip,grf : phandle to the syscon managing the "general
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register files"
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- clocks : phandle + clock specifier for the phy clocks
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- clock-names : string, clock name, must be "tcpdcore", "tcpdphy-ref";
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- assigned-clocks: main clock, should be <&cru SCLK_UPHY0_TCPDCORE> or
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<&cru SCLK_UPHY1_TCPDCORE>;
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- assigned-clock-rates : the phy core clk frequency, shall be: 50000000
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- resets : a list of phandle + reset specifier pairs
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- reset-names : string reset name, must be:
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"uphy", "uphy-pipe", "uphy-tcphy"
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Optional properties:
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- extcon : extcon specifier for the Power Delivery
|
||||
|
||||
Required nodes : a sub-node is required for each port the phy provides.
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The sub-node name is used to identify dp or usb3 port,
|
||||
and shall be the following entries:
|
||||
* "dp-port" : the name of DP port.
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* "usb3-port" : the name of USB3 port.
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Required properties (port (child) node):
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- #phy-cells : must be 0, See ./phy-bindings.txt for details.
|
||||
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Deprecated properties, do not use in new device tree sources, these
|
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properties are determined by the compatible value:
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||||
- rockchip,typec-conn-dir
|
||||
- rockchip,usb3tousb2-en
|
||||
- rockchip,external-psm
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- rockchip,pipe-status
|
||||
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Example:
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tcphy0: phy@ff7c0000 {
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compatible = "rockchip,rk3399-typec-phy";
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reg = <0x0 0xff7c0000 0x0 0x40000>;
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rockchip,grf = <&grf>;
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extcon = <&fusb0>;
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clocks = <&cru SCLK_UPHY0_TCPDCORE>,
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<&cru SCLK_UPHY0_TCPDPHY_REF>;
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clock-names = "tcpdcore", "tcpdphy-ref";
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assigned-clocks = <&cru SCLK_UPHY0_TCPDCORE>;
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assigned-clock-rates = <50000000>;
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resets = <&cru SRST_UPHY0>,
|
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<&cru SRST_UPHY0_PIPE_L00>,
|
||||
<&cru SRST_P_UPHY0_TCPHY>;
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reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
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tcphy0_dp: dp-port {
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#phy-cells = <0>;
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};
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tcphy0_usb3: usb3-port {
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#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
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tcphy1: phy@ff800000 {
|
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compatible = "rockchip,rk3399-typec-phy";
|
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reg = <0x0 0xff800000 0x0 0x40000>;
|
||||
rockchip,grf = <&grf>;
|
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extcon = <&fusb1>;
|
||||
clocks = <&cru SCLK_UPHY1_TCPDCORE>,
|
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<&cru SCLK_UPHY1_TCPDPHY_REF>;
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clock-names = "tcpdcore", "tcpdphy-ref";
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assigned-clocks = <&cru SCLK_UPHY1_TCPDCORE>;
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assigned-clock-rates = <50000000>;
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resets = <&cru SRST_UPHY1>,
|
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<&cru SRST_UPHY1_PIPE_L00>,
|
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<&cru SRST_P_UPHY1_TCPHY>;
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reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
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|
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tcphy1_dp: dp-port {
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#phy-cells = <0>;
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||||
};
|
||||
|
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tcphy1_usb3: usb3-port {
|
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#phy-cells = <0>;
|
||||
};
|
||||
};
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@@ -47,6 +47,9 @@ properties:
|
||||
- const: pcs_apb
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- const: pma_apb
|
||||
|
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phy-supply:
|
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description: Single PHY regulator
|
||||
|
||||
rockchip,dp-lane-mux:
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$ref: /schemas/types.yaml#/definitions/uint32-array
|
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minItems: 2
|
||||
|
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@@ -11,26 +11,24 @@ maintainers:
|
||||
- Varadarajan Narayanan <quic_varada@quicinc.com>
|
||||
|
||||
description:
|
||||
PCIe and USB combo PHY found in Qualcomm IPQ5332 SoC
|
||||
PCIe and USB combo PHY found in Qualcomm IPQ5018 & IPQ5332 SoCs
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,ipq5018-uniphy-pcie-phy
|
||||
- qcom,ipq5332-uniphy-pcie-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
items:
|
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- description: pcie pipe clock
|
||||
- description: pcie ahb clock
|
||||
minItems: 1
|
||||
maxItems: 2
|
||||
|
||||
resets:
|
||||
items:
|
||||
- description: phy reset
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||||
- description: ahb reset
|
||||
- description: cfg reset
|
||||
minItems: 2
|
||||
maxItems: 3
|
||||
|
||||
"#phy-cells":
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const: 0
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||||
@@ -53,6 +51,41 @@ required:
|
||||
|
||||
additionalProperties: false
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||||
|
||||
allOf:
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- if:
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properties:
|
||||
compatible:
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||||
contains:
|
||||
enum:
|
||||
- qcom,ipq5018-uniphy-pcie-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: pcie pipe clock
|
||||
resets:
|
||||
items:
|
||||
- description: phy reset
|
||||
- description: cfg reset
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,ipq5332-uniphy-pcie-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
items:
|
||||
- description: pcie pipe clock
|
||||
- description: pcie ahb clock
|
||||
resets:
|
||||
items:
|
||||
- description: phy reset
|
||||
- description: ahb reset
|
||||
- description: cfg reset
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/qcom,ipq5332-gcc.h>
|
||||
|
||||
@@ -16,6 +16,7 @@ properties:
|
||||
- enum:
|
||||
- renesas,usb2-phy-r8a77470 # RZ/G1C
|
||||
- renesas,usb2-phy-r9a08g045 # RZ/G3S
|
||||
- renesas,usb2-phy-r9a09g057 # RZ/V2H(P)
|
||||
|
||||
- items:
|
||||
- enum:
|
||||
@@ -105,8 +106,13 @@ allOf:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: renesas,rzg2l-usb2-phy
|
||||
enum:
|
||||
- renesas,usb2-phy-r9a09g057
|
||||
- renesas,rzg2l-usb2-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
minItems: 2
|
||||
required:
|
||||
- resets
|
||||
|
||||
|
||||
@@ -13,12 +13,14 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- rockchip,px30-usb2phy
|
||||
- rockchip,rk3036-usb2phy
|
||||
- rockchip,rk3128-usb2phy
|
||||
- rockchip,rk3228-usb2phy
|
||||
- rockchip,rk3308-usb2phy
|
||||
- rockchip,rk3328-usb2phy
|
||||
- rockchip,rk3366-usb2phy
|
||||
- rockchip,rk3399-usb2phy
|
||||
- rockchip,rk3562-usb2phy
|
||||
- rockchip,rk3568-usb2phy
|
||||
- rockchip,rk3576-usb2phy
|
||||
- rockchip,rk3588-usb2phy
|
||||
@@ -184,12 +186,14 @@ allOf:
|
||||
contains:
|
||||
enum:
|
||||
- rockchip,px30-usb2phy
|
||||
- rockchip,rk3036-usb2phy
|
||||
- rockchip,rk3128-usb2phy
|
||||
- rockchip,rk3228-usb2phy
|
||||
- rockchip,rk3308-usb2phy
|
||||
- rockchip,rk3328-usb2phy
|
||||
- rockchip,rk3366-usb2phy
|
||||
- rockchip,rk3399-usb2phy
|
||||
- rockchip,rk3562-usb2phy
|
||||
- rockchip,rk3568-usb2phy
|
||||
- rockchip,rk3588-usb2phy
|
||||
- rockchip,rv1108-usb2phy
|
||||
|
||||
@@ -46,6 +46,9 @@ properties:
|
||||
reset-names:
|
||||
const: phy
|
||||
|
||||
phy-supply:
|
||||
description: Single PHY regulator
|
||||
|
||||
rockchip,phy-grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description: phandle to the syscon managing the phy "general register files"
|
||||
|
||||
@@ -0,0 +1,45 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/rockchip,rk3399-pcie-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip RK3399 PCIE PHY
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: rockchip,rk3399-pcie-phy
|
||||
|
||||
'#phy-cells':
|
||||
oneOf:
|
||||
- const: 0
|
||||
deprecated: true
|
||||
- const: 1
|
||||
description: One lane per phy mode
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: refclk
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
reset-names:
|
||||
const: phy
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- '#phy-cells'
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
...
|
||||
@@ -0,0 +1,116 @@
|
||||
# SPDX-License-Identifier: GPL-2.0
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/rockchip,rk3399-typec-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Rockchip Type-C PHY
|
||||
|
||||
maintainers:
|
||||
- Heiko Stuebner <heiko@sntech.de>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
const: rockchip,rk3399-typec-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
clocks:
|
||||
maxItems: 2
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: tcpdcore
|
||||
- const: tcpdphy-ref
|
||||
|
||||
extcon: true
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
resets:
|
||||
maxItems: 3
|
||||
|
||||
reset-names:
|
||||
items:
|
||||
- const: uphy
|
||||
- const: uphy-pipe
|
||||
- const: uphy-tcphy
|
||||
|
||||
rockchip,grf:
|
||||
$ref: /schemas/types.yaml#/definitions/phandle
|
||||
description:
|
||||
Phandle to the syscon managing the "general register files" (GRF).
|
||||
|
||||
dp-port:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Connection to USB Type-C connector
|
||||
|
||||
required:
|
||||
- '#phy-cells'
|
||||
|
||||
usb3-port:
|
||||
type: object
|
||||
additionalProperties: false
|
||||
|
||||
properties:
|
||||
'#phy-cells':
|
||||
const: 0
|
||||
|
||||
orientation-switch: true
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description: Connection to USB Type-C connector SS port
|
||||
|
||||
required:
|
||||
- '#phy-cells'
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- resets
|
||||
- reset-names
|
||||
- dp-port
|
||||
- usb3-port
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/rk3399-cru.h>
|
||||
|
||||
phy@ff7c0000 {
|
||||
compatible = "rockchip,rk3399-typec-phy";
|
||||
reg = <0xff7c0000 0x40000>;
|
||||
rockchip,grf = <&grf>;
|
||||
extcon = <&fusb0>;
|
||||
clocks = <&cru SCLK_UPHY0_TCPDCORE>,
|
||||
<&cru SCLK_UPHY0_TCPDPHY_REF>;
|
||||
clock-names = "tcpdcore", "tcpdphy-ref";
|
||||
resets = <&cru SRST_UPHY0>,
|
||||
<&cru SRST_UPHY0_PIPE_L00>,
|
||||
<&cru SRST_P_UPHY0_TCPHY>;
|
||||
reset-names = "uphy", "uphy-pipe", "uphy-tcphy";
|
||||
|
||||
dp-port {
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
usb3-port {
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
};
|
||||
|
||||
...
|
||||
@@ -1,36 +0,0 @@
|
||||
Rockchip PCIE PHY
|
||||
-----------------------
|
||||
|
||||
Required properties:
|
||||
- compatible: rockchip,rk3399-pcie-phy
|
||||
- clocks: Must contain an entry in clock-names.
|
||||
See ../clocks/clock-bindings.txt for details.
|
||||
- clock-names: Must be "refclk"
|
||||
- resets: Must contain an entry in reset-names.
|
||||
See ../reset/reset.txt for details.
|
||||
- reset-names: Must be "phy"
|
||||
|
||||
Required properties for legacy PHY mode (deprecated):
|
||||
- #phy-cells: must be 0
|
||||
|
||||
Required properties for per-lane PHY mode (preferred):
|
||||
- #phy-cells: must be 1
|
||||
|
||||
Example:
|
||||
|
||||
grf: syscon@ff770000 {
|
||||
compatible = "rockchip,rk3399-grf", "syscon", "simple-mfd";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
|
||||
...
|
||||
|
||||
pcie_phy: pcie-phy {
|
||||
compatible = "rockchip,rk3399-pcie-phy";
|
||||
#phy-cells = <0>;
|
||||
clocks = <&cru SCLK_PCIEPHY_REF>;
|
||||
clock-names = "refclk";
|
||||
resets = <&cru SRST_PCIEPHY>;
|
||||
reset-names = "phy";
|
||||
};
|
||||
};
|
||||
@@ -0,0 +1,80 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/phy/samsung,exynos2200-eusb2-phy.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Samsung Exynos2200 eUSB2 phy controller
|
||||
|
||||
maintainers:
|
||||
- Ivaylo Ivanov <ivo.ivanov.ivanov1@gmail.com>
|
||||
|
||||
description:
|
||||
Samsung Exynos2200 eUSB2 phy, based on Synopsys eUSB2 IP block, supports
|
||||
LS/FS/HS usb connectivity.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- samsung,exynos2200-eusb2-phy
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
"#phy-cells":
|
||||
const: 0
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Reference clock
|
||||
- description: Bus (APB) clock
|
||||
- description: Control clock
|
||||
|
||||
clock-names:
|
||||
items:
|
||||
- const: ref
|
||||
- const: bus
|
||||
- const: ctrl
|
||||
|
||||
resets:
|
||||
maxItems: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
description:
|
||||
Phandle to eUSB2 to USB 2.0 repeater
|
||||
|
||||
vdd-supply:
|
||||
description:
|
||||
Phandle to 0.88V regulator supply to PHY digital circuit.
|
||||
|
||||
vdda12-supply:
|
||||
description:
|
||||
Phandle to 1.2V regulator supply to PHY refclk pll block.
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- "#phy-cells"
|
||||
- clocks
|
||||
- clock-names
|
||||
- vdd-supply
|
||||
- vdda12-supply
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
usb_hsphy: phy@10ab0000 {
|
||||
compatible = "samsung,exynos2200-eusb2-phy";
|
||||
reg = <0x10ab0000 0x10000>;
|
||||
#phy-cells = <0>;
|
||||
|
||||
clocks = <&cmu_hsi0 7>,
|
||||
<&cmu_hsi0 5>,
|
||||
<&cmu_hsi0 8>;
|
||||
clock-names = "ref", "bus", "ctrl";
|
||||
|
||||
vdd-supply = <&vreg_0p88>;
|
||||
vdda12-supply = <&vreg_1p2>;
|
||||
};
|
||||
@@ -26,31 +26,41 @@ properties:
|
||||
compatible:
|
||||
enum:
|
||||
- google,gs101-usb31drd-phy
|
||||
- samsung,exynos2200-usb32drd-phy
|
||||
- samsung,exynos5250-usbdrd-phy
|
||||
- samsung,exynos5420-usbdrd-phy
|
||||
- samsung,exynos5433-usbdrd-phy
|
||||
- samsung,exynos7-usbdrd-phy
|
||||
- samsung,exynos7870-usbdrd-phy
|
||||
- samsung,exynos850-usbdrd-phy
|
||||
|
||||
clocks:
|
||||
minItems: 2
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
|
||||
clock-names:
|
||||
minItems: 2
|
||||
minItems: 1
|
||||
maxItems: 5
|
||||
description: |
|
||||
At least two clocks::
|
||||
Typically two clocks:
|
||||
- Main PHY clock (same as USB DRD controller i.e. DWC3 IP clock), used
|
||||
for register access.
|
||||
- PHY reference clock (usually crystal clock), used for PHY operations,
|
||||
associated by phy name. It is used to determine bit values for clock
|
||||
settings register. For Exynos5420 this is given as 'sclk_usbphy30'
|
||||
in the CMU.
|
||||
in the CMU. It's not needed for Exynos2200.
|
||||
|
||||
"#phy-cells":
|
||||
const: 1
|
||||
|
||||
phys:
|
||||
maxItems: 1
|
||||
description:
|
||||
USBDRD-underlying high-speed PHY
|
||||
|
||||
phy-names:
|
||||
const: hs
|
||||
|
||||
port:
|
||||
$ref: /schemas/graph.yaml#/properties/port
|
||||
description:
|
||||
@@ -150,6 +160,27 @@ allOf:
|
||||
- vdda-usbdp-supply
|
||||
- vddh-usbdp-supply
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- samsung,exynos2200-usb32drd-phy
|
||||
then:
|
||||
properties:
|
||||
clocks:
|
||||
maxItems: 1
|
||||
clock-names:
|
||||
items:
|
||||
- const: phy
|
||||
reg:
|
||||
maxItems: 1
|
||||
reg-names:
|
||||
maxItems: 1
|
||||
required:
|
||||
- phys
|
||||
- phy-names
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
@@ -184,6 +215,7 @@ allOf:
|
||||
enum:
|
||||
- samsung,exynos5250-usbdrd-phy
|
||||
- samsung,exynos5420-usbdrd-phy
|
||||
- samsung,exynos7870-usbdrd-phy
|
||||
- samsung,exynos850-usbdrd-phy
|
||||
then:
|
||||
properties:
|
||||
|
||||
@@ -208,8 +208,8 @@ allOf:
|
||||
|
||||
pcie-phy:
|
||||
type: object
|
||||
description:
|
||||
Documentation/devicetree/bindings/phy/rockchip-pcie-phy.txt
|
||||
$ref: /schemas/phy/rockchip,rk3399-pcie-phy.yaml#
|
||||
unevaluatedProperties: false
|
||||
|
||||
patternProperties:
|
||||
"^phy@[0-9a-f]+$":
|
||||
@@ -333,6 +333,15 @@ examples:
|
||||
#phy-cells = <0>;
|
||||
};
|
||||
|
||||
pcie-phy {
|
||||
compatible = "rockchip,rk3399-pcie-phy";
|
||||
#phy-cells = <1>;
|
||||
clocks = <&cru SCLK_PCIEPHY_REF>;
|
||||
clock-names = "refclk";
|
||||
resets = <&cru SRST_PCIEPHY>;
|
||||
reset-names = "phy";
|
||||
};
|
||||
|
||||
phy@f780 {
|
||||
compatible = "rockchip,rk3399-emmc-phy";
|
||||
reg = <0xf780 0x20>;
|
||||
|
||||
@@ -18,7 +18,7 @@ description:
|
||||
Documentation/devicetree/bindings/phy/rockchip,inno-usb2phy.yaml
|
||||
|
||||
Type-C PHY
|
||||
Documentation/devicetree/bindings/phy/phy-rockchip-typec.txt
|
||||
Documentation/devicetree/bindings/phy/rockchip,rk3399-typec-phy.yaml
|
||||
|
||||
select:
|
||||
properties:
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user