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mfd: cs40l50: Add support for CS40L50 core driver
Introduce support for Cirrus Logic Device CS40L50: a haptic driver with waveform memory, integrated DSP, and closed-loop algorithms. The MFD component registers and initializes the device. Signed-off-by: James Ogletree <jogletre@opensource.cirrus.com> Reviewed-by: Jeff LaBundy <jeff@labundy.com> Link: https://lore.kernel.org/r/20240620161745.2312359-4-jogletre@opensource.cirrus.com Signed-off-by: Lee Jones <lee@kernel.org>
This commit is contained in:
James Ogletree
committed by
Lee Jones
Lee Jones
parent
2fab5abad1
commit
cb626376cb
@@ -5213,6 +5213,8 @@ M: Ben Bright <ben.bright@cirrus.com>
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L: patches@opensource.cirrus.com
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S: Supported
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F: Documentation/devicetree/bindings/input/cirrus,cs40l50.yaml
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F: drivers/mfd/cs40l*
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F: include/linux/mfd/cs40l*
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CIRRUS LOGIC DSP FIRMWARE DRIVER
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M: Simon Trimmer <simont@opensource.cirrus.com>
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@@ -2243,6 +2243,36 @@ config MCP_UCB1200_TS
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endmenu
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config MFD_CS40L50_CORE
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tristate
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select MFD_CORE
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select FW_CS_DSP
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select REGMAP_IRQ
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config MFD_CS40L50_I2C
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tristate "Cirrus Logic CS40L50 (I2C)"
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select REGMAP_I2C
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select MFD_CS40L50_CORE
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depends on I2C
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help
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Select this to support the Cirrus Logic CS40L50 Haptic
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Driver over I2C.
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This driver can be built as a module. If built as a module it will be
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called "cs40l50-i2c".
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config MFD_CS40L50_SPI
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tristate "Cirrus Logic CS40L50 (SPI)"
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select REGMAP_SPI
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select MFD_CS40L50_CORE
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depends on SPI
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help
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Select this to support the Cirrus Logic CS40L50 Haptic
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Driver over SPI.
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This driver can be built as a module. If built as a module it will be
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called "cs40l50-spi".
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config MFD_VEXPRESS_SYSREG
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tristate "Versatile Express System Registers"
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depends on VEXPRESS_CONFIG && GPIOLIB
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@@ -88,6 +88,10 @@ obj-$(CONFIG_MFD_MADERA) += madera.o
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obj-$(CONFIG_MFD_MADERA_I2C) += madera-i2c.o
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obj-$(CONFIG_MFD_MADERA_SPI) += madera-spi.o
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obj-$(CONFIG_MFD_CS40L50_CORE) += cs40l50-core.o
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obj-$(CONFIG_MFD_CS40L50_I2C) += cs40l50-i2c.o
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obj-$(CONFIG_MFD_CS40L50_SPI) += cs40l50-spi.o
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obj-$(CONFIG_TPS6105X) += tps6105x.o
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obj-$(CONFIG_TPS65010) += tps65010.o
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obj-$(CONFIG_TPS6507X) += tps6507x.o
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File diff suppressed because it is too large
Load Diff
@@ -0,0 +1,68 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* CS40L50 Advanced Haptic Driver with waveform memory,
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* integrated DSP, and closed-loop algorithms
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*
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* Copyright 2024 Cirrus Logic, Inc.
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*
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* Author: James Ogletree <james.ogletree@cirrus.com>
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*/
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#include <linux/i2c.h>
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#include <linux/mfd/cs40l50.h>
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static int cs40l50_i2c_probe(struct i2c_client *i2c)
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{
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struct cs40l50 *cs40l50;
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cs40l50 = devm_kzalloc(&i2c->dev, sizeof(*cs40l50), GFP_KERNEL);
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if (!cs40l50)
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return -ENOMEM;
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i2c_set_clientdata(i2c, cs40l50);
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cs40l50->dev = &i2c->dev;
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cs40l50->irq = i2c->irq;
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cs40l50->regmap = devm_regmap_init_i2c(i2c, &cs40l50_regmap);
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if (IS_ERR(cs40l50->regmap))
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return dev_err_probe(cs40l50->dev, PTR_ERR(cs40l50->regmap),
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"Failed to initialize register map\n");
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return cs40l50_probe(cs40l50);
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}
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static void cs40l50_i2c_remove(struct i2c_client *i2c)
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{
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struct cs40l50 *cs40l50 = i2c_get_clientdata(i2c);
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cs40l50_remove(cs40l50);
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}
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static const struct i2c_device_id cs40l50_id_i2c[] = {
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{ "cs40l50" },
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{}
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};
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MODULE_DEVICE_TABLE(i2c, cs40l50_id_i2c);
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static const struct of_device_id cs40l50_of_match[] = {
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{ .compatible = "cirrus,cs40l50" },
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{}
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};
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MODULE_DEVICE_TABLE(of, cs40l50_of_match);
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static struct i2c_driver cs40l50_i2c_driver = {
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.driver = {
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.name = "cs40l50",
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.of_match_table = cs40l50_of_match,
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.pm = pm_ptr(&cs40l50_pm_ops),
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},
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.id_table = cs40l50_id_i2c,
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.probe = cs40l50_i2c_probe,
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.remove = cs40l50_i2c_remove,
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};
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module_i2c_driver(cs40l50_i2c_driver);
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MODULE_DESCRIPTION("CS40L50 I2C Driver");
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MODULE_AUTHOR("James Ogletree, Cirrus Logic Inc. <james.ogletree@cirrus.com>");
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MODULE_LICENSE("GPL");
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@@ -0,0 +1,68 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* CS40L50 Advanced Haptic Driver with waveform memory,
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* integrated DSP, and closed-loop algorithms
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*
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* Copyright 2024 Cirrus Logic, Inc.
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*
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* Author: James Ogletree <james.ogletree@cirrus.com>
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*/
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#include <linux/mfd/cs40l50.h>
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#include <linux/spi/spi.h>
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static int cs40l50_spi_probe(struct spi_device *spi)
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{
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struct cs40l50 *cs40l50;
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cs40l50 = devm_kzalloc(&spi->dev, sizeof(*cs40l50), GFP_KERNEL);
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if (!cs40l50)
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return -ENOMEM;
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spi_set_drvdata(spi, cs40l50);
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cs40l50->dev = &spi->dev;
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cs40l50->irq = spi->irq;
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cs40l50->regmap = devm_regmap_init_spi(spi, &cs40l50_regmap);
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if (IS_ERR(cs40l50->regmap))
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return dev_err_probe(cs40l50->dev, PTR_ERR(cs40l50->regmap),
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"Failed to initialize register map\n");
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return cs40l50_probe(cs40l50);
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}
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static void cs40l50_spi_remove(struct spi_device *spi)
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{
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struct cs40l50 *cs40l50 = spi_get_drvdata(spi);
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cs40l50_remove(cs40l50);
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}
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static const struct spi_device_id cs40l50_id_spi[] = {
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{ "cs40l50" },
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{}
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};
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MODULE_DEVICE_TABLE(spi, cs40l50_id_spi);
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static const struct of_device_id cs40l50_of_match[] = {
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{ .compatible = "cirrus,cs40l50" },
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{}
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};
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MODULE_DEVICE_TABLE(of, cs40l50_of_match);
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static struct spi_driver cs40l50_spi_driver = {
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.driver = {
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.name = "cs40l50",
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.of_match_table = cs40l50_of_match,
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.pm = pm_ptr(&cs40l50_pm_ops),
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},
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.id_table = cs40l50_id_spi,
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.probe = cs40l50_spi_probe,
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.remove = cs40l50_spi_remove,
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};
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module_spi_driver(cs40l50_spi_driver);
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MODULE_DESCRIPTION("CS40L50 SPI Driver");
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MODULE_AUTHOR("James Ogletree, Cirrus Logic Inc. <james.ogletree@cirrus.com>");
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MODULE_LICENSE("GPL");
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@@ -0,0 +1,137 @@
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/* SPDX-License-Identifier: GPL-2.0
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*
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* CS40L50 Advanced Haptic Driver with waveform memory,
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* integrated DSP, and closed-loop algorithms
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*
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* Copyright 2024 Cirrus Logic, Inc.
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*
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* Author: James Ogletree <james.ogletree@cirrus.com>
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*/
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#ifndef __MFD_CS40L50_H__
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#define __MFD_CS40L50_H__
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#include <linux/firmware/cirrus/cs_dsp.h>
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#include <linux/gpio/consumer.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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/* Power Supply Configuration */
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#define CS40L50_BLOCK_ENABLES2 0x201C
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#define CS40L50_ERR_RLS 0x2034
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#define CS40L50_BST_LPMODE_SEL 0x3810
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#define CS40L50_DCM_LOW_POWER 0x1
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#define CS40L50_OVERTEMP_WARN 0x4000010
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/* Interrupts */
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#define CS40L50_IRQ1_INT_1 0xE010
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#define CS40L50_IRQ1_BASE CS40L50_IRQ1_INT_1
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#define CS40L50_IRQ1_INT_2 0xE014
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#define CS40L50_IRQ1_INT_8 0xE02C
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#define CS40L50_IRQ1_INT_9 0xE030
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#define CS40L50_IRQ1_INT_10 0xE034
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#define CS40L50_IRQ1_INT_18 0xE054
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#define CS40L50_IRQ1_MASK_1 0xE090
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#define CS40L50_IRQ1_MASK_2 0xE094
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#define CS40L50_IRQ1_MASK_20 0xE0DC
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#define CS40L50_IRQ1_INT_1_OFFSET (CS40L50_IRQ1_INT_1 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ1_INT_2_OFFSET (CS40L50_IRQ1_INT_2 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ1_INT_8_OFFSET (CS40L50_IRQ1_INT_8 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ1_INT_9_OFFSET (CS40L50_IRQ1_INT_9 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ1_INT_10_OFFSET (CS40L50_IRQ1_INT_10 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ1_INT_18_OFFSET (CS40L50_IRQ1_INT_18 - CS40L50_IRQ1_BASE)
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#define CS40L50_IRQ_MASK_2_OVERRIDE 0xFFDF7FFF
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#define CS40L50_IRQ_MASK_20_OVERRIDE 0x15C01000
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#define CS40L50_AMP_SHORT_MASK BIT(31)
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#define CS40L50_DSP_QUEUE_MASK BIT(21)
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#define CS40L50_TEMP_ERR_MASK BIT(31)
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#define CS40L50_BST_UVP_MASK BIT(6)
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#define CS40L50_BST_SHORT_MASK BIT(7)
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#define CS40L50_BST_ILIMIT_MASK BIT(18)
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#define CS40L50_UVLO_VDDBATT_MASK BIT(16)
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#define CS40L50_GLOBAL_ERROR_MASK BIT(15)
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enum cs40l50_irq_list {
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CS40L50_DSP_QUEUE_IRQ,
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CS40L50_GLOBAL_ERROR_IRQ,
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CS40L50_UVLO_VDDBATT_IRQ,
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CS40L50_BST_ILIMIT_IRQ,
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CS40L50_BST_SHORT_IRQ,
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CS40L50_BST_UVP_IRQ,
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CS40L50_TEMP_ERR_IRQ,
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CS40L50_AMP_SHORT_IRQ,
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};
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/* DSP */
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#define CS40L50_XMEM_PACKED_0 0x2000000
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#define CS40L50_XMEM_UNPACKED24_0 0x2800000
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#define CS40L50_SYS_INFO_ID 0x25E0000
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#define CS40L50_DSP_QUEUE_WT 0x28042C8
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#define CS40L50_DSP_QUEUE_RD 0x28042CC
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#define CS40L50_NUM_WAVES 0x2805C18
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#define CS40L50_CORE_BASE 0x2B80000
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#define CS40L50_YMEM_PACKED_0 0x2C00000
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#define CS40L50_YMEM_UNPACKED24_0 0x3400000
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#define CS40L50_PMEM_0 0x3800000
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#define CS40L50_DSP_POLL_US 1000
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#define CS40L50_DSP_TIMEOUT_COUNT 100
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#define CS40L50_RESET_PULSE_US 2200
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#define CS40L50_CP_READY_US 3100
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#define CS40L50_AUTOSUSPEND_MS 2000
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#define CS40L50_PM_ALGO 0x9F206
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#define CS40L50_GLOBAL_ERR_RLS_SET BIT(11)
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#define CS40L50_GLOBAL_ERR_RLS_CLEAR 0
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enum cs40l50_wseqs {
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CS40L50_PWR_ON,
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CS40L50_STANDBY,
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CS40L50_ACTIVE,
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CS40L50_NUM_WSEQS,
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};
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/* DSP Queue */
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#define CS40L50_DSP_QUEUE_BASE 0x11004
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#define CS40L50_DSP_QUEUE_END 0x1101C
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#define CS40L50_DSP_QUEUE 0x11020
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#define CS40L50_PREVENT_HIBER 0x2000003
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#define CS40L50_ALLOW_HIBER 0x2000004
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#define CS40L50_SHUTDOWN 0x2000005
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#define CS40L50_SYSTEM_RESET 0x2000007
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#define CS40L50_START_I2S 0x3000002
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#define CS40L50_OWT_PUSH 0x3000008
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#define CS40L50_STOP_PLAYBACK 0x5000000
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#define CS40L50_OWT_DELETE 0xD000000
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/* Firmware files */
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#define CS40L50_FW "cs40l50.wmfw"
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#define CS40L50_WT "cs40l50.bin"
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/* Device */
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#define CS40L50_DEVID 0x0
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#define CS40L50_REVID 0x4
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#define CS40L50_DEVID_A 0x40A50
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#define CS40L50_REVID_B0 0xB0
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struct cs40l50 {
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struct device *dev;
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struct regmap *regmap;
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struct mutex lock;
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struct cs_dsp dsp;
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struct gpio_desc *reset_gpio;
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struct regmap_irq_chip_data *irq_data;
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const struct firmware *fw;
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const struct firmware *bin;
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struct cs_dsp_wseq wseqs[CS40L50_NUM_WSEQS];
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int irq;
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u32 devid;
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u32 revid;
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};
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int cs40l50_dsp_write(struct device *dev, struct regmap *regmap, u32 val);
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int cs40l50_probe(struct cs40l50 *cs40l50);
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int cs40l50_remove(struct cs40l50 *cs40l50);
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extern const struct regmap_config cs40l50_regmap;
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extern const struct dev_pm_ops cs40l50_pm_ops;
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#endif /* __MFD_CS40L50_H__ */
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