mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'soc-drivers-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull SoC driver updates from Arnd Bergmann:
"There are are a number of to firmware drivers, in particular the TEE
subsystem:
- a bus callback for TEE firmware that device drivers can register to
- sysfs support for tee firmware information
- minor updates to platform specific TEE drivers for AMD, NXP,
Qualcomm and the generic optee driver
- ARM SCMI firmware refactoring to improve the protocol discover
among other fixes and cleanups
- ARM FF-A firmware interoperability improvements
The reset controller and memory controller subsystems gain support for
additional hardware platforms from Mediatek, Renesas, NXP, Canaan and
SpacemiT.
Most of the other changes are for random drivers/soc code. Among a
number of cleanups and newly added hardware support, including:
- Mediatek MT8196 DVFS power management and mailbox support
- Qualcomm SCM firmware and MDT loader refactoring, as part of the
new Glymur platform support.
- NXP i.MX9 System Manager firmware support for accessing the syslog
- Minor updates for TI, Renesas, Samsung, Apple, Marvell and AMD
SoCs"
* tag 'soc-drivers-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (171 commits)
bus: fsl-mc: fix an error handling in fsl_mc_device_add()
reset: spacemit: Add SpacemiT K3 reset driver
reset: spacemit: Extract common K1 reset code
reset: Create subdirectory for SpacemiT drivers
dt-bindings: soc: spacemit: Add K3 reset support and IDs
reset: canaan: k230: drop OF dependency and enable by default
reset: rzg2l-usbphy-ctrl: Add suspend/resume support
reset: rzg2l-usbphy-ctrl: Propagate the return value of regmap_field_update_bits()
reset: gpio: check the return value of gpiod_set_value_cansleep()
reset: imx8mp-audiomix: Support i.MX8ULP SIM LPAV
reset: imx8mp-audiomix: Extend the driver usage
reset: imx8mp-audiomix: Switch to using regmap API
reset: imx8mp-audiomix: Drop unneeded macros
soc: fsl: qe: qe_ports_ic: Consolidate chained IRQ handler install/remove
soc: mediatek: mtk-cmdq: Add mminfra_offset adjustment for DRAM addresses
soc: mediatek: mtk-cmdq: Extend cmdq_pkt_write API for SoCs without subsys ID
soc: mediatek: mtk-cmdq: Add pa_base parsing for hardware without subsys ID support
soc: mediatek: mtk-cmdq: Add cmdq_get_mbox_priv() in cmdq_pkt_create()
mailbox: mtk-cmdq: Add driver data to support for MT8196
mailbox: mtk-cmdq: Add mminfra_offset configuration for DRAM transaction
...
This commit is contained in:
Linus Torvalds
@@ -13,3 +13,13 @@ Description:
|
||||
space if the variable is absent. The primary purpose
|
||||
of this variable is to let systemd know whether
|
||||
tee-supplicant is needed in the early boot with initramfs.
|
||||
|
||||
What: /sys/class/tee/tee{,priv}X/revision
|
||||
Date: Jan 2026
|
||||
KernelVersion: 6.19
|
||||
Contact: op-tee@lists.trustedfirmware.org
|
||||
Description:
|
||||
Read-only revision string reported by the TEE driver. This is
|
||||
for diagnostics only and must not be used to infer feature
|
||||
support. Use TEE_IOC_VERSION for capability and compatibility
|
||||
checks.
|
||||
|
||||
+44
-2
@@ -20,6 +20,7 @@ description: |
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- qcom,glymur-llcc
|
||||
- qcom,ipq5424-llcc
|
||||
- qcom,kaanapali-llcc
|
||||
- qcom,qcs615-llcc
|
||||
@@ -46,11 +47,11 @@ properties:
|
||||
|
||||
reg:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
maxItems: 14
|
||||
|
||||
reg-names:
|
||||
minItems: 1
|
||||
maxItems: 10
|
||||
maxItems: 14
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
@@ -84,6 +85,47 @@ allOf:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- qcom,glymur-llcc
|
||||
then:
|
||||
properties:
|
||||
reg:
|
||||
items:
|
||||
- description: LLCC0 base register region
|
||||
- description: LLCC1 base register region
|
||||
- description: LLCC2 base register region
|
||||
- description: LLCC3 base register region
|
||||
- description: LLCC4 base register region
|
||||
- description: LLCC5 base register region
|
||||
- description: LLCC6 base register region
|
||||
- description: LLCC7 base register region
|
||||
- description: LLCC8 base register region
|
||||
- description: LLCC9 base register region
|
||||
- description: LLCC10 base register region
|
||||
- description: LLCC11 base register region
|
||||
- description: LLCC broadcast base register region
|
||||
- description: LLCC broadcast AND register region
|
||||
reg-names:
|
||||
items:
|
||||
- const: llcc0_base
|
||||
- const: llcc1_base
|
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- const: llcc2_base
|
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- const: llcc3_base
|
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- const: llcc4_base
|
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- const: llcc5_base
|
||||
- const: llcc6_base
|
||||
- const: llcc7_base
|
||||
- const: llcc8_base
|
||||
- const: llcc9_base
|
||||
- const: llcc10_base
|
||||
- const: llcc11_base
|
||||
- const: llcc_broadcast_base
|
||||
- const: llcc_broadcast_and_base
|
||||
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -21,6 +21,7 @@ properties:
|
||||
- qcom,ipq5424-trng
|
||||
- qcom,ipq9574-trng
|
||||
- qcom,kaanapali-trng
|
||||
- qcom,milos-trng
|
||||
- qcom,qcs615-trng
|
||||
- qcom,qcs8300-trng
|
||||
- qcom,sa8255p-trng
|
||||
|
||||
@@ -0,0 +1,51 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/interrupt-controller/fsl,qe-ports-ic.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
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title: Freescale QUICC Engine I/O Ports Interrupt Controller
|
||||
|
||||
maintainers:
|
||||
- Christophe Leroy (CS GROUP) <chleroy@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
enum:
|
||||
- fsl,mpc8323-qe-ports-ic
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
interrupt-controller: true
|
||||
|
||||
'#address-cells':
|
||||
const: 0
|
||||
|
||||
'#interrupt-cells':
|
||||
const: 1
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- interrupt-controller
|
||||
- '#address-cells'
|
||||
- '#interrupt-cells'
|
||||
- interrupts
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
interrupt-controller@c00 {
|
||||
compatible = "fsl,mpc8323-qe-ports-ic";
|
||||
reg = <0xc00 0x18>;
|
||||
interrupt-controller;
|
||||
#address-cells = <0>;
|
||||
#interrupt-cells = <1>;
|
||||
interrupts = <74 0x8>;
|
||||
interrupt-parent = <&ipic>;
|
||||
};
|
||||
@@ -27,6 +27,8 @@ properties:
|
||||
items:
|
||||
- enum:
|
||||
- qcom,glymur-pdc
|
||||
- qcom,kaanapali-pdc
|
||||
- qcom,milos-pdc
|
||||
- qcom,qcs615-pdc
|
||||
- qcom,qcs8300-pdc
|
||||
- qcom,qdu1000-pdc
|
||||
|
||||
@@ -0,0 +1,34 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,ddr4.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: DDR4 SDRAM compliant to JEDEC JESD79-4D
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: jedec,sdram-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- pattern: "^ddr4-[0-9a-f]{4},[a-z]{1,20}-[0-9a-f]{2}$"
|
||||
- const: jedec,ddr4
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- density
|
||||
- io-width
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
ddr {
|
||||
compatible = "ddr4-00ff,azaz-ff", "jedec,ddr4";
|
||||
density = <8192>;
|
||||
io-width = <8>;
|
||||
};
|
||||
@@ -1,74 +0,0 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-props.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Common properties for LPDDR types
|
||||
|
||||
description:
|
||||
Different LPDDR types generally use the same properties and only differ in the
|
||||
range of legal values for each. This file defines the common parts that can be
|
||||
reused for each type. Nodes using this schema should generally be nested under
|
||||
an LPDDR channel node.
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description:
|
||||
Compatible strings can be either explicit vendor names and part numbers
|
||||
(e.g. elpida,ECB240ABACN), or generated strings of the form
|
||||
lpddrX-YY,ZZZZ where X is the LPDDR version, YY is the manufacturer ID
|
||||
(from MR5) and ZZZZ is the revision ID (from MR6 and MR7). Both IDs are
|
||||
formatted in lower case hexadecimal representation with leading zeroes.
|
||||
The latter form can be useful when LPDDR nodes are created at runtime by
|
||||
boot firmware that doesn't have access to static part number information.
|
||||
|
||||
reg:
|
||||
description:
|
||||
The rank number of this LPDDR rank when used as a subnode to an LPDDR
|
||||
channel.
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
revision-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description:
|
||||
Revision IDs read from Mode Register 6 and 7. One byte per uint32 cell (i.e. <MR6 MR7>).
|
||||
maxItems: 2
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
|
||||
density:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
Density in megabits of SDRAM chip. Decoded from Mode Register 8.
|
||||
enum:
|
||||
- 64
|
||||
- 128
|
||||
- 256
|
||||
- 512
|
||||
- 1024
|
||||
- 2048
|
||||
- 3072
|
||||
- 4096
|
||||
- 6144
|
||||
- 8192
|
||||
- 12288
|
||||
- 16384
|
||||
- 24576
|
||||
- 32768
|
||||
|
||||
io-width:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description:
|
||||
IO bus width in bits of SDRAM chip. Decoded from Mode Register 8.
|
||||
enum:
|
||||
- 8
|
||||
- 16
|
||||
- 32
|
||||
|
||||
additionalProperties: true
|
||||
@@ -10,7 +10,7 @@ maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: jedec,lpddr-props.yaml#
|
||||
- $ref: jedec,sdram-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -10,7 +10,7 @@ maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: jedec,lpddr-props.yaml#
|
||||
- $ref: jedec,sdram-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -10,7 +10,7 @@ maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: jedec,lpddr-props.yaml#
|
||||
- $ref: jedec,sdram-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
@@ -10,7 +10,7 @@ maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
allOf:
|
||||
- $ref: jedec,lpddr-props.yaml#
|
||||
- $ref: jedec,sdram-props.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
|
||||
+27
-13
@@ -1,23 +1,28 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,lpddr-channel.yaml#
|
||||
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-channel.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: LPDDR channel with chip/rank topology description
|
||||
title: SDRAM channel with chip/rank topology description
|
||||
|
||||
description:
|
||||
An LPDDR channel is a completely independent set of LPDDR pins (DQ, CA, CS,
|
||||
CK, etc.) that connect one or more LPDDR chips to a host system. The main
|
||||
purpose of this node is to overall LPDDR topology of the system, including the
|
||||
amount of individual LPDDR chips and the ranks per chip.
|
||||
A memory channel of SDRAM memory like DDR SDRAM or LPDDR SDRAM is a completely
|
||||
independent set of pins (DQ, CA, CS, CK, etc.) that connect one or more memory
|
||||
chips to a host system. The main purpose of this node is to overall memory
|
||||
topology of the system, including the amount of individual memory chips and
|
||||
the ranks per chip.
|
||||
|
||||
maintainers:
|
||||
- Julius Werner <jwerner@chromium.org>
|
||||
|
||||
properties:
|
||||
$nodename:
|
||||
pattern: "sdram-channel-[0-9]+$"
|
||||
|
||||
compatible:
|
||||
enum:
|
||||
- jedec,ddr4-channel
|
||||
- jedec,lpddr2-channel
|
||||
- jedec,lpddr3-channel
|
||||
- jedec,lpddr4-channel
|
||||
@@ -26,14 +31,14 @@ properties:
|
||||
io-width:
|
||||
description:
|
||||
The number of DQ pins in the channel. If this number is different
|
||||
from (a multiple of) the io-width of the LPDDR chip, that means that
|
||||
from (a multiple of) the io-width of the SDRAM chip, that means that
|
||||
multiple instances of that type of chip are wired in parallel on this
|
||||
channel (with the channel's DQ pins split up between the different
|
||||
chips, and the CA, CS, etc. pins of the different chips all shorted
|
||||
together). This means that the total physical memory controlled by a
|
||||
channel is equal to the sum of the densities of each rank on the
|
||||
connected LPDDR chip, times the io-width of the channel divided by
|
||||
the io-width of the LPDDR chip.
|
||||
connected SDRAM chip, times the io-width of the channel divided by
|
||||
the io-width of the SDRAM chip.
|
||||
enum:
|
||||
- 8
|
||||
- 16
|
||||
@@ -51,8 +56,8 @@ patternProperties:
|
||||
"^rank@[0-9]+$":
|
||||
type: object
|
||||
description:
|
||||
Each physical LPDDR chip may have one or more ranks. Ranks are
|
||||
internal but fully independent sub-units of the chip. Each LPDDR bus
|
||||
Each physical SDRAM chip may have one or more ranks. Ranks are
|
||||
internal but fully independent sub-units of the chip. Each SDRAM bus
|
||||
transaction on the channel targets exactly one rank, based on the
|
||||
state of the CS pins. Different ranks may have different densities and
|
||||
timing requirements.
|
||||
@@ -60,6 +65,15 @@ patternProperties:
|
||||
- reg
|
||||
|
||||
allOf:
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
const: jedec,ddr4-channel
|
||||
then:
|
||||
patternProperties:
|
||||
"^rank@[0-9]+$":
|
||||
$ref: /schemas/memory-controllers/ddr/jedec,ddr4.yaml#
|
||||
- if:
|
||||
properties:
|
||||
compatible:
|
||||
@@ -107,7 +121,7 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
lpddr-channel0 {
|
||||
sdram-channel-0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "jedec,lpddr3-channel";
|
||||
@@ -122,7 +136,7 @@ examples:
|
||||
};
|
||||
};
|
||||
|
||||
lpddr-channel1 {
|
||||
sdram-channel-1 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
compatible = "jedec,lpddr4-channel";
|
||||
@@ -0,0 +1,94 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/memory-controllers/ddr/jedec,sdram-props.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Common properties for SDRAM types
|
||||
|
||||
description:
|
||||
Different SDRAM types generally use the same properties and only differ in the
|
||||
range of legal values for each. This file defines the common parts that can be
|
||||
reused for each type. Nodes using this schema should generally be nested under
|
||||
a SDRAM channel node.
|
||||
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
description: |
|
||||
Compatible strings can be either explicit vendor names and part numbers
|
||||
(e.g. elpida,ECB240ABACN), or generated strings of the form
|
||||
lpddrX-YY,ZZZZ or ddrX-YYYY,AAAA...-ZZ where X, Y, and Z are lowercase
|
||||
hexadecimal with leading zeroes, and A is lowercase ASCII.
|
||||
For LPDDR and DDR SDRAM, X is the SDRAM version (2, 3, 4, etc.).
|
||||
For LPDDR SDRAM:
|
||||
- YY is the manufacturer ID (from MR5), 1 byte
|
||||
- ZZZZ is the revision ID (from MR6 and MR7), 2 bytes
|
||||
For DDR4 SDRAM with SPD, according to JEDEC SPD4.1.2.L-6:
|
||||
- YYYY is the manufacturer ID, 2 bytes, from bytes 320 and 321
|
||||
- AAAA... is the part number, 20 bytes (20 chars) from bytes 329 to 348
|
||||
without trailing spaces
|
||||
- ZZ is the revision ID, 1 byte, from byte 349
|
||||
The former form is useful when the SDRAM vendor and part number are
|
||||
known, for example, when memory is soldered on the board. The latter
|
||||
form is useful when SDRAM nodes are created at runtime by boot firmware
|
||||
that doesn't have access to static part number information.
|
||||
|
||||
reg:
|
||||
description:
|
||||
The rank number of this memory rank when used as a subnode to an memory
|
||||
channel.
|
||||
minimum: 0
|
||||
maximum: 3
|
||||
|
||||
revision-id:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32-array
|
||||
description: |
|
||||
SDRAM revision ID:
|
||||
- LPDDR SDRAM, decoded from Mode Registers 6 and 7, always 2 bytes.
|
||||
- DDR4 SDRAM, decoded from the SPD from byte 349 according to
|
||||
JEDEC SPD4.1.2.L-6, always 1 byte.
|
||||
One byte per uint32 cell (e.g., <MR6 MR7>).
|
||||
maxItems: 2
|
||||
items:
|
||||
minimum: 0
|
||||
maximum: 255
|
||||
|
||||
density:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
Density of the SDRAM chip in megabits:
|
||||
- LPDDR SDRAM, decoded from Mode Register 8.
|
||||
- DDR4 SDRAM, decoded from the SPD from bits 3-0 of byte 4 according to
|
||||
JEDEC SPD4.1.2.L-6.
|
||||
enum:
|
||||
- 64
|
||||
- 128
|
||||
- 256
|
||||
- 512
|
||||
- 1024
|
||||
- 2048
|
||||
- 3072
|
||||
- 4096
|
||||
- 6144
|
||||
- 8192
|
||||
- 12288
|
||||
- 16384
|
||||
- 24576
|
||||
- 32768
|
||||
|
||||
io-width:
|
||||
$ref: /schemas/types.yaml#/definitions/uint32
|
||||
description: |
|
||||
I/O bus width in bits of the SDRAM chip:
|
||||
- LPDDR SDRAM, decoded from Mode Register 8.
|
||||
- DDR4 SDRAM, decoded from the SPD from bits 2-0 of byte 12 according to
|
||||
JEDEC SPD4.1.2.L-6.
|
||||
enum:
|
||||
- 8
|
||||
- 16
|
||||
- 32
|
||||
|
||||
additionalProperties: true
|
||||
@@ -0,0 +1,61 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/nvmem/google,gs101-otp.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: Google GS101 OTP Controller
|
||||
|
||||
maintainers:
|
||||
- Tudor Ambarus <tudor.ambarus@linaro.org>
|
||||
|
||||
description: |
|
||||
OTP controller drives a NVMEM memory where system or user specific data
|
||||
can be stored. The OTP controller register space is of interest as well
|
||||
because it contains dedicated registers where it stores the Product ID
|
||||
and the Chip ID (apart other things like TMU or ASV info).
|
||||
|
||||
allOf:
|
||||
- $ref: nvmem.yaml#
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- const: google,gs101-otp
|
||||
|
||||
clocks:
|
||||
maxItems: 1
|
||||
|
||||
clock-names:
|
||||
const: pclk
|
||||
|
||||
interrupts:
|
||||
maxItems: 1
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
maxItems: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- clocks
|
||||
- clock-names
|
||||
- interrupts
|
||||
|
||||
unevaluatedProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/google,gs101.h>
|
||||
#include <dt-bindings/interrupt-controller/arm-gic.h>
|
||||
|
||||
efuse@10000000 {
|
||||
compatible = "google,gs101-otp";
|
||||
reg = <0x10000000 0xf084>;
|
||||
clocks = <&cmu_misc CLK_GOUT_MISC_OTP_CON_TOP_PCLK>;
|
||||
clock-names = "pclk";
|
||||
interrupts = <GIC_SPI 752 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
@@ -44,6 +44,9 @@ properties:
|
||||
- const: stop-ack
|
||||
- const: shutdown-ack
|
||||
|
||||
iommus:
|
||||
maxItems: 1
|
||||
|
||||
power-domains:
|
||||
minItems: 1
|
||||
maxItems: 3
|
||||
|
||||
@@ -34,6 +34,10 @@ properties:
|
||||
maxItems: 1
|
||||
description: DVFSRC common register address and length.
|
||||
|
||||
clocks:
|
||||
items:
|
||||
- description: Clock that drives the DVFSRC MCU
|
||||
|
||||
regulators:
|
||||
type: object
|
||||
$ref: /schemas/regulator/mediatek,mt6873-dvfsrc-regulator.yaml#
|
||||
@@ -50,6 +54,7 @@ additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
#include <dt-bindings/clock/mt8195-clk.h>
|
||||
soc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
@@ -57,6 +62,7 @@ examples:
|
||||
system-controller@10012000 {
|
||||
compatible = "mediatek,mt8195-dvfsrc";
|
||||
reg = <0 0x10012000 0 0x1000>;
|
||||
clocks = <&topckgen CLK_TOP_DVFSRC>;
|
||||
|
||||
regulators {
|
||||
compatible = "mediatek,mt8195-dvfsrc-regulator";
|
||||
|
||||
@@ -9,28 +9,6 @@ title: Samsung Exynos SoC series Power Management Unit (PMU)
|
||||
maintainers:
|
||||
- Krzysztof Kozlowski <krzk@kernel.org>
|
||||
|
||||
# Custom select to avoid matching all nodes with 'syscon'
|
||||
select:
|
||||
properties:
|
||||
compatible:
|
||||
contains:
|
||||
enum:
|
||||
- google,gs101-pmu
|
||||
- samsung,exynos3250-pmu
|
||||
- samsung,exynos4210-pmu
|
||||
- samsung,exynos4212-pmu
|
||||
- samsung,exynos4412-pmu
|
||||
- samsung,exynos5250-pmu
|
||||
- samsung,exynos5260-pmu
|
||||
- samsung,exynos5410-pmu
|
||||
- samsung,exynos5420-pmu
|
||||
- samsung,exynos5433-pmu
|
||||
- samsung,exynos7-pmu
|
||||
- samsung,exynos850-pmu
|
||||
- samsung-s5pv210-pmu
|
||||
required:
|
||||
- compatible
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
oneOf:
|
||||
@@ -52,6 +30,7 @@ properties:
|
||||
- const: syscon
|
||||
- items:
|
||||
- enum:
|
||||
- axis,artpec9-pmu
|
||||
- samsung,exynos2200-pmu
|
||||
- samsung,exynos7870-pmu
|
||||
- samsung,exynos7885-pmu
|
||||
|
||||
@@ -10,7 +10,7 @@ maintainers:
|
||||
- Haylen Chu <heylenay@4d2.org>
|
||||
|
||||
description:
|
||||
System controllers found on SpacemiT K1 SoC, which are capable of
|
||||
System controllers found on SpacemiT K1/K3 SoC, which are capable of
|
||||
clock, reset and power-management functions.
|
||||
|
||||
properties:
|
||||
@@ -46,6 +46,12 @@ properties:
|
||||
|
||||
"#reset-cells":
|
||||
const: 1
|
||||
description: |
|
||||
ID of the reset controller line. Valid IDs are defined in corresponding
|
||||
files:
|
||||
|
||||
For SpacemiT K1, see include/dt-bindings/clock/spacemit,k1-syscon.h
|
||||
For SpacemiT K3, see include/dt-bindings/reset/spacemit,k3-resets.h
|
||||
|
||||
required:
|
||||
- compatible
|
||||
|
||||
@@ -34,6 +34,7 @@ properties:
|
||||
- nvidia,tegra186-sysram
|
||||
- nvidia,tegra194-sysram
|
||||
- nvidia,tegra234-sysram
|
||||
- qcom,kaanapali-imem
|
||||
- qcom,rpm-msg-ram
|
||||
- rockchip,rk3288-pmu-sram
|
||||
|
||||
@@ -89,6 +90,7 @@ patternProperties:
|
||||
- arm,juno-scp-shmem
|
||||
- arm,scmi-shmem
|
||||
- arm,scp-shmem
|
||||
- qcom,pil-reloc-info
|
||||
- renesas,smp-sram
|
||||
- rockchip,rk3066-smp-sram
|
||||
- samsung,exynos4210-sysram
|
||||
|
||||
@@ -43,24 +43,12 @@ snippet would look like::
|
||||
MODULE_DEVICE_TABLE(tee, client_id_table);
|
||||
|
||||
static struct tee_client_driver client_driver = {
|
||||
.probe = client_probe,
|
||||
.remove = client_remove,
|
||||
.id_table = client_id_table,
|
||||
.driver = {
|
||||
.name = DRIVER_NAME,
|
||||
.bus = &tee_bus_type,
|
||||
.probe = client_probe,
|
||||
.remove = client_remove,
|
||||
},
|
||||
};
|
||||
|
||||
static int __init client_init(void)
|
||||
{
|
||||
return driver_register(&client_driver.driver);
|
||||
}
|
||||
|
||||
static void __exit client_exit(void)
|
||||
{
|
||||
driver_unregister(&client_driver.driver);
|
||||
}
|
||||
|
||||
module_init(client_init);
|
||||
module_exit(client_exit);
|
||||
module_tee_client_driver(client_driver);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user