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ARM: Xilinx: Adding Xilinx board support

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The 1st board support is minimal to get a system up and running
on the Xilinx platform.

This platform reuses the clock implementation from plat-versatile, and
it depends entirely on CONFIG_OF support.  There is only one board
support file which obtains all device information from a device tree
dtb file which is passed to the kernel at boot time.

Signed-off-by: John Linn <john.linn@xilinx.com>
This commit is contained in:
John Linn
2011-06-20 11:52:30 -06:00
parent 2c53b436a3
commit b85a3ef4ac
24 changed files with 938 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files
Documentation/devicetree/bindings/arm/xilinx.txt
+7
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@@ -0,0 +1,7 @@
Xilinx Zynq EP107 Emulation Platform board
This board is an emulation platform for the Zynq product which is
based on an ARM Cortex A9 processor.
Required root node properties:
- compatible = "xlnx,zynq-ep107";
arch/arm/Kconfig
+14
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@@ -879,6 +879,20 @@ config ARCH_VT8500
select HAVE_PWM
help
Support for VIA/WonderMedia VT8500/WM85xx System-on-Chip.
config ARCH_ZYNQ
bool "Xilinx Zynq ARM Cortex A9 Platform"
select CPU_V7
select GENERIC_TIME
select GENERIC_CLOCKEVENTS
select CLKDEV_LOOKUP
select ARM_GIC
select ARM_AMBA
select ICST
select USE_OF
help
Support for Xilinx Zynq ARM Cortex A9 Platform
endchoice
#
arch/arm/Makefile
+2
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@@ -196,6 +196,7 @@ machine-$(CONFIG_MACH_SPEAR300) := spear3xx
machine-$(CONFIG_MACH_SPEAR310) := spear3xx
machine-$(CONFIG_MACH_SPEAR320) := spear3xx
machine-$(CONFIG_MACH_SPEAR600) := spear6xx
machine-$(CONFIG_ARCH_ZYNQ) := zynq
# Platform directory name. This list is sorted alphanumerically
# by CONFIG_* macro name.
@@ -203,6 +204,7 @@ plat-$(CONFIG_ARCH_MXC) := mxc
plat-$(CONFIG_ARCH_OMAP) := omap
plat-$(CONFIG_ARCH_S3C64XX) := samsung
plat-$(CONFIG_ARCH_TCC_926) := tcc
plat-$(CONFIG_ARCH_ZYNQ) := versatile
plat-$(CONFIG_PLAT_IOP) := iop
plat-$(CONFIG_PLAT_NOMADIK) := nomadik
plat-$(CONFIG_PLAT_ORION) := orion
arch/arm/boot/dts/zynq-ep107.dts
+52
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@@ -0,0 +1,52 @@
/*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/dts-v1/;
/ {
model = "Xilinx Zynq EP107";
compatible = "xlnx,zynq-ep107";
#address-cells = <1>;
#size-cells = <1>;
interrupt-parent = <&intc>;
memory {
device_type = "memory";
reg = <0x0 0x10000000>;
};
chosen {
bootargs = "console=ttyPS0,9600 root=/dev/ram rw initrd=0x800000,8M earlyprintk";
linux,stdout-path = &uart0;
};
amba {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges;
intc: interrupt-controller@f8f01000 {
interrupt-controller;
compatible = "arm,gic";
reg = <0xF8F01000 0x1000>;
#interrupt-cells = <2>;
};
uart0: uart@e0000000 {
compatible = "xlnx,xuartps";
reg = <0xE0000000 0x1000>;
interrupts = <59 0>;
clock = <50000000>;
};
};
};
arch/arm/mach-zynq/Makefile
+6
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@@ -0,0 +1,6 @@
#
# Makefile for the linux kernel.
#
# Common support
obj-y := common.o timer.o board_dt.o
arch/arm/mach-zynq/Makefile.boot
+3
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@@ -0,0 +1,3 @@
zreladdr-y := 0x00008000
params_phys-y := 0x00000100
initrd_phys-y := 0x00800000
arch/arm/mach-zynq/board_dt.c
+37
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@@ -0,0 +1,37 @@
/*
* This file contains code for boards with device tree support.
*
* Copyright (C) 2011 Xilinx
*
* based on arch/arm/mach-realview/core.c
*
* Copyright (C) 1999 - 2003 ARM Limited
* Copyright (C) 2000 Deep Blue Solutions Ltd
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/of.h>
#include <asm/mach/arch.h>
#include <asm/mach-types.h>
#include "common.h"
static const char *xilinx_dt_match[] = {
"xlnx,zynq-ep107",
NULL
};
MACHINE_START(XILINX_EP107, "Xilinx Zynq Platform")
.map_io = xilinx_map_io,
.init_irq = xilinx_irq_init,
.init_machine = xilinx_init_machine,
.timer = &xttcpss_sys_timer,
.dt_compat = xilinx_dt_match,
MACHINE_END
arch/arm/mach-zynq/common.c
+102
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@@ -0,0 +1,102 @@
/*
* This file contains common code that is intended to be used across
* boards so that it's not replicated.
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <linux/init.h>
#include <linux/kernel.h>
#include <linux/cpumask.h>
#include <linux/platform_device.h>
#include <linux/clk.h>
#include <linux/of_irq.h>
#include <linux/of_platform.h>
#include <asm/mach/map.h>
#include <asm/page.h>
#include <asm/hardware/gic.h>
#include <asm/hardware/cache-l2x0.h>
#include <mach/zynq_soc.h>
#include <mach/clkdev.h>
#include "common.h"
static struct of_device_id zynq_of_bus_ids[] __initdata = {
{ .compatible = "simple-bus", },
{}
};
/**
* xilinx_init_machine() - System specific initialization, intended to be
* called from board specific initialization.
*/
void __init xilinx_init_machine(void)
{
#ifdef CONFIG_CACHE_L2X0
/*
* 64KB way size, 8-way associativity, parity disabled
*/
l2x0_init(PL310_L2CC_BASE, 0x02060000, 0xF0F0FFFF);
#endif
of_platform_bus_probe(NULL, zynq_of_bus_ids, NULL);
}
/**
* xilinx_irq_init() - Interrupt controller initialization for the GIC.
*/
void __init xilinx_irq_init(void)
{
gic_init(0, 29, SCU_GIC_DIST_BASE, SCU_GIC_CPU_BASE);
}
/* The minimum devices needed to be mapped before the VM system is up and
* running include the GIC, UART and Timer Counter.
*/
static struct map_desc io_desc[] __initdata = {
{
.virtual = TTC0_VIRT,
.pfn = __phys_to_pfn(TTC0_PHYS),
.length = SZ_4K,
.type = MT_DEVICE,
}, {
.virtual = SCU_PERIPH_VIRT,
.pfn = __phys_to_pfn(SCU_PERIPH_PHYS),
.length = SZ_8K,
.type = MT_DEVICE,
}, {
.virtual = PL310_L2CC_VIRT,
.pfn = __phys_to_pfn(PL310_L2CC_PHYS),
.length = SZ_4K,
.type = MT_DEVICE,
},
#ifdef CONFIG_DEBUG_LL
{
.virtual = UART0_VIRT,
.pfn = __phys_to_pfn(UART0_PHYS),
.length = SZ_4K,
.type = MT_DEVICE,
},
#endif
};
/**
* xilinx_map_io() - Create memory mappings needed for early I/O.
*/
void __init xilinx_map_io(void)
{
iotable_init(io_desc, ARRAY_SIZE(io_desc));
}
arch/arm/mach-zynq/common.h
+29
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@@ -0,0 +1,29 @@
/*
* This file contains common function prototypes to avoid externs
* in the c files.
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_ZYNQ_COMMON_H__
#define __MACH_ZYNQ_COMMON_H__
#include <linux/init.h>
#include <asm/mach/time.h>
extern void xilinx_init_machine(void);
extern void xilinx_irq_init(void);
extern void xilinx_map_io(void);
extern struct sys_timer xttcpss_sys_timer;
#endif
arch/arm/mach-zynq/include/mach/clkdev.h
+32
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@@ -0,0 +1,32 @@
/*
* arch/arm/mach-zynq/include/mach/clkdev.h
*
* Copyright (C) 2011 Xilinx, Inc.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#ifndef __MACH_CLKDEV_H__
#define __MACH_CLKDEV_H__
#include <plat/clock.h>
struct clk {
unsigned long rate;
const struct clk_ops *ops;
const struct icst_params *params;
void __iomem *vcoreg;
};
#define __clk_get(clk) ({ 1; })
#define __clk_put(clk) do { } while (0)
#endif
arch/arm/mach-zynq/include/mach/debug-macro.S
+36
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@@ -0,0 +1,36 @@
/* arch/arm/mach-zynq/include/mach/debug-macro.S
*
* Debugging macro include header
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <mach/zynq_soc.h>
#include <mach/uart.h>
.macro addruart, rp, rv
ldr \rp, =LL_UART_PADDR @ physical
ldr \rv, =LL_UART_VADDR @ virtual
.endm
.macro senduart,rd,rx
str \rd, [\rx, #UART_FIFO_OFFSET] @ TXDATA
.endm
.macro waituart,rd,rx
.endm
.macro busyuart,rd,rx
1002: ldr \rd, [\rx, #UART_SR_OFFSET] @ get status register
tst \rd, #UART_SR_TXFULL @
bne 1002b @ wait if FIFO is full
.endm
arch/arm/mach-zynq/include/mach/entry-macro.S
+30
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@@ -0,0 +1,30 @@
/*
* arch/arm/mach-zynq/include/mach/entry-macro.S
*
* Low-level IRQ helper macros
*
* Copyright (C) 2011 Xilinx
*
* based on arch/plat-mxc/include/mach/entry-macro.S
*
* Copyright (C) 2007 Lennert Buytenhek <buytenh@wantstofly.org>
* Copyright 2004-2007 Freescale Semiconductor, Inc. All Rights Reserved.
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <mach/hardware.h>
#include <asm/hardware/entry-macro-gic.S>
.macro disable_fiq
.endm
.macro arch_ret_to_user, tmp1, tmp2
.endm
arch/arm/mach-zynq/include/mach/hardware.h
+18
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@@ -0,0 +1,18 @@
/* arch/arm/mach-zynq/include/mach/hardware.h
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_HARDWARE_H__
#define __MACH_HARDWARE_H__
#endif
arch/arm/mach-zynq/include/mach/io.h
+33
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@@ -0,0 +1,33 @@
/* arch/arm/mach-zynq/include/mach/io.h
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_IO_H__
#define __MACH_IO_H__
/* Allow IO space to be anywhere in the memory */
#define IO_SPACE_LIMIT 0xffff
/* IO address mapping macros, nothing special at this time but required */
#ifdef __ASSEMBLER__
#define IOMEM(x) (x)
#else
#define IOMEM(x) ((void __force __iomem *)(x))
#endif
#define __io(a) __typesafe_io(a)
#define __mem_pci(a) (a)
#endif
arch/arm/mach-zynq/include/mach/irqs.h
+21
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@@ -0,0 +1,21 @@
/* arch/arm/mach-zynq/include/mach/irqs.h
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_IRQS_H
#define __MACH_IRQS_H
#define ARCH_NR_GPIOS 118
#define NR_IRQS (128 + ARCH_NR_GPIOS)
#endif
arch/arm/mach-zynq/include/mach/memory.h
+22
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@@ -0,0 +1,22 @@
/* arch/arm/mach-zynq/include/mach/memory.h
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_MEMORY_H__
#define __MACH_MEMORY_H__
#include <asm/sizes.h>
#define PLAT_PHYS_OFFSET UL(0x0)
#endif
arch/arm/mach-zynq/include/mach/system.h
+28
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@@ -0,0 +1,28 @@
/* arch/arm/mach-zynq/include/mach/system.h
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_SYSTEM_H__
#define __MACH_SYSTEM_H__
static inline void arch_idle(void)
{
cpu_do_idle();
}
static inline void arch_reset(char mode, const char *cmd)
{
/* Add architecture specific reset processing here */
}
#endif
arch/arm/mach-zynq/include/mach/timex.h
+23
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@@ -0,0 +1,23 @@
/* arch/arm/mach-zynq/include/mach/timex.h
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_TIMEX_H__
#define __MACH_TIMEX_H__
/* the following is needed for the system to build but will be removed
in the future, the value is not important but won't hurt
*/
#define CLOCK_TICK_RATE (100 * HZ)
#endif
arch/arm/mach-zynq/include/mach/uart.h
+25
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@@ -0,0 +1,25 @@
/* arch/arm/mach-zynq/include/mach/uart.h
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_UART_H__
#define __MACH_UART_H__
#define UART_CR_OFFSET 0x00 /* Control Register [8:0] */
#define UART_SR_OFFSET 0x2C /* Channel Status [11:0] */
#define UART_FIFO_OFFSET 0x30 /* FIFO [15:0] or [7:0] */
#define UART_SR_TXFULL 0x00000010 /* TX FIFO full */
#define UART_SR_TXEMPTY 0x00000008 /* TX FIFO empty */
#endif
arch/arm/mach-zynq/include/mach/uncompress.h
+51
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@@ -0,0 +1,51 @@
/* arch/arm/mach-zynq/include/mach/uncompress.h
*
* Copyright (C) 2011 Xilinx
*
* This software is licensed under the terms of the GNU General Public
* License version 2, as published by the Free Software Foundation, and
* may be copied, distributed, and modified under those terms.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __MACH_UNCOMPRESS_H__
#define __MACH_UNCOMPRESS_H__
#include <linux/io.h>
#include <asm/processor.h>
#include <mach/zynq_soc.h>
#include <mach/uart.h>
void arch_decomp_setup(void)
{
}
static inline void flush(void)
{
/*
* Wait while the FIFO is not empty
*/
while (!(__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) &
UART_SR_TXEMPTY))
cpu_relax();
}
#define arch_decomp_wdog()
static void putc(char ch)
{
/*
* Wait for room in the FIFO, then write the char into the FIFO
*/
while (__raw_readl(IOMEM(LL_UART_PADDR + UART_SR_OFFSET)) &
UART_SR_TXFULL)
cpu_relax();
__raw_writel(ch, IOMEM(LL_UART_PADDR + UART_FIFO_OFFSET));
}
#endif

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