mirror of
https://github.com/linux-msm/laptops-kernel.git
synced 2026-08-13 14:19:53 -07:00
Merge tag 'mips_6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux
Pull MIPS updates from Thomas Bogendoerfer:
- add support for TP-Link HC220 G5 v1
- add support for Wifi/Bluetooth on CI20
- rework Ralink clock and reset handling
- cleanups and fixes
* tag 'mips_6.5' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (58 commits)
MIPS: Loongson64: DTS: Add RTC support to Loongson-2K1000
MIPS: Loongson64: DTS: Add RTC support to LS7A PCH
MIPS: OCTEON: octeon-usb: cleanup divider calculation
MIPS: OCTEON: octeon-usb: introduce dwc3_octeon_{read,write}q
MIPS: OCTEON: octeon-usb: move gpio config to separate function
MIPS: OCTEON: octeon-usb: use bitfields for shim register
MIPS: OCTEON: octeon-usb: use bitfields for host config register
MIPS: OCTEON: octeon-usb: use bitfields for control register
MIPS: OCTEON: octeon-usb: add all register offsets
mips: ralink: match all supported system controller compatible strings
MIPS: dec: prom: Address -Warray-bounds warning
MIPS: DTS: CI20: Raise VDDCORE voltage to 1.125 volts
clk: ralink: mtmips: Fix uninitialized use of ret in mtmips_register_{fixed,factor}_clocks()
mips: ralink: introduce commonly used remap node function
mips: pci-mt7620: use dev_info() to log PCIe device detection result
mips: pci-mt7620: do not print NFTS register value as error log
MAINTAINERS: add Mediatek MTMIPS Clock maintainer
mips: ralink: get cpu rate from new driver code
mips: ralink: remove reset related code
mips: ralink: mt7620: remove clock related code
...
This commit is contained in:
Linus Torvalds
@@ -3716,8 +3716,8 @@
|
||||
|
||||
nohibernate [HIBERNATION] Disable hibernation and resume.
|
||||
|
||||
nohlt [ARM,ARM64,MICROBLAZE,SH] Forces the kernel to busy wait
|
||||
in do_idle() and not use the arch_cpu_idle()
|
||||
nohlt [ARM,ARM64,MICROBLAZE,MIPS,SH] Forces the kernel to
|
||||
busy wait in do_idle() and not use the arch_cpu_idle()
|
||||
implementation; requires CONFIG_GENERIC_IDLE_POLL_SETUP
|
||||
to be effective. This is useful on platforms where the
|
||||
sleep(SH) or wfi(ARM,ARM64) instructions do not work
|
||||
@@ -3852,7 +3852,7 @@
|
||||
nosmp [SMP] Tells an SMP kernel to act as a UP kernel,
|
||||
and disable the IO APIC. legacy for "maxcpus=0".
|
||||
|
||||
nosmt [KNL,S390] Disable symmetric multithreading (SMT).
|
||||
nosmt [KNL,MIPS,S390] Disable symmetric multithreading (SMT).
|
||||
Equivalent to smt=1.
|
||||
|
||||
[KNL,X86] Disable symmetric multithreading (SMT).
|
||||
@@ -5770,7 +5770,7 @@
|
||||
1: Fast pin select (default)
|
||||
2: ATC IRMode
|
||||
|
||||
smt= [KNL,S390] Set the maximum number of threads (logical
|
||||
smt= [KNL,MIPS,S390] Set the maximum number of threads (logical
|
||||
CPUs) to use per physical CPU on systems capable of
|
||||
symmetric multithreading (SMT). Will be capped to the
|
||||
actual hardware limit.
|
||||
|
||||
@@ -0,0 +1,64 @@
|
||||
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
%YAML 1.2
|
||||
---
|
||||
$id: http://devicetree.org/schemas/clock/mediatek,mtmips-sysc.yaml#
|
||||
$schema: http://devicetree.org/meta-schemas/core.yaml#
|
||||
|
||||
title: MTMIPS SoCs System Controller
|
||||
|
||||
maintainers:
|
||||
- Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
|
||||
description: |
|
||||
MediaTek MIPS and Ralink SoCs provides a system controller to allow
|
||||
to access to system control registers. These registers include clock
|
||||
and reset related ones so this node is both clock and reset provider
|
||||
for the rest of the world.
|
||||
|
||||
These SoCs have an XTAL from where the cpu clock is
|
||||
provided as well as derived clocks for the bus and the peripherals.
|
||||
|
||||
properties:
|
||||
compatible:
|
||||
items:
|
||||
- enum:
|
||||
- ralink,mt7620-sysc
|
||||
- ralink,mt7628-sysc
|
||||
- ralink,mt7688-sysc
|
||||
- ralink,rt2880-sysc
|
||||
- ralink,rt3050-sysc
|
||||
- ralink,rt3052-sysc
|
||||
- ralink,rt3352-sysc
|
||||
- ralink,rt3883-sysc
|
||||
- ralink,rt5350-sysc
|
||||
- const: syscon
|
||||
|
||||
reg:
|
||||
maxItems: 1
|
||||
|
||||
'#clock-cells':
|
||||
description:
|
||||
The first cell indicates the clock number.
|
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const: 1
|
||||
|
||||
'#reset-cells':
|
||||
description:
|
||||
The first cell indicates the reset bit within the register.
|
||||
const: 1
|
||||
|
||||
required:
|
||||
- compatible
|
||||
- reg
|
||||
- '#clock-cells'
|
||||
- '#reset-cells'
|
||||
|
||||
additionalProperties: false
|
||||
|
||||
examples:
|
||||
- |
|
||||
syscon@0 {
|
||||
compatible = "ralink,rt5350-sysc", "syscon";
|
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reg = <0x0 0x100>;
|
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#clock-cells = <1>;
|
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#reset-cells = <1>;
|
||||
};
|
||||
@@ -80,6 +80,7 @@ properties:
|
||||
- enum:
|
||||
- gnubee,gb-pc1
|
||||
- gnubee,gb-pc2
|
||||
- tplink,hc220-g5-v1
|
||||
- const: mediatek,mt7621-soc
|
||||
|
||||
additionalProperties: true
|
||||
|
||||
+6
-1
@@ -11442,7 +11442,6 @@ F: tools/testing/selftests/kvm/aarch64/
|
||||
|
||||
KERNEL VIRTUAL MACHINE FOR MIPS (KVM/mips)
|
||||
M: Huacai Chen <chenhuacai@kernel.org>
|
||||
M: Aleksandar Markovic <aleksandar.qemu.devel@gmail.com>
|
||||
L: linux-mips@vger.kernel.org
|
||||
L: kvm@vger.kernel.org
|
||||
S: Maintained
|
||||
@@ -13331,6 +13330,12 @@ S: Maintained
|
||||
F: Documentation/devicetree/bindings/i2c/mediatek,mt7621-i2c.yaml
|
||||
F: drivers/i2c/busses/i2c-mt7621.c
|
||||
|
||||
MEDIATEK MTMIPS CLOCK DRIVER
|
||||
M: Sergio Paracuellos <sergio.paracuellos@gmail.com>
|
||||
S: Maintained
|
||||
F: Documentation/devicetree/bindings/clock/mediatek,mtmips-sysc.yaml
|
||||
F: drivers/clk/ralink/clk-mtmips.c
|
||||
|
||||
MEDIATEK NAND CONTROLLER DRIVER
|
||||
L: linux-mtd@lists.infradead.org
|
||||
S: Orphan
|
||||
|
||||
+3
-1
@@ -45,6 +45,7 @@ config MIPS
|
||||
select GENERIC_LIB_UCMPDI2
|
||||
select GENERIC_SCHED_CLOCK if !CAVIUM_OCTEON_SOC
|
||||
select GENERIC_SMP_IDLE_THREAD
|
||||
select GENERIC_IDLE_POLL_SETUP
|
||||
select GENERIC_TIME_VSYSCALL
|
||||
select GUP_GET_PXX_LOW_HIGH if CPU_MIPS32 && PHYS_ADDR_T_64BIT
|
||||
select HAS_IOPORT if !NO_IOPORT_MAP || ISA
|
||||
@@ -80,7 +81,6 @@ config MIPS
|
||||
select HAVE_LD_DEAD_CODE_DATA_ELIMINATION
|
||||
select HAVE_MOD_ARCH_SPECIFIC
|
||||
select HAVE_NMI
|
||||
select HAVE_PATA_PLATFORM
|
||||
select HAVE_PERF_EVENTS
|
||||
select HAVE_PERF_REGS
|
||||
select HAVE_PERF_USER_STACK_DUMP
|
||||
@@ -155,9 +155,11 @@ config MIPS_GENERIC_KERNEL
|
||||
select SWAP_IO_SPACE
|
||||
select SYS_HAS_CPU_MIPS32_R1
|
||||
select SYS_HAS_CPU_MIPS32_R2
|
||||
select SYS_HAS_CPU_MIPS32_R5
|
||||
select SYS_HAS_CPU_MIPS32_R6
|
||||
select SYS_HAS_CPU_MIPS64_R1
|
||||
select SYS_HAS_CPU_MIPS64_R2
|
||||
select SYS_HAS_CPU_MIPS64_R5
|
||||
select SYS_HAS_CPU_MIPS64_R6
|
||||
select SYS_SUPPORTS_32BIT_KERNEL
|
||||
select SYS_SUPPORTS_64BIT_KERNEL
|
||||
|
||||
@@ -14,6 +14,7 @@ config MIPS_DB1XXX
|
||||
bool "Alchemy DB1XXX / PB1XXX boards"
|
||||
select GPIOLIB
|
||||
select HAVE_PCI
|
||||
select HAVE_PATA_PLATFORM
|
||||
select SYS_SUPPORTS_LITTLE_ENDIAN
|
||||
select SYS_HAS_EARLY_PRINTK
|
||||
help
|
||||
|
||||
@@ -67,14 +67,14 @@
|
||||
};
|
||||
};
|
||||
|
||||
eth0_power: fixedregulator@0 {
|
||||
eth0_power: fixedregulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "eth0_power";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
|
||||
gpio = <&gpb 25 GPIO_ACTIVE_LOW>;
|
||||
gpio = <&gpb 25 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
@@ -97,25 +97,64 @@
|
||||
gpios = <&gpe 3 GPIO_ACTIVE_LOW>;
|
||||
};
|
||||
|
||||
wlan0_power: fixedregulator@1 {
|
||||
bt_power: fixedregulator-1 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "wlan0_power";
|
||||
regulator-name = "bt_power";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-settling-time-us = <1400>;
|
||||
|
||||
gpio = <&gpb 19 GPIO_ACTIVE_LOW>;
|
||||
vin-supply = <&vcc_50>;
|
||||
|
||||
gpio = <&gpb 19 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
otg_power: fixedregulator@2 {
|
||||
otg_power: fixedregulator-2 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "otg_power";
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
|
||||
gpio = <&gpf 15 GPIO_ACTIVE_LOW>;
|
||||
gpio = <&gpf 15 0>;
|
||||
enable-active-high;
|
||||
};
|
||||
|
||||
wifi_power: fixedregulator-4 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "wifi_power";
|
||||
|
||||
/*
|
||||
* Technically it's 5V, the WiFi chip has its own internal
|
||||
* regulators; but the MMC/SD subsystem won't accept such a
|
||||
* value.
|
||||
*/
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-settling-time-us = <150000>;
|
||||
|
||||
vin-supply = <&bt_power>;
|
||||
};
|
||||
|
||||
vcc_33v: fixedregulator-5 {
|
||||
compatible = "regulator-fixed";
|
||||
|
||||
regulator-name = "vcc_33v";
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
wifi_pwrseq: pwrseq {
|
||||
compatible = "mmc-pwrseq-simple";
|
||||
reset-gpios = <&gpf 7 GPIO_ACTIVE_LOW>;
|
||||
|
||||
clocks = <&rtc_dev>;
|
||||
clock-names = "ext_clock";
|
||||
};
|
||||
};
|
||||
|
||||
&ext {
|
||||
@@ -129,10 +168,11 @@
|
||||
*/
|
||||
assigned-clocks = <&cgu JZ4780_CLK_OTGPHY>, <&cgu JZ4780_CLK_RTC>,
|
||||
<&cgu JZ4780_CLK_SSIPLL>, <&cgu JZ4780_CLK_SSI>,
|
||||
<&cgu JZ4780_CLK_HDMI>;
|
||||
<&cgu JZ4780_CLK_HDMI>, <&cgu JZ4780_CLK_MSCMUX>;
|
||||
assigned-clock-parents = <0>, <&cgu JZ4780_CLK_RTCLK>,
|
||||
<&cgu JZ4780_CLK_MPLL>,
|
||||
<&cgu JZ4780_CLK_SSIPLL>;
|
||||
<&cgu JZ4780_CLK_SSIPLL>,
|
||||
<0>, <&cgu JZ4780_CLK_MPLL>;
|
||||
assigned-clock-rates = <48000000>, <0>, <54000000>, <0>, <27000000>;
|
||||
};
|
||||
|
||||
@@ -160,24 +200,33 @@
|
||||
pinctrl-0 = <&pins_mmc0>;
|
||||
|
||||
cd-gpios = <&gpf 20 GPIO_ACTIVE_LOW>;
|
||||
vmmc-supply = <&vcc_33v>;
|
||||
vqmmc-supply = <&vcc_33v>;
|
||||
};
|
||||
|
||||
&mmc1 {
|
||||
status = "okay";
|
||||
|
||||
bus-width = <4>;
|
||||
max-frequency = <50000000>;
|
||||
max-frequency = <25000000>;
|
||||
mmc-pwrseq = <&wifi_pwrseq>;
|
||||
vmmc-supply = <&wifi_power>;
|
||||
vqmmc-supply = <&wifi_io>;
|
||||
non-removable;
|
||||
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_mmc1>;
|
||||
|
||||
brcmf: wifi@1 {
|
||||
/* reg = <4>;*/
|
||||
compatible = "brcm,bcm4330-fmac";
|
||||
vcc-supply = <&wlan0_power>;
|
||||
device-wakeup-gpios = <&gpd 9 GPIO_ACTIVE_HIGH>;
|
||||
shutdown-gpios = <&gpf 7 GPIO_ACTIVE_LOW>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
wifi@1 {
|
||||
compatible = "brcm,bcm4329-fmac";
|
||||
reg = <1>;
|
||||
|
||||
interrupt-parent = <&gpd>;
|
||||
interrupts = <9 IRQ_TYPE_EDGE_FALLING>;
|
||||
interrupt-names = "host-wake";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -204,11 +253,20 @@
|
||||
|
||||
bluetooth {
|
||||
compatible = "brcm,bcm4330-bt";
|
||||
reset-gpios = <&gpf 8 GPIO_ACTIVE_HIGH>;
|
||||
vcc-supply = <&wlan0_power>;
|
||||
|
||||
vbat-supply = <&bt_power>;
|
||||
vddio-supply = <&wifi_io>;
|
||||
|
||||
interrupt-parent = <&gpf>;
|
||||
interrupts = <6 IRQ_TYPE_EDGE_RISING>;
|
||||
interrupt-names = "host-wakeup";
|
||||
|
||||
clocks = <&rtc_dev>;
|
||||
clock-names = "lpo";
|
||||
|
||||
reset-gpios = <&gpf 8 GPIO_ACTIVE_LOW>;
|
||||
device-wakeup-gpios = <&gpf 5 GPIO_ACTIVE_HIGH>;
|
||||
host-wakeup-gpios = <&gpf 6 GPIO_ACTIVE_HIGH>;
|
||||
shutdown-gpios = <&gpf 4 GPIO_ACTIVE_LOW>;
|
||||
shutdown-gpios = <&gpf 4 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
|
||||
@@ -237,59 +295,54 @@
|
||||
act8600: act8600@5a {
|
||||
compatible = "active-semi,act8600";
|
||||
reg = <0x5a>;
|
||||
status = "okay";
|
||||
|
||||
regulators {
|
||||
vddcore: SUDCDC1 {
|
||||
regulator-name = "DCDC_REG1";
|
||||
regulator-min-microvolt = <1100000>;
|
||||
regulator-max-microvolt = <1100000>;
|
||||
vddcore: DCDC1 {
|
||||
regulator-min-microvolt = <1125000>;
|
||||
regulator-max-microvolt = <1125000>;
|
||||
vp1-supply = <&vcc_33v>;
|
||||
regulator-always-on;
|
||||
};
|
||||
vddmem: SUDCDC2 {
|
||||
regulator-name = "DCDC_REG2";
|
||||
vddmem: DCDC2 {
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
vp2-supply = <&vcc_33v>;
|
||||
regulator-always-on;
|
||||
};
|
||||
vcc_33: SUDCDC3 {
|
||||
regulator-name = "DCDC_REG3";
|
||||
vcc_33: DCDC3 {
|
||||
regulator-min-microvolt = <3300000>;
|
||||
regulator-max-microvolt = <3300000>;
|
||||
vp3-supply = <&vcc_33v>;
|
||||
regulator-always-on;
|
||||
};
|
||||
vcc_50: SUDCDC4 {
|
||||
regulator-name = "SUDCDC_REG4";
|
||||
vcc_50: SUDCDC_REG4 {
|
||||
regulator-min-microvolt = <5000000>;
|
||||
regulator-max-microvolt = <5000000>;
|
||||
regulator-always-on;
|
||||
};
|
||||
vcc_25: LDO_REG5 {
|
||||
regulator-name = "LDO_REG5";
|
||||
vcc_25: LDO5 {
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
inl-supply = <&vcc_33v>;
|
||||
regulator-always-on;
|
||||
};
|
||||
wifi_io: LDO_REG6 {
|
||||
regulator-name = "LDO_REG6";
|
||||
regulator-min-microvolt = <2500000>;
|
||||
regulator-max-microvolt = <2500000>;
|
||||
regulator-always-on;
|
||||
wifi_io: LDO6 {
|
||||
regulator-min-microvolt = <1800000>;
|
||||
regulator-max-microvolt = <1800000>;
|
||||
regulator-settling-time-us = <150000>;
|
||||
inl-supply = <&vcc_33v>;
|
||||
};
|
||||
vcc_28: LDO_REG7 {
|
||||
regulator-name = "LDO_REG7";
|
||||
cim_io_28: LDO7 {
|
||||
regulator-min-microvolt = <2800000>;
|
||||
regulator-max-microvolt = <2800000>;
|
||||
regulator-always-on;
|
||||
inl-supply = <&vcc_33v>;
|
||||
};
|
||||
vcc_15: LDO_REG8 {
|
||||
regulator-name = "LDO_REG8";
|
||||
cim_io_15: LDO8 {
|
||||
regulator-min-microvolt = <1500000>;
|
||||
regulator-max-microvolt = <1500000>;
|
||||
regulator-always-on;
|
||||
inl-supply = <&vcc_33v>;
|
||||
};
|
||||
vrtc_18: LDO_REG9 {
|
||||
regulator-name = "LDO_REG9";
|
||||
/* Despite the datasheet stating 3.3V
|
||||
* for REG9 and the driver expecting that,
|
||||
* REG9 outputs 1.8V.
|
||||
@@ -303,7 +356,6 @@
|
||||
regulator-always-on;
|
||||
};
|
||||
vcc_11: LDO_REG10 {
|
||||
regulator-name = "LDO_REG10";
|
||||
regulator-min-microvolt = <1200000>;
|
||||
regulator-max-microvolt = <1200000>;
|
||||
regulator-always-on;
|
||||
@@ -363,7 +415,7 @@
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
ingenic,bch-controller = <&bch>;
|
||||
ecc-engine = <&bch>;
|
||||
|
||||
ingenic,nemc-tAS = <10>;
|
||||
ingenic,nemc-tAH = <5>;
|
||||
@@ -429,8 +481,8 @@
|
||||
pinctrl-names = "default";
|
||||
pinctrl-0 = <&pins_nemc_cs6>;
|
||||
|
||||
reg = <6 0 1 /* addr */
|
||||
6 2 1>; /* data */
|
||||
reg = <6 0 1>, /* addr */
|
||||
<6 2 1>; /* data */
|
||||
|
||||
ingenic,nemc-tAS = <15>;
|
||||
ingenic,nemc-tAH = <10>;
|
||||
@@ -442,7 +494,7 @@
|
||||
vcc-supply = <ð0_power>;
|
||||
|
||||
interrupt-parent = <&gpe>;
|
||||
interrupts = <19 4>;
|
||||
interrupts = <19 IRQ_TYPE_EDGE_RISING>;
|
||||
|
||||
nvmem-cells = <ð0_addr>;
|
||||
nvmem-cell-names = "mac-address";
|
||||
|
||||
@@ -198,11 +198,8 @@
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
clocks = <&cgu JZ4725B_CLK_AIC>,
|
||||
<&cgu JZ4725B_CLK_I2S>,
|
||||
<&cgu JZ4725B_CLK_EXT>,
|
||||
<&cgu JZ4725B_CLK_PLL_HALF>;
|
||||
clock-names = "aic", "i2s", "ext", "pll half";
|
||||
clocks = <&cgu JZ4725B_CLK_AIC>, <&cgu JZ4725B_CLK_I2S>;
|
||||
clock-names = "aic", "i2s";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <10>;
|
||||
|
||||
@@ -192,11 +192,8 @@
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <18>;
|
||||
|
||||
clocks = <&cgu JZ4740_CLK_AIC>,
|
||||
<&cgu JZ4740_CLK_I2S>,
|
||||
<&cgu JZ4740_CLK_EXT>,
|
||||
<&cgu JZ4740_CLK_PLL_HALF>;
|
||||
clock-names = "aic", "i2s", "ext", "pll half";
|
||||
clocks = <&cgu JZ4740_CLK_AIC>, <&cgu JZ4740_CLK_I2S>;
|
||||
clock-names = "aic", "i2s";
|
||||
|
||||
dmas = <&dmac 25 0xffffffff>, <&dmac 24 0xffffffff>;
|
||||
dma-names = "rx", "tx";
|
||||
|
||||
@@ -238,9 +238,8 @@
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>,
|
||||
<&cgu JZ4770_CLK_EXT>, <&cgu JZ4770_CLK_PLL0>;
|
||||
clock-names = "aic", "i2s", "ext", "pll half";
|
||||
clocks = <&cgu JZ4770_CLK_AIC>, <&cgu JZ4770_CLK_I2S>;
|
||||
clock-names = "aic", "i2s";
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <34>;
|
||||
|
||||
@@ -27,7 +27,7 @@
|
||||
stdout-path = &uart0;
|
||||
};
|
||||
|
||||
vcc: regulator@0 {
|
||||
vcc: regulator-0 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "vcc";
|
||||
|
||||
@@ -36,7 +36,7 @@
|
||||
regulator-always-on;
|
||||
};
|
||||
|
||||
mmc_power: regulator@1 {
|
||||
mmc_power: regulator-1 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "mmc_vcc";
|
||||
gpio = <&gpd 2 0>;
|
||||
@@ -45,7 +45,7 @@
|
||||
regulator-max-microvolt = <3300000>;
|
||||
};
|
||||
|
||||
amp_supply: regulator@2 {
|
||||
amp_supply: regulator-2 {
|
||||
compatible = "regulator-fixed";
|
||||
regulator-name = "amp_supply";
|
||||
gpio = <&gpd 4 0>;
|
||||
|
||||
@@ -417,4 +417,22 @@
|
||||
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
aic: audio-controller@10020000 {
|
||||
compatible = "ingenic,x1000-i2s";
|
||||
reg = <0x10020000 0x38>;
|
||||
|
||||
#sound-dai-cells = <0>;
|
||||
|
||||
interrupt-parent = <&intc>;
|
||||
interrupts = <1>;
|
||||
|
||||
clocks = <&cgu X1000_CLK_AIC>,
|
||||
<&cgu X1000_CLK_I2S>;
|
||||
clock-names = "aic", "i2s";
|
||||
|
||||
dmas = <&pdma X1000_DMA_I2S0_RX 0xffffffff>,
|
||||
<&pdma X1000_DMA_I2S0_TX 0xffffffff>;
|
||||
dma-names = "rx", "tx";
|
||||
};
|
||||
};
|
||||
|
||||
@@ -97,6 +97,13 @@
|
||||
<0x00000000>; /* int3 */
|
||||
};
|
||||
|
||||
rtc0: rtc@1fe07800 {
|
||||
compatible = "loongson,ls2k1000-rtc";
|
||||
reg = <0 0x1fe07800 0 0x78>;
|
||||
interrupt-parent = <&liointc0>;
|
||||
interrupts = <60 IRQ_TYPE_LEVEL_LOW>;
|
||||
};
|
||||
|
||||
uart0: serial@1fe00000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0 0x1fe00000 0 0x8>;
|
||||
|
||||
@@ -19,6 +19,13 @@
|
||||
#interrupt-cells = <2>;
|
||||
};
|
||||
|
||||
rtc0: rtc@100d0100 {
|
||||
compatible = "loongson,ls7a-rtc";
|
||||
reg = <0 0x100d0100 0 0x78>;
|
||||
interrupt-parent = <&pic>;
|
||||
interrupts = <52 IRQ_TYPE_LEVEL_HIGH>;
|
||||
};
|
||||
|
||||
ls7a_uart0: serial@10080000 {
|
||||
compatible = "ns16550a";
|
||||
reg = <0 0x10080000 0 0x100>;
|
||||
|
||||
@@ -8,6 +8,7 @@ dtb-$(CONFIG_DTB_VOCORE2) += vocore2.dtb
|
||||
|
||||
dtb-$(CONFIG_SOC_MT7621) += \
|
||||
mt7621-gnubee-gb-pc1.dtb \
|
||||
mt7621-gnubee-gb-pc2.dtb
|
||||
mt7621-gnubee-gb-pc2.dtb \
|
||||
mt7621-tplink-hc220-g5-v1.dtb
|
||||
|
||||
obj-$(CONFIG_BUILTIN_DTB) += $(addsuffix .o, $(dtb-y))
|
||||
|
||||
@@ -0,0 +1,84 @@
|
||||
// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
|
||||
/dts-v1/;
|
||||
|
||||
#include "mt7621.dtsi"
|
||||
|
||||
#include <dt-bindings/gpio/gpio.h>
|
||||
#include <dt-bindings/input/input.h>
|
||||
#include <dt-bindings/leds/common.h>
|
||||
|
||||
/ {
|
||||
compatible = "tplink,hc220-g5-v1", "mediatek,mt7621-soc";
|
||||
model = "TP-Link HC220 G5 v1";
|
||||
|
||||
memory@0 {
|
||||
device_type = "memory";
|
||||
reg = <0x00000000 0x08000000>;
|
||||
};
|
||||
|
||||
chosen {
|
||||
bootargs = "earlycon console=ttyS0,115200";
|
||||
};
|
||||
|
||||
gpio-keys {
|
||||
compatible = "gpio-keys";
|
||||
|
||||
key-reset {
|
||||
label = "reset";
|
||||
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_RESTART>;
|
||||
};
|
||||
|
||||
key-wps {
|
||||
label = "wps";
|
||||
gpios = <&gpio 16 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WPS_BUTTON>;
|
||||
};
|
||||
};
|
||||
|
||||
leds {
|
||||
compatible = "gpio-leds";
|
||||
|
||||
led-fault {
|
||||
color = <LED_COLOR_ID_RED>;
|
||||
function = LED_FUNCTION_FAULT;
|
||||
gpios = <&gpio 13 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
|
||||
led-power {
|
||||
color = <LED_COLOR_ID_GREEN>;
|
||||
function = LED_FUNCTION_POWER;
|
||||
gpios = <&gpio 14 GPIO_ACTIVE_HIGH>;
|
||||
linux,default-trigger = "default-on";
|
||||
};
|
||||
|
||||
led-wps {
|
||||
color = <LED_COLOR_ID_BLUE>;
|
||||
function = LED_FUNCTION_WPS;
|
||||
gpios = <&gpio 15 GPIO_ACTIVE_HIGH>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
&pcie {
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&switch0 {
|
||||
ports {
|
||||
port@0 {
|
||||
status = "okay";
|
||||
label = "lan2";
|
||||
};
|
||||
|
||||
port@1 {
|
||||
status = "okay";
|
||||
label = "lan1";
|
||||
};
|
||||
|
||||
port@2 {
|
||||
status = "okay";
|
||||
label = "wan";
|
||||
};
|
||||
};
|
||||
};
|
||||
@@ -51,85 +51,85 @@
|
||||
pinctrl-single,register-width = <32>;
|
||||
pinctrl-single,function-mask = <0x1>;
|
||||
|
||||
pinmux_gpio_gpio: pinmux_gpio_gpio {
|
||||
pinmux_gpio_gpio: gpio-gpio-pins {
|
||||
pinctrl-single,bits = <0x0 0x0 0x3>;
|
||||
};
|
||||
|
||||
pinmux_spi_cs1_cs: pinmux_spi_cs1_cs {
|
||||
pinmux_spi_cs1_cs: spi-cs1-cs-pins {
|
||||
pinctrl-single,bits = <0x0 0x0 0x30>;
|
||||
};
|
||||
|
||||
pinmux_i2s_gpio: pinmux_i2s_gpio {
|
||||
pinmux_i2s_gpio: i2s-gpio-pins {
|
||||
pinctrl-single,bits = <0x0 0x40 0xc0>;
|
||||
};
|
||||
|
||||
pinmux_uart0_uart: pinmux_uart0_uart0 {
|
||||
pinmux_uart0_uart: uart0-uart0-pins {
|
||||
pinctrl-single,bits = <0x0 0x0 0x300>;
|
||||
};
|
||||
|
||||
pinmux_sdmode_sdxc: pinmux_sdmode_sdxc {
|
||||
pinmux_sdmode_sdxc: sdmode-sdxc-pins {
|
||||
pinctrl-single,bits = <0x0 0x0 0xc00>;
|
||||
};
|
||||
|
||||
pinmux_sdmode_gpio: pinmux_sdmode_gpio {
|
||||
pinmux_sdmode_gpio: sdmode-gpio-pins {
|
||||
pinctrl-single,bits = <0x0 0x400 0xc00>;
|
||||
};
|
||||
|
||||
pinmux_spi_spi: pinmux_spi_spi {
|
||||
pinmux_spi_spi: spi-spi-pins {
|
||||
pinctrl-single,bits = <0x0 0x0 0x1000>;
|
||||
};
|
||||
|
||||
pinmux_refclk_gpio: pinmux_refclk_gpio {
|
||||
pinmux_refclk_gpio: refclk-gpio-pins {
|
||||
pinctrl-single,bits = <0x0 0x40000 0x40000>;
|
||||
};
|
||||
|
||||
pinmux_i2c_i2c: pinmux_i2c_i2c {
|
||||
pinmux_i2c_i2c: i2c-i2c-pins {
|
||||
pinctrl-single,bits = <0x0 0x0 0x300000>;
|
||||
};
|
||||
|
||||
pinmux_uart1_uart: pinmux_uart1_uart1 {
|
||||
pinmux_uart1_uart: uart1-uart1-pins {
|
||||
pinctrl-single,bits = <0x0 0x0 0x3000000>;
|
||||
};
|
||||
|
||||
pinmux_uart2_uart: pinmux_uart2_uart {
|
||||
pinmux_uart2_uart: uart2-uart-pins {
|
||||
pinctrl-single,bits = <0x0 0x0 0xc000000>;
|
||||
};
|
||||
|
||||
pinmux_pwm0_pwm: pinmux_pwm0_pwm {
|
||||
pinmux_pwm0_pwm: pwm0-pwm-pins {
|
||||
pinctrl-single,bits = <0x0 0x0 0x30000000>;
|
||||
};
|
||||
|
||||
pinmux_pwm0_gpio: pinmux_pwm0_gpio {
|
||||
pinmux_pwm0_gpio: pwm0-gpio-pins {
|
||||
pinctrl-single,bits = <0x0 0x10000000
|
||||
0x30000000>;
|
||||
};
|
||||
|
||||
pinmux_pwm1_pwm: pinmux_pwm1_pwm {
|
||||
pinmux_pwm1_pwm: pwm1-pwm-pins {
|
||||
pinctrl-single,bits = <0x0 0x0 0xc0000000>;
|
||||
};
|
||||
|
||||
pinmux_pwm1_gpio: pinmux_pwm1_gpio {
|
||||
pinmux_pwm1_gpio: pwm1-gpio-pins {
|
||||
pinctrl-single,bits = <0x0 0x40000000
|
||||
0xc0000000>;
|
||||
};
|
||||
|
||||
pinmux_p0led_an_gpio: pinmux_p0led_an_gpio {
|
||||
pinmux_p0led_an_gpio: p0led-an-gpio-pins {
|
||||
pinctrl-single,bits = <0x4 0x4 0xc>;
|
||||
};
|
||||
|
||||
pinmux_p1led_an_gpio: pinmux_p1led_an_gpio {
|
||||
pinmux_p1led_an_gpio: p1led-an-gpio-pins {
|
||||
pinctrl-single,bits = <0x4 0x10 0x30>;
|
||||
};
|
||||
|
||||
pinmux_p2led_an_gpio: pinmux_p2led_an_gpio {
|
||||
pinmux_p2led_an_gpio: p2led-an-gpio-pins {
|
||||
pinctrl-single,bits = <0x4 0x40 0xc0>;
|
||||
};
|
||||
|
||||
pinmux_p3led_an_gpio: pinmux_p3led_an_gpio {
|
||||
pinmux_p3led_an_gpio: p3led-an-gpio-pins {
|
||||
pinctrl-single,bits = <0x4 0x100 0x300>;
|
||||
};
|
||||
|
||||
pinmux_p4led_an_gpio: pinmux_p4led_an_gpio {
|
||||
pinmux_p4led_an_gpio: p4led-an-gpio-pins {
|
||||
pinctrl-single,bits = <0x4 0x400 0xc00>;
|
||||
};
|
||||
};
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@@ -19,19 +19,19 @@ CONFIG_USER_NS=y
|
||||
CONFIG_CC_OPTIMIZE_FOR_SIZE=y
|
||||
CONFIG_KALLSYMS_ALL=y
|
||||
CONFIG_EMBEDDED=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
CONFIG_SLAB=y
|
||||
CONFIG_MACH_INGENIC_SOC=y
|
||||
CONFIG_JZ4780_CI20=y
|
||||
CONFIG_HIGHMEM=y
|
||||
CONFIG_HZ_100=y
|
||||
# CONFIG_SECCOMP is not set
|
||||
# CONFIG_SUSPEND is not set
|
||||
# CONFIG_SECCOMP is not set
|
||||
CONFIG_MODULES=y
|
||||
# CONFIG_CORE_DUMP_DEFAULT_ELF_HEADERS is not set
|
||||
CONFIG_SLAB=y
|
||||
# CONFIG_COMPAT_BRK is not set
|
||||
# CONFIG_COMPACTION is not set
|
||||
CONFIG_CMA=y
|
||||
# CONFIG_VM_EVENT_COUNTERS is not set
|
||||
CONFIG_NET=y
|
||||
CONFIG_PACKET=y
|
||||
CONFIG_UNIX=y
|
||||
@@ -40,7 +40,12 @@ CONFIG_IP_PNP=y
|
||||
CONFIG_IP_PNP_DHCP=y
|
||||
# CONFIG_INET_DIAG is not set
|
||||
# CONFIG_IPV6 is not set
|
||||
# CONFIG_WIRELESS is not set
|
||||
CONFIG_BT=m
|
||||
# CONFIG_BT_LE is not set
|
||||
CONFIG_BT_HCIUART=m
|
||||
CONFIG_BT_HCIUART_BCM=y
|
||||
CONFIG_CFG80211=m
|
||||
CONFIG_CFG80211_WEXT=y
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_FW_LOADER=m
|
||||
# CONFIG_ALLOW_DEV_COREDUMP is not set
|
||||
@@ -68,10 +73,27 @@ CONFIG_DM9000_FORCE_SIMPLE_PHY_POLL=y
|
||||
# CONFIG_NET_VENDOR_STMICRO is not set
|
||||
# CONFIG_NET_VENDOR_VIA is not set
|
||||
# CONFIG_NET_VENDOR_WIZNET is not set
|
||||
# CONFIG_WLAN is not set
|
||||
# CONFIG_WLAN_VENDOR_ADMTEK is not set
|
||||
# CONFIG_WLAN_VENDOR_ATH is not set
|
||||
# CONFIG_WLAN_VENDOR_ATMEL is not set
|
||||
CONFIG_BRCMFMAC=m
|
||||
# CONFIG_WLAN_VENDOR_CISCO is not set
|
||||
# CONFIG_WLAN_VENDOR_INTEL is not set
|
||||
# CONFIG_WLAN_VENDOR_INTERSIL is not set
|
||||
# CONFIG_WLAN_VENDOR_MARVELL is not set
|
||||
# CONFIG_WLAN_VENDOR_MEDIATEK is not set
|
||||
# CONFIG_WLAN_VENDOR_MICROCHIP is not set
|
||||
# CONFIG_WLAN_VENDOR_PURELIFI is not set
|
||||
# CONFIG_WLAN_VENDOR_RALINK is not set
|
||||
# CONFIG_WLAN_VENDOR_REALTEK is not set
|
||||
# CONFIG_WLAN_VENDOR_RSI is not set
|
||||
# CONFIG_WLAN_VENDOR_SILABS is not set
|
||||
# CONFIG_WLAN_VENDOR_ST is not set
|
||||
# CONFIG_WLAN_VENDOR_TI is not set
|
||||
# CONFIG_WLAN_VENDOR_ZYDAS is not set
|
||||
# CONFIG_WLAN_VENDOR_QUANTENNA is not set
|
||||
CONFIG_KEYBOARD_GPIO=m
|
||||
# CONFIG_INPUT_MOUSE is not set
|
||||
CONFIG_VT_HW_CONSOLE_BINDING=y
|
||||
CONFIG_LEGACY_PTY_COUNT=2
|
||||
CONFIG_SERIAL_8250=y
|
||||
CONFIG_SERIAL_8250_CONSOLE=y
|
||||
@@ -79,6 +101,7 @@ CONFIG_SERIAL_8250_NR_UARTS=5
|
||||
CONFIG_SERIAL_8250_RUNTIME_UARTS=5
|
||||
CONFIG_SERIAL_8250_INGENIC=y
|
||||
CONFIG_SERIAL_OF_PLATFORM=y
|
||||
CONFIG_SERIAL_DEV_BUS=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_JZ4780=y
|
||||
CONFIG_SPI=y
|
||||
@@ -99,13 +122,12 @@ CONFIG_IR_GPIO_CIR=m
|
||||
CONFIG_IR_GPIO_TX=m
|
||||
CONFIG_MEDIA_SUPPORT=m
|
||||
CONFIG_DRM=m
|
||||
CONFIG_DRM_DISPLAY_CONNECTOR=m
|
||||
CONFIG_DRM_INGENIC=m
|
||||
CONFIG_DRM_INGENIC_DW_HDMI=m
|
||||
CONFIG_DRM_DISPLAY_CONNECTOR=m
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FB=y
|
||||
# CONFIG_VGA_CONSOLE is not set
|
||||
CONFIG_FRAMEBUFFER_CONSOLE=y
|
||||
# CONFIG_HID is not set
|
||||
CONFIG_USB=y
|
||||
CONFIG_USB_STORAGE=y
|
||||
CONFIG_USB_DWC2=y
|
||||
@@ -125,7 +147,6 @@ CONFIG_LEDS_TRIGGER_HEARTBEAT=y
|
||||
CONFIG_LEDS_TRIGGER_BACKLIGHT=m
|
||||
CONFIG_LEDS_TRIGGER_CPU=y
|
||||
CONFIG_LEDS_TRIGGER_ACTIVITY=y
|
||||
CONFIG_LEDS_TRIGGER_GPIO=y
|
||||
CONFIG_LEDS_TRIGGER_DEFAULT_ON=y
|
||||
CONFIG_LEDS_TRIGGER_TRANSIENT=y
|
||||
CONFIG_LEDS_TRIGGER_CAMERA=m
|
||||
@@ -144,7 +165,6 @@ CONFIG_JZ4780_NEMC=y
|
||||
CONFIG_PWM=y
|
||||
CONFIG_PWM_JZ4740=m
|
||||
CONFIG_NVMEM_JZ4780_EFUSE=y
|
||||
CONFIG_JZ4770_PHY=y
|
||||
CONFIG_EXT4_FS=y
|
||||
# CONFIG_DNOTIFY is not set
|
||||
CONFIG_AUTOFS_FS=y
|
||||
@@ -157,7 +177,6 @@ CONFIG_CONFIGFS_FS=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NLS=y
|
||||
CONFIG_NLS_CODEPAGE_437=y
|
||||
CONFIG_NLS_CODEPAGE_737=y
|
||||
CONFIG_NLS_CODEPAGE_775=y
|
||||
@@ -196,6 +215,7 @@ CONFIG_NLS_ISO8859_15=y
|
||||
CONFIG_NLS_KOI8_R=y
|
||||
CONFIG_NLS_KOI8_U=y
|
||||
CONFIG_NLS_UTF8=y
|
||||
# CONFIG_CRYPTO_AES is not set
|
||||
CONFIG_DMA_CMA=y
|
||||
CONFIG_CMA_SIZE_MBYTES=32
|
||||
CONFIG_PRINTK_TIME=y
|
||||
@@ -206,7 +226,6 @@ CONFIG_DEBUG_FS=y
|
||||
CONFIG_PANIC_ON_OOPS=y
|
||||
CONFIG_PANIC_TIMEOUT=10
|
||||
# CONFIG_SCHED_DEBUG is not set
|
||||
# CONFIG_DEBUG_PREEMPT is not set
|
||||
CONFIG_STACKTRACE=y
|
||||
# CONFIG_FTRACE is not set
|
||||
CONFIG_CMDLINE_BOOL=y
|
||||
|
||||
@@ -276,6 +276,13 @@ CONFIG_MEDIA_SUPPORT=m
|
||||
CONFIG_MEDIA_USB_SUPPORT=y
|
||||
CONFIG_USB_VIDEO_CLASS=m
|
||||
CONFIG_DRM=y
|
||||
CONFIG_DRM_AMDGPU=m
|
||||
CONFIG_DRM_AMDGPU_SI=y
|
||||
CONFIG_DRM_AMDGPU_CIK=y
|
||||
CONFIG_DRM_AMDGPU_USERPTR=y
|
||||
CONFIG_DRM_AMD_ACP=y
|
||||
CONFIG_DRM_AMD_DC=y
|
||||
CONFIG_DRM_AMD_DC_SI=y
|
||||
CONFIG_DRM_RADEON=m
|
||||
CONFIG_DRM_QXL=y
|
||||
CONFIG_DRM_VIRTIO_GPU=y
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user